RENESAS M66596FP

M66596FP/WG
ASSP (USB2.0 Dual Function Controller)
REJ03F0119-0100Z
Rev 1.00
2006.3.14
1 Overview
1.1 Overview
The M66596 is a USB (Universal Serial Bus) Rev. 2.0 host and peripheral controller that supports USB Hi-Speed
and Full-Speed transfers. This controller has a built-in USB transceiver and supports all of the transfer types defined
by the USB specification. M66596 has a compact package and is pin compatible with the peripheral controller
M66592.
The M66596 has a 5 kB built-in buffer memory for data transfers and enables use of up to eight pipes. For pipes 1
to 7, any endpoint numbers can be assigned, based on the user’s system. The controller can be connected to the CPU
using either a separate bus or a multiplex bus. Moreover, a split bus interface (dedicated external DMA interface) is
provided independent of the CPU bus interface, making this an ideal choice for systems that require transfer of large
volumes of data at high speed.
1.2 Features
1.2.1
Built in USB Hi-Speed host and peripheral controller
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•
•
•
1.2.2
USB Hi-Speed host and peripheral controllers are built in 1 chip.
Both Hi-Speed transfer (480Mbps) and Full-Speed transfer (12Mbps) are supported
It is possible to change host or peripheral mode by register setup.
Built-in Hi-Speed / Full-Speed USB transceiver
Reduced power consumption
•
•
•
1.2.3
Small package
•
•
•
1.2.4
1.5 V core power supply, and selectable bus interface power supply 3.3V or 1.8V.
Low power consumption makes this ideal for mobile devices
Low-power mode (power-saving sleep state) supported to reduce power consumption during suspended
operation
Compact 64-pin package used
Pin compatible with Renesas Technology Hi-Speed peripheral controller M66596.
Few external elements are used, so less space is required for mounting
- VBUS signal can be connected directly to the controller pin
- Built-in D+ pull-up resistor(Peripheral mode)
- Built-in D+ and D- pull-down resistor(Host mode)
- Built-in D+ and D- terminating resistors (for Hi-Speed operation)
- Built-in D+ and D- output resistors (for Full-Speed operation)
Isochronous transfer supported
All types of USB transfers supported
- Control transfers
- Bulk transfers
- Interrupt transfers (High-Bandwidth transfers are not supported)
- Isochronous transfers (High-Bandwidth transfers are not supported)
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M66596FP/WG
1.2.5
Bus interfaces
•
•
The user can select either a 1.8 V or 3.3 V bus interface power supply
16-bit CPU bus interface
- 16-bit separate bus and 16-bit multiplex bus supported
- 8 and 16-bit DMA interface (slave function) supported
8-bit split bus (dedicated external DMA interface) supported
Built-in two DMA interface channels
DMA transfer enables high-speed access of 40 MB/sec.
•
•
•
1.2.6
Pipe configuration
•
•
•
•
•
1.2.7
Built-in 5 KB buffer memory for USB communication
Up to 8 pipes(endpoints) can be selected (including the default control pipe for endpoint 0)
Programmable pipe configuration
End point numbers can be assigned to pipe 1-7.
Transfer conditions that can be set for each pipes
- Pipe 0: Control transfer, continuous transfer mode, 256-byte fixed single buffer
- Pipe 1 and 2: Bulk transfer or isochronous transfer, continuous transfer mode, programmable buffer size
(up to 2 KB; double buffer can be selected)
- Pipe 3 to 5: Bulk transfer, continuous transfer mode, programmable buffer size
(up to 2 KB; double buffer can be selected)
- Pipe 6 and 7: Interrupt transfer, 64-byte fixed single buffer
Feature in host mode
•
•
•
1.2.8
Capable of USB Hi-Speed transfer to one peripheral device.
Automatic schedule to send SOF and transaction.
Automatic schedule interval of isochronous trenasfer and interrupt transfer.
Feature in peripheral mode
•
•
•
•
1.2.9
Control transfer stage control function
Device state control function
Auto response function for SET_ADDRESS request
NAK response assignment function (NRDY)
Other functions
•
•
•
•
•
•
•
•
•
•
•
•
Automatic recognition of Hi-Speed operation or Full-Speed operation based on automatic response to the reset
handshake
Byte endian swap function when using 16-bit data transfers
Transfer termination function when using transaction count function.
DMA transfer termination function using external trigger (DEND pin)
SOF interpolation function
SOF pulse output function
Three types of input clocks can built into the PLL and are available for selection
- Input clocks of 48 MHz / 24 MHz / 12 MHz can be selected
Zero-Length packet addition function (DEZPM) when ending DMA transfers using the DEND pin
BRDY interrupt event notification timing change function (BFRE)
Function that automatically clears the buffer memory after the data for the pipe specified at the DxFIFO port
has been read (DCLRM)
Function to automatically supply a clock from the low-power sleep state (ATCKM)
NAK setting function for response PID generated by end of transfer (SHTNAK)
1.2.10 Applications
PDA, DVD recorder, Set top box, Digital TV, Printer , USB audio devce, Digital video camera, Digital still camera,
external storage device, and Hi-Speed USB devices
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M66596FP/WG
1.3 Pin layout diagram
SD5
SD4
SD3
SD2
SD1
SD0
VIF
DGND
VDD
D15
D14
D13
D12
D11
D10
D9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 1.1 and Figure 1.2 show the pin layout diagram (top view) of the controller.
DREQ1_N
60
21
A4
DACK1_N/DSTB0_N
61
20
A3
DEND1_N
62
19
A2
RST_N
63
18
A1
VIF
64
17
MPBUS
*The “_N” in the signal name
indicates that the signal is in the
“L” active state.
16
A5
TEST
DEND0_N
22
15
A6/ ALE
59
VIF
DACK0_N
14
D0
23
AFED15G
24
58
13
57
AFED15V
DREQ0_N
12
D1/AD1
AFEA33V
25
(Top view)
11
56
XOUT
D2/AD2
CS_N
M66596FP
10
WR1_N
26
XIN
D3/AD3
55
9
54
AFEA33G
WR0_N
8
D4/AD4
27
REFRIN
28
7
53
AFEA15G
RD_N
6
D5/AD5
AFEA15V
29
5
52
VBUS
SOF_N
4
D6/AD6
DP
INT_N
30
3
D7
51
DM
SD7
2
D8
31
AFED33V
32
50
1
49
AFED33G
SD6
package
M66596FP : 64P6X : 64pinLQFP(0.5mm pitch)
Figure 1.1 Pin layout diagram of M66596FP
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M66596FP/WG
M66596WG(TOP VIEW)
8
SD6
SD4
SD2
DGND
VDD
D13
D10
D9
7
SD7
SD5
SD3
VIF
D15
D12
D8
D7
6
RD_N
SOF_N
INT_N
SD0
D14
D11
D6/AD6
D5/AD5
5
CS_N
WR1_N
WR0_N
SD1
D2/AD2
D1/AD1
D4/AD4
D3/AD3
A5
A2
A6/ALE
D0
A3
A4
4
DEND0_N DREQ1_N DREQ0_N DACK0_N
3
DACK1_N
/DSTB0_N
VIF
2
RST_N
AFED33V
VBUS
AFEA15G
XOUT
AFED15G
TEST
A1
1
AFED33G
DM
DP
REFRIN
XIN
AFED15V
VIF
MPBUS
A
B
C
D
E
F
G
H
DEND1_N AFEA15V AFEA33G AFEA33V
*The “_N” in the signal name
indicates that the signal is in
the “L” active state.
Package
M66596WG : 64FHX : 64pin FBGA (0.8mm pitch)
Figure 1.2 Pin layout diagram of M66956WG
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M66596FP/WG
1.4 Description of pins
Table 1.1 describes the controller pins. Table 1.2 describes the not used pins.
Table 1.1 Pin descriptions
Category
Pin name
Name
I/O
Function
Pin
count
(Pin
no.s.)
CPU bus
interface
D15-0
AD6-1
Data Bus
Multiplex
Address Bus
I/O
I/O
A6-1
Address Bus
IN
ALE
IN
CS_N
Address Latch
Enable
Chip Select
RD_N
Read Strobe
IN
WR0_N
D7-0 Byte
Write Strobe
D15-8 Byte
Write Strobe
Bus Mode
Selection
IN
SD7-0
Split Data Bus
I/O
DREQ0_N*1)
DREQ1_N*1)
DMA Request
OUT
DACK0_N*1)
DACK1_N*1)
DSTB0_N*2)
DMA
Acknowledge
Data Strobe 0
IN
DEND0_N*1)
DEND1_N*1)
DMA Transfer
End
I/O
Interrupt/
SOF
output
INT_N
Interrupt
OUT
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WR1_N
MPBUS
Split bus
interface
DMA bus
interface
page 5 of 127
IN
IN
IN
IN
This is a 16-bit data bus.
When a multiplex bus is specified, this
group of pins is used on a time-shared
basis for some of the data buses
(D6-D1), or for 6 bits of the address
bus (A6-A1).
This is a 6-bit address bus.
Because the data bus consists of 16
bits, there is no A0.
When a multiplex bus is specified, the
A6 pin is used as the ALE signal.
Setting this to the “L” level selects this
controller.
Setting this to the “L” level reads data
from the controller registers.
At the rising edge, D7-D0 are written to
the registers of the controller.
At the rising edge, D15-D8 are written
to the registers of the controller.
Setting this to the “L” level selects a
separate bus.
Setting this to the “H” level selects a
multiplex bus.
This should be fixed at either the “H” or
“L” level.
If a split bus is selected, this functions
as the data bus for the split bus.
This notifies the system of a D0FIFO
port or D1FIFO port DMA transfer
request.
Input the DMA Acknowledge signal for
the D0FIFO or D1FIFO port.
This functions as the data strobe
signal for the D0FIFO port.
Because it is also used for the DMA
Acknowledge signal of the D1FIFO
port, the DSTB0_N function cannot be
used if the DACK1_N function is being
used.
<In the FIFO port access writing
direction>
This receives the Transfer End signal
from another peripheral chip or the
CPU as an input signal.
<In the FIFO port access reading
direction>
This indicates the transfer end data as
an output signal.
In the “L” active state, this notifies the
system of various types of interrupts
relating to USB communication.
State of pin *7)
RST_
N=”L”
RST_
N
goes
“H”
PCUT
=1
16
(24-39)
*4)
*4)
Input
(Hi-z)
6
(18-23)
Input
*5)
Input
*5)
Input
(Hi-z)
Input
Input
Input
Input
*6)
Input
Input
*6)
Input
Input
Input
*6)
Input
*6)
Input
*3)
Input
*6)
Input
*6)
Input
*3)
Input
Input
(Hi-z)
H
Input
(Hi-z)
H
Input
(Hi-z)
H/L
*8)
2
(58, 61)
Input
Input
Input
2
(59, 62)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
1
(51)
H
H
H
1
(56)
1
(53)
1
(54)
1
(55)
1
(17)
8
(43-50)
2
(57, 60)
Input
Input
Input
*3)
M66596FP/WG
Category
Pin name
Name
I/O
Function
Pin
count
(Pin
no.s.)
SOF_N
XOUT
Oscillation
output
OUT
RST_N
Reset signal
IN
When an SOF is detected in the “L”
active state, an SOF pulse is output.
A crystal oscillator should be
connected between XIN and XOUT.
When using external clock input, the
external clock signal should be
connected to XIN, and XOUT should
be open.
At “L” level, the controller is initialized.
TEST
Test signal
IN
This should be fixed at “L” or open.
DP
USB D+ data
I/O
DM
USB D- data
I/O
VBUS
monitor
input
VBUS
VBUS input
IN
Reference
resistance
REFRIN
IN
Power
supply /
GND
AFEA33V
Reference
input
Transceiver
unit analog
power supply
Transceiver
unit analog
GND
Transceiver
unit digital
power supply
Transceiver
unit digital
GND
Transceiver
unit analog 1.5
V power
supply
Transceiver
unit analog
GND
Transceiver
unit digital 1.5
V power
supply
Transceiver
unit digital
GND
Core power
supply
IO power
supply
This should be connected to the D+
pin of the USB bus.
This should be connected to the D- pin
of the USB bus.
This should be connected directly to
the Vbus of the USB bus. The
connected or disconnected state of the
Vbus can be detected. If this pin is not
connected with Vbus of a USB bus,
connect 5V.
And in case of a host controller, please
fix to 5V too.
*This pin can’t supply vbus.
This should be connected to AFEA33G
through a 5.6 kOhm ±1% resistance.
This should be connected to 3.3 V.
Digital GND
-
Clock
System
control
USB bus
interface
XIN
AFEA33G
AFED33V
AFED33G
AFEA15V
AFEA15G
AFED15V
AFED15G
VDD
VIF
DGND
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SOF pulse
output
Oscillation
input
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OUT
IN
-
This should be connected to 3.3 V.
This should be connected to 1.5 V.
1
(3)
1
(5)
1
(8)
1
(12)
1
(2)
1
(6)
1
(7)
-
-
1
(63)
1
(1)
-
-
1
(16)
1
(4)
This should be connected to 1.5 V.
1
(13)
1
(14)
-
RST_
N=”L”
RST_
N
goes
“H”
PCUT
=1
H
H
H
Input
(L)
Input
(H)
Input
(H)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
1
(11)
1
(9)
-
-
1
(52)
1
(10)
State of pin *7)
-
This should be connected to 1.5 V.
1
(40)
-
This should be connected to 3.3 V or
1.8 V.
3
(15, 42,
64)
1
(41)
M66596FP/WG
*1) The “L” active and “H” active states of these pins can be selected using the control program for the user system.
”_N” indicates that the “L” active state is the default state.
*2) DSTB0_N and DACK1_N are assigned to the same pin, so the functions of one or the other are valid.
*3) The input level of the MPBUS pin needs to be established just before the end of H/W reset. Also, this should not
be switched during operation.
*4) When CS_N and RD_N are “L”, These pins output “H” or “L”.
*5) If MPBUS is “H”, these pins can be made to open.
*6) CS_N, WR0_N, and WR1_N should be kept as (a) or (b) during RST_N=”L” (from RST_N goes "L" to right after
RST_N goes "H").
(a) CS_N=”H”
(b) WR0_N=”H” and WR1_N=”H”
*7) Description of “State of pin”
(a) Input : Pins are Hi-z state. Please do not make it “open” on a board.
(b) Input(Hi-z) : Pins are Hi-z state. Pins can be “open” on a board.
(c) H, L, H/L : Output states is shown.
*8) These pins are in an inactive state.
Table 1.2 The example of not used pins
Category
SPLIT bus interface
DMA bus interface
SOF output
System control
VBUS monitor input
Pin name
SD7-0
DREQ0_N
DREQ1_N
DACK0_N
DACK1_N/DSTB0_N
DEND0_N
DEND1_N
SOF_N
TEST
VBUS
Description
“Open”
“Open”
“Open”
Fix to “H”*1)
Fix to “H”*1)
“Open” *2)
“Open” *2)
“Open”
Fix to “L” or “Open”
Fix to 5V *3)
*1) When DACKn_N pin is not used, please set DACKA bit of DMAnCFG register as "0" (n=0,1).
*2) When DENDx_N pin is not used, please set DENDA bit of DMAnCFG register as "0" (n=0,1).
*3) If this pin is not connected with Vbus of a USB bus, fix to 5V.
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M66596FP/WG
1.5 Pin function configuration
Figure 1.3 shows a diagram of the pin function configuration of the controller.
CPU bus interface
D15-7,D6-1(/AD6-1),D0
A6/ALE,A5-1
CS_N
RD_N
WR0_N
WR1_N
MPBUS
16
6
Interrupt / SOF output
INT_N
SOF_N
Clock
XIN
XOUT
M66596
DMA interface
VBUS monitor input
VBUS
DREQ0_N
DACK0_N
DEND0_N
DREQ1_N
DACK1_N/DSTB0_N
DEND1_N
Split bus
SD7-0
8
System control
RST_N
TEST
2
USB interface
DP, DM
Reference resistance
REFRIN
Figure 1.3 Pin function configuration diagram
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M66596FP/WG
1.6 Block diagram
The controller is consists of an analog front end unit (AFE), a protocol engine unit (Prtcl_Eng) that includes an SIE,
a pipe control unit (Pipe_Ctrl), a transaction schedule control unit(Schedule Ctrl), a FIFO port unit (FIFO_Port), a
buffer memory unit (Buf_Mem), an interrupt control unit (Int_Ctrl), a bus interface unit (BIU), and a CPU interface
register unit (CPU_IF_Reg). Figure 1.4 shows a block diagram of the controller.
When data is being sent and received between M66596 and a USB peripheral(or host) controller connected on the
USB bus, a buffer memory assigned to each of the pipes is used. Two-way communication is possible by the controller
changing data stored in the buffer memory into USB data packets and outputting them to the USB bus using serial
output, and by inputting data packets on the USB bus which are then stored in the buffer memory.
Core power supply
I/O power supply
VIF
AFE power supply
AFEA33V, AFED33V
AFEA15V, AFED15V
VDD
CPU bus interface
A6(/ALE), A5-1,
D15-7, D6-1(/AD6-1), D0,
CS_N, RD_N,
WR0_N,WR1_N
MPBUS
Int_Ctrl
CPU_IF_Reg
Interrupt / SOF output
INT_N, SOF_N
System control
RST_N, TEST
Ground
DGND
Figure 1.4 Block diagram
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VBUS monitor
VBUS
AFE
SIE
Split bus
SD7-0
Buf_Mem
FIFO_Port
DMA interface
DREQ0_N, DREQ1_N
DACK0_N,
DACK1_N/DSTB0_N,
DEND0_N, DEND1_N
Clock
XIN, XOUT
Prctl_Eng
Pipe_Ctrl
BIU
Schedule
_Ctrl
USB interface
DP, DM
Reference resistance
REFRIN
AFE ground
AFEA33G,AFED33G
AFEA15G,AFED15G
M66596FP/WG
1.7 An overview of functions
1.7.1
The function selection
The controller can change a host function and a peripheral function by register setup.
When which of the Host function and the Peripheral function is chosen, hardware recognizes Hi-Speed or
Full-Speed automatically.
1.7.2
Bus interfaces
The controller supports the bus interfaces noted below.
1.7.2.1 External bus interface
The controller uses a CPU bus interface to access control registers.
The bus interface with the CPU supports the two access methods noted below. The Chip Select pin (CS_N) and
the three strobe pins (RD_N, WR0_N and WR1_N) should be used for access.
(1) (16-bit separate bus
The six address buses (A6-1) and the 16 data buses (D15-0) are used.
(2) 16-bit multiplex bus
The ALE pin (ALE) and the 16 data buses (D15-0) are used. The data buses are used for addresses and data on
a time-shared basis.
The separate bus and multiplex bus are selected based on the MPBUS pin signal level when the H/W reset is
canceled.
1.7.2.2 Accessing the buffer memory
The controller supports the two methods described below to access the USB data transfer buffer memory.
(1) CPU access
Addresses and control signals should be used to write data to the buffer memory or read it from the buffer
memory.
(2) DMA access
Data should be written to the buffer memory of the controller, or read from the buffer memory, from the
DMAC in the CPU or a dedicated DMAC.
USB data communication is done using Little Endian. There is a byte Endian swap function for FIFO port
access, and when using 16-bit access, the Endian can be switched using the register settings.
1.7.2.3 DMA access methods
When using DMA access to access the buffer memory, the two access methods noted below can be selected.
(1) Method using a bus shared with the CPU
(2) Method using a dedicated bus (split bus)
1.7.3
USB events
The controller notifies the user’s system of USB operation events by means of interrupts. Moreover, with a pipe
for which the DMA interface has been selected, the system is notified that the buffer memory of the controller
can be accessed by asserting the DREQ signal.
There are 12 types of interrupts and 39 causes for interrupts being generated. The user can select whether or
not interrupt notification is permitted for each type and each cause, using settings in the control program for the
user system.
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M66596FP/WG
1.7.4
USB data transfers
The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and
interrupt transfers, as well as isochronous data transfers. The pipes noted below can be used with data transfers
for various types of communication.
(1) Dedicated control transfer pipe(Default Control Pipe(DCP))
(2) Two dedicated interrupt transfer pipes(Pipe6,7)
(3) Three dedicated bulk transfer pipes(Pipe3, 4, 5)
(4) Two pipes for which bulk transfers or isochronous transfers can be selected(Pipe1, 2)
The settings necessary for USB transfers, such as the transfer type, end point number, and maximum packet
size, should be set for each pipe, in conjunction with the user system.
Also, the controller has a built-in 5 kB buffer memory. For a dedicated bulk transfer pipe and the pipes for
which bulk transfers or isochronous transfers can be selected, settings such as the buffer memory assignment
and buffer operation mode which are based on the user system should be entered. The buffer operation mode
setting can be set to enable high-speed data transfers with few interrupts, using the double-buffer configuration
and data packet continuous transfer function.
Access to the buffer memory from the control CPU of the user’s system and the DMA controller is done
through the three FIFO port registers.
1.7.5
DMA interface
The DMA (Direct Memory Access) interface consists of data transfers between the user system and the
controller using the DxFIFO port, and is a type of data transfer in which the CPU is not involved. The controller
is equipped with a 2-channel DMA interface and has the following functions.
(1) A transfer end notification function using the Transfer End signal (DEND signal)
(2) An auto-clear function activated when a Zero-Length packet is received
(3) A “send addition” function used to send a Zero-Length packet based on input of the Transfer End signal
(DEND signal)
(4) A transfer end function using a transaction counter function
The controller supports the two types of DMA interfaces noted below.
(5) Cycle steal transfer
With this type of transfer, the DREQ pin is repeatedly asserted and negated each time a data transfer (1 byte /
1 word) is carried out.
(6) Burst transfer
With this type of transfer, the DREQ pin remains asserted for the pipe buffer area assigned to the pertinent
FIFO port, or until the transfer is ended by the DEND signal, without ever being negated.
Also, the following can be selected as the DMA interface handshake signal (pin): CS_N, RD_N, or WR_N, or
DACK_N. With DMA transfers using a split bus, high-speed DMA transfers are possible by changing the data
setup timing, by operating the OBUS bit of the DMAxCFG register.
1.7.6
SOF pulse output function
An SOF pulse output function is provided that notifies the system of the timing at which SOF packets are
transmited or received.
In the Host mode, when the controller transmits a SOF packet, the controller outputs pulses to an SOF_N pin.
In the Peripheral mode, when the controller recives SOF packet, the controller outputs pulse. And the
controller outputs pulses at fairly regular intervals, using an SOF interpolation timer, even if an SOF packet is
damaged. In the Peripheral mode, it is also possible to output the pulse only when an SOF packet is damaged.
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M66596FP/WG
1.7.7
External elements integration
The controller has the following external elements built into it. Also, because the VBUS pin can withstand 5 V,
the user system can input the VBUS signal directly to the controller.
(1) Resistors necessary for D+ and D- line control
Resistance of D+ and D-line is built in.
 D+ pull up-registor(Peripheral mode)
 D+, D- pull-down registor(Host mode)
 D+, D- terminating resistors (for Hi-Speed operation)
 D+, D- output resistors (for Full-Speed operation)
(2) 48 MHz and 480 MHz PLL
One of three external clocks (12 MHz / 24 MHz / 48 MHz) can be selected and Hi-Speed and Full-Speed
operation carried out.
1.7.8
Low-power sleep state function
The controller is equipped with a low-power sleep state that reduces current consumption.
The low-power sleep state functions effectively under the following circumstances.
(1) When there is no host or peripheral controller connected
(2) When the device state is shifted to the suspended state, and USB data transfer is not necessary
The system is returned from the low-power sleep state to the normal operating state using a designated
interrupt, or by dummy writing to the controller.
rev.1.00
2006.3.14
page 12 of 127
M66596FP/WG
2 Registers
Reading the table of registers
c Bit no.
Each register is connected to a 16-bit internal bus.
Odd-numbered addresses will use b15 to b8, and even-numbered addresses b7 to b0.
d Status after reset
This indicates the default state of the register immediately after a reset operation, and after
recovering from the low-power sleep state.
H/W Reset is the default state when an external reset signal has been input from the RST_N
pin.
S/W Reset is the default state when the user system has carried out a bit operation using the
USBE bit.
USB Reset is the default state when the controller has detected a USB bus reset.
Low-power Sleep is the default state when the controller has recovered from the low-power
sleep state.
Items that require particular attention during a reset operation are noted under “ Notes”.
“-“ indicates a state in which there is no operation by the controller, and the user setting is
retained.
“?” indicates that a value is undecided.
f S/W Access Condition
This is the condition in effect if the softwear is accessing a register.
g H/W Access Condition This is the condition in effect if the controller is accessing a register during any operation
other than a reset.
R ...... Read Only
W ...... Write Only
R/W ...... Read / Write
R(0) ...... "0"Read Only
W(1) ...... "1"Write Only
h Note
i Bit Name
j Function Description
This is the number of detailed explanations and the number of notes.
This indicates the bit symbol and bit name.
This describes active items and notes.
<Example of table notation>
Nothing is placed in shaded sections. These should be fixed at “0”.
c Bit number
Bit symbol
dH/W reset
S/W reset
USB reset
15
Low-power sleep state
Bit
15
14
13
12
?
?
?
?
14
13
12
A bit B bit C bit
0
0
0
0
0
0
0
0
0
11
10
9
Name
Function
Nothing is placed here. It should be fixed at “0”.
A bit
0 : Operation disabled
AAA enabled
1 : Operation enabled
B bit
0 : "L"output
BBB operation
1 : "H"output
C bit
0 : .......
CCC control
1 : .......
i
j
8
7
6
5
4
3
2
S/W
H/W
Note
R/W
R
R
W
R(0)/
W(1)
R
2.3.1
*1
2.3.2
*1
2.3.2
f
g
h
1
<<Note>>
*1) If the A bit and B bit are being accessed in succession for writing, an access cycle of 300 ns is necessary.
rev.1.00
2006.3.14
page 13 of 127
0
M66596FP/WG
2.1
Table of registers
Table 2.1 shows the controller registers.
Table 2.1 Registers
Address
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
4E
50
52
54
56
58
5A
rev.1.00
Symbol
Name
Index
SYSCFG
SYSSTS
DVSTCTR
TESTMODE
System configuration control register
System configuration status register
2.3
2.3
Device state control register
Test mode register
2.4
2.4
PINCFG
DMA0CFG
DMA1CFG
CFIFO
Data pin configuration register
DMA0 pin configuration register
DMA1 pin configuration register
CFIFO port register
2.5
2.5
2.5
2.6
D0FIFO
D0FIFO port register
2.6
D1FIFO
D1FIFO port register
2.6
CFIFOSEL
CFIFOCTR
CFIFOSIE
D0FIFOSEL
D0FIFOCTR
D0FIFOTRN
D1FIFOSEL
D1FIFOCTR
D1FIFOTRN
INTENB0
INTENB1
CFIFO port selection register
CFIFO port control register
CFIFO port SIE register
D0FIFO port selection register
D0FIFO port control register
D0 transaction counter register
D1FIFO port selection register
D1FIFO port control register
D1 transaction counter register
Interrupt enable register 0
Interrupt enable register 1
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.7
2.7
BRDYENB
NRDYENB
BEMPENB
SOFCFG
BRDY interrupt enable register
NRDY interrupt enable register
BEMP interrupt enable register
SOF pin configuration register
2.7
2.7
2.7
2.8
INTSTS0
INTSTS1
Interrupt status register 0
Interrupt status register 1
2.9
2.9
BRDYSTS
NRDYSTS
BEMPSTS
FRMNUM
UFRMNUM
RECOVER
BRDY interrupt status register
NRDY interrupt status register
BEMP interrupt status register
Frame number register
Micro frame number register
USB address / low-power status recovery register
2.9
2.9
2.9
2.10
2.10
2.11
USBREQ
USBVAL
USBINDX
USBLENG
USB request type register
USB request value register
USB request index register
USB request length register
2.12
2.12
2.12
2.12
2006.3.14
page 14 of 127
M66596FP/WG
Address
5C
5E
60
62
64
66
6E
6A
6C
6E
70
72
74
76
78
7A
7C
7E
Symbol
Name
DCP configuration register
DCP maximum packet size register
DCP control register
2.13
2.13
2.13
PIPESEL
PIPECFG
PIPEBUF
PIPEMAXP
PIPEPERI
Pipe window selection register
Pipe configuration register
Pipe buffer setting register
Pipe maximum packet size register
Pipe period control register
2.14
2.14
2.14
2.14
2.14
PIPE1CTR
PIPE2CTR
PIPE3CTR
PIPE4CTR
PIPE5CTR
PIPE6CTR
PIPE7CTR
Pipe 1 control register
Pipe 2 control register
Pipe 3 control register
Pipe 4 control register
Pipe 5 control register
Pipe 6 control register
Pipe 7 control register
2.14
2.14
2.14
2.14
2.14
2.14
2.14
Nothing is placed in addresses that are shaded. These addresses should not be accessed.
rev.1.00
Index
DCPCFG
DCPMAXP
DCPCTR
2006.3.14
page 15 of 127
M66596FP/WG
2.2 Table of bit symbols
Table 2.2 shows the controller bit symbols.
Table 2.2 Bit symbols
Addr
Register
name
00 SYSCFG
02 SYSSTS
15
14
XTAL
Odd-numbered addresses
13
12
11
10
XCKE
RCKE
PLLC
9
SCKE
8
7
ATCKM
HSE
Even-numbered addresses
5
4
3
2
6
DCFM DMRPD DPRPU
1
FSRPC
0
PCUT
USBE
LNST
04 DVSTCTR
06 TESTMODE
08
0A PINCFG
0C DMA0CFG
WKUP RWUPE USBRST RESUME UACT
RHST
UTST
BIGEND
LDRV
0E DMA1CFG
10 CFIFO
DREQA BURST
DACKA
DFORM
DENDA PKTM
DENDE
OBUS
DREQA BURST
DACKA
DFORM
DENDA PKTM
DENDE
OBUS
CFPORT
12
14 D0FIFO
D0FPORT
16
18 D1FIFO
D1FIPORT
1A
1C
1E CFIFOSEL
20 CFIFOCTR
22 CFIFOSIE
24 D0FIFOSEL
RCNT
REW
BVAL
BCLR
MBW
TGL
SCLR
SBUSY
RCNT
REW
DCLRM DREQE
26 D0FIFOCTR BVAL
28 D0FIFOTRN
BCLR
2A D1FIFOSEL RCNT
2C D1FIFOCTR BVAL
2E D1FIFOTRN
REW
30 INTENB0
32 INTENB1
VBSE
ISEL
CURPIPE
DTLN
FRDY
MBW
TRENB TRCLR DEZPM
CURPIPE
DTLN
FRDY
TRNCNT
MBW
DCLRM DREQE
BCLR
FRDY
RSME
SOFE
TRENB TRCLR DEZPM
CURPIPE
DTLN
TRNCNT
BCHGE
DVSE
CTRE
BEMPE NRDYE BRDYE
URST
DTCHE
SADR
SCFG
SUSP
WDST
SIGNE SACKE
RDST
CMPL
SERR
BRDYM
INTL
PCSE
34
36 BRDYENB
38 NRDYENB
PIPEBRDYE
PIPENRDYE
3A BEMPENB
3C SOFCFG
PIPEBEMPE
SOFM
3E
40 INTSTS0
42 INTSTS1
VBINT
RESM
SOFR
DVST
BCHG
SOFR
DTCH
CTRT
BEMP
NRDY
BRDY
BEMP
NRDY
BRDY
VBSTS
DVSQ
SIGN
VALID
CTSQ
SACK
44
46 BRDYSTS
48 NRDYSTS
4A BEMPSTS
4C FRMNUM
PIPEBRDY
PIPENRDY
PIPEBEMP
OVRN
CRCE
SOFRM
4E UFRMNUM
50 RECOVER
FRNM
UFRNM
STSRECOV
USBADDR
52
54 USBREQ
56 USBVAL
bRequest
58 USBINDX
5A USBLENG
5C DCPCFG
5E DCPMAXP
rev.1.00
bmRequestType
wValue
wIndex
wLength
CNTMD
DEVSEL
2006.3.14
DIR
MXPS
page 16 of 127
M66596FP/WG
Addr
Register
name
60 DCPCTR
15
14
BSTS
SUREQ
Odd-numbered addresses
13
12
11
10
9
8
7
6
Even-numbered addresses
5
4
3
2
SQCLR SQSET SQMON
1
CCPL
0
PID
62
64 PIPESEL
66 PIPECFG
TYPE
68 PIPEBUF
6A PIPEMAXP
DEVSEL
PIPESEL
BFRE
DBLB
CNTMD SHTNAK
DIR
BUFSIZE
6C PIPEPERI
EPNUM
BUFNMB
MXPS
IFIS
IITV
6E
70 PIPE1CTR
72 PIPE2CTR
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
74 PIPE3CTR
76 PIPE4CTR
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
78 PIPE5CTR
7A PIPE6CTR
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
BSTS
ACLRM SQCLR SQSET SQMON
PID
7C PIPE7CTR
BSTS
ACLRM SQCLR SQSET SQMON
PID
7E
rev.1.00
2006.3.14
page 17 of 127
M66596FP/WG
2.3 System control
System configuration control register [SYSCFG]
15
14
XTAL
0
-
0
-
13
XCKE
0
1
12
RCKE
0
0
Bit
11
PLLC
0
0
10
SCKE
0
0
9
?
?
?
?
8
ATCKM
0
-
<Address : 00H>
7
HSE
0
-
6
5
4
DCFM DMRPD DPRPU
0
0
0
-
Name
15-14 XTAL
Clock selection
Function
00: 12 MHz input
01: 24 MHz input
10: 48 MHz input
11: Reserved
3
?
?
?
?
2
1
FSRPC PCUT
0
0
0
-
0
USBE
0
-
S/W
H/W
Note
R/W
R
3.1.6
13 XCKE
0: Oscillation buffer operation disabled
R/W R/W
Oscillation buffer enabled
1: Oscillation buffer operation enabled
(1)
12 RCKE
0: Reference clock supply stopped
R/W
R
Reference clock enabled
1: Reference clock supply enabled
11 PLLC
0: PLL operation disabled
R/W
R
PLL operation enabled
1: PLL operation enabled
10 SCKE
0: Internal clock supply stopped
R/W
R
Internal clock enabled
1: Internal clock supply enabled
9 Nothing is placed here. It should be fixed at “0”.
R
8 ATCKM
The clock is supplied from the low-power sleep R/W
Auto clock supply function enabled
state or clock stop state.
0: Auto clock supply function disabled
1: Auto clock supply function enabled
R/W
R
7 HSE
This enables Hi-Speed operation.
Hi-Speed operation enabled
0: Hi-Speed operation disabled (Full-Speed)
1: Hi-Speed operation enabled (detected by
controller)
6 DCFM
0: Peripheral Controller
R/W
R
1: Host Controller
For detailed information, refer to Chapter 2.3.4 R/W
5 DMRPD
R
D+,D- line resistance control
4 DPRPU
R/W
R
D+,D- line resistance control
3 Nothing is placed here. These should be fixed at “0”.
2 FSRPC
0: Full-Speed receiver is controled by H/W
R/W
R
Full-Speed receiver enable
1: Full-Speed receiver enabled by S/W
1 PCUT
0: Normal operation state
R/W (1) R/W
Low-power sleep state enabled
1: Low-power sleep state
(0)
0 USBE
0: USB block operation disabled (S/W Reset) R/W
R
USB block operation enabled
1: USB block operation enabled
3.1.6
*2)
3.1.6
3.1.6
3.1.6
3.1.7
2.3.1
3.1.4
*1)
2.3.1
*1)
2.3.4
2.3.4
2.3.3
*1)
2.3.2
3.1.4
<< Notes >>
*1) The Hi-Speed operation enabled (HSE) bit and Device Controller function (DCFM) should be set before the
internal clock is supplied and .setup DPRPU and DPRPD bit.
*2) When the system returns from the low-power sleep state to the normal operation state, the controller sets
“XCKE = 1”.
rev.1.00
2006.3.14
page 18 of 127
M66596FP/WG
System configuration status register [SYSSTS]
15
14
13
12
11
10
9
<Address: 02H>
8
7
6
5
4
3
2
1
0
LNST
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Bit
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Name
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Function
15-2 Nothing is placed here. These should be fixed at “0”.
1-0 LNST
Please see the detailed explanation concerning
USB data line status
this item.
?
?
?
?
?
?
?
?
?
?
?
?
S/W
H/W
Note
R
W
2.3.3
<<Notes>>
None in particular
2.3.1
Selection of a function
The HSE and DCFM bit of the SYSCFG register should be used to select function of the controller. The
controller function selection table is shown in Table 2.3.
Table 2.3 The controller function selection
HSE
DCFM
Speed
0
0
Full
0
1
Full
1
0
Full / Hi
1
1
Full / Hi
* RHSP : Reset Handshake Protocol
2.3.2
Function
Peripheral
Host
Peripheral
Host
Note
Full-Speed communication only.
Full-Speed communication only.
The communication speed is based on the result of RHSP.
The communication speed is based on the result of RHSP.
USB block operation enabled
The USBE bit of the SYSCFG register should be used to enable USB block operation.
The same bit can be used to carry out an S/W reset of the controller. When software is set to “USBE=0”, the
controller resets the register targeted for S/W reset initialization to the default setting value. As long as
“USBE=0” is set, no data can be written by software to the bit targeted for S/W reset initialization. “USBE=1”
should be set following an S/W reset to enable controller operation.
rev.1.00
2006.3.14
page 19 of 127
M66596FP/WG
2.3.3
Line status monitor
Table 2.4Table 2.3 shows the USB data bus line statuses of the controller. The controller monitors the line
status (D+ line and D- line) of the USB data bus using the LNST bit of the SYSSTS register. The LNST bit is
configured of two bits. For the meaning of each of the bits, please refer to the table below.
The line status is checked with the Full-Speed receiver inside a M66596. This controller controls a Full-Speed
receiver automatically when internal clock is supplied. If the FSRPC of the SYSCFG register is set up, it is
enabled by setting the FSRPC of the SYSCFG register by S/W when internal clock is not supplied. After H/W
reset, in checking the state of D+ and D- before supplying an internal clock, please set a FSRPC bit as 1. Once
supplying an internal clock, it is not necessary to set up by S/W.
In the low-power sleep state, the line status cannot be monitored.
Table 2.4 USB data bus line statuses
LNST [1]
LNST [0]
During Full-Speed
operation
During Hi-Speed operation
During chirp operation
0
0
1
1
0
SE0
Squelch
Squelch
1
J State
not Squelch
Chirp J
0
K State
Invalid
Chirp K
1
SE1
Invalid
Invalid
Chirp:
The reset handshake protocol is being executed in the Hi-Speed operation enabled state (HSE = “1”).
Squelch:
SE0 or Idle state
not Squelch: Hi-Speed J state or Hi-Speed K state
Chirp J:
Chirp J state
Chirp K:
Chirp K state
2.3.4
USB data bus register control
A setup about resistance of a USB data bus is shown in Table 2.5. USB data bus line resistors are controled by
DMRPD and DPRPU bit of SYSCFG register.
Table 2.5 Resistance control of a USB data bus
DMRPD
0
0
1
1
rev.1.00
2006.3.14
DPRPU
0
1
0
1
DOpen
Open
Pull-Down
Pull-Down
page 20 of 127
D+
Open
Pull-Up
Pull-Down
Pull-Up
note
Peripheral Controller
Host Controller
M66596FP/WG
2.4 USB signal control
Device state control register [DVSTCTR]
15
14
?
?
?
?
?
?
?
?
13
?
?
?
?
12
?
?
?
?
Bit
11
?
?
?
?
10
?
?
?
?
9
?
?
?
?
<Address: 04H>
8
7
6
5
4
WKUP RWUPE USBRST RESUME UACT
0
0
0
0
0
0
0
0
0
01
0
0
0
0
0
0
0
0
Name
3
2
1
0
RHST
?
?
?
?
Function
S/W
15-9 Nothing is placed here. These should be fixed at “0”.
8 WKUP
0: Non-output
Wakeup output (Peripheral mode)
1: Remote wakeup signal output
0
0
0
0
0
0
H/W
Note
?
?
?
?
R/W(1) R/W(0) 2.4.1
*1),*2)
7
RWUPE
0: Remote wakeup disabled
Remote wakeup enable
1: Remote wakeup enabled
(Host mode)
6 USBRST
0: Non-output
USB bus reset output (Host mode)
1: USB bus reset output
5 RESUME
0: Non-output
Resume output (Host mode)
1: Resume signal output
4 UACT
0: Disable
USB Communication enable
1: Enable
3-2 Nothing is placed here. These should be fixed at “0”.
1-0 RHST
00: Communication speed not decided
Reset handshake
01: Reset handshake being processed
10: Full-Speed operation established
11: Hi-Speed operation established
R/W
R
R/W
R
R/W
R/W
R
2.4.1
*2),*3)
2.4.1
*3)*3
R/W(1) 2.4.1
*3)
R
2.4.1
*3)
W
2.4.2
<<Notes>>
*1) ”1” should never be written to the WKUP bit unless “Suspended” is set for the device state (“DVSQ = 1xx”) and
a remote wakeup from the USB host is enabled.
*2) If the WKUP or RWUPE bit is set 1,don’ t stop Internal clock supply.
*3) If the controller is in peripheral mode ,set to “RWUPE=0, USBRST=0, RESUME=0, UACT=0”.
Test mode register [TESTMODE]
15
14
13
12
11
10
<Address: 06H>
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R
2.4.3
*4)
UTST
?
?
?
?
?
?
?
?
?
?
?
?
Bit
?
?
?
?
?
?
?
?
?
?
?
?
Name
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Function
?
?
?
?
0
0
0
15-4 Nothing is placed here. These should be fixed at “0”.
3-0 UTST
Please see the detailed explanation concerning R/W
Test mode
this item.
<<Note>>
*4) The UTST bit is valid only during Hi-Speed operation. Check to make sure the “RHST=11” before using it.
H/W reset is required for after the test by UTST bit operation.
rev.1.00
2006.3.14
page 21 of 127
M66596FP/WG
2.4.1
USB data bus control
Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on
the user system.
(a)
Remote wakeup (Peripheral mode)
The WKUP bit handles control of remote wakeup signal output to the USB bus. The controller controls the
output time for remote wakeup signals. 2ms after a software has set “1” for the WKUP bit, the M66596 outputs a
10 ms “K-State” then it transfers the bus state to idle. When the bus state is transferred to the idle state, the
controller sets “WKUP=0”.
According to the USB specification, USB idle state must be kept longer than 5ms. Thus if the software set
“WKUP=1” right after detection of Suspend state, the controller will assert “K-State” after 2ms.
(b)
Remote wakeup, Resume (Host mode)
A resume signal is output on a USB bus by setting a RESUME bit as 1.
Moreover, when the RWUPE bit is set as 1 and a remote wakeup signal is detected, a resume signal is
outputted to a down port. At this time, a controller sets 1 as a "RESUME" bit. In both cases manage the output
time of a resume signal by S/W. The output of a resume signal is stopped by "RWUP=0" or "RESUME=0" writing
by S/W.
(c)
USB Communication enable (Host mode)
A SOF (or uSOF) packet is transmitted on a USB bus by a UACT bit. The controller manages a SOF packet
interval. When "1" is set as a UACT bitthe SOF packet is sent out. When "0" is set as a UACT bit, after sending
out the next SOF, the controller is made into a bus idle state.
(d)
USB bus reset (Host mode)
A USB bus reset signal is outputted by setting a USBRST bit as 1. Software should manage USB bus reset
time. Please set "USBRST=0" after waiting for USB bus reset time.
2.4.2
Communication speed discrimination
If the HSE bit of a SYSCFG register is set as 1, at the time of transmission and reception of USB bus reset,
this controller execute a reset handshake automatically and determine transmission speed. Softwear is able to
confirm the USB speed, using the RHST bit.
If Hi-Speed operation has been set to the disabled state (“HSE=0”) by softwere, the controller immediately
establishes Full-Speed operation (“RHST=10”), without executing the reset handshake protocol.
In the Host mode, it is the following timing that a result is reflected in a RHST bit after USB reset is desabled.
Software needs to wait connected peripheral is Full-Speed device.
- Full-Speed device : When a USB bus changes from the SE0 State to J State by with USB bus reset.
- Hi-Speed device : When termination resistance is changed to Hi-Speed mode by the reset handshake.
(It decides during USB bus reset)
After the USB bus reset end (after URST=0 setup), when RHST is not decided after sufficient waiting time,
the USB cable may be disconnect during USB bus reset. In such a case, please check the state of a USB bus by
the LNST bit.
2.4.3
Test mode
Table 2.6 shows the test mode operation of the controller. The UTST bit of the TESTMODE register controls
the USB test signal output during Hi-Speed operation.
Table 2.6 Test mode operation
UTST bit setting
Test mode
Normal operation
Test_J
Test_K
Test_SE0_NAK
Test_Packet
Reserved
rev.1.00
2006.3.14
page 22 of 127
Peripheral mode
0000
0001
0010
0011
0100
0101-0111
Host mode
0000
1001
1010
1011
1100
1101-0111
M66596FP/WG
2.5 External input/output control
Data pin configuration register [PINCFG]
15
LDRV
0
-
14
13
12
11
10
9
<Address: 0AH>
8
7
6
5
4
3
2
1
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
S/W
H/W
Note
R/W
R
2.5.1
*1)
R/W
R
2.5.2
*1)
BIGEND
?
?
?
?
?
?
?
?
Bit
?
?
?
?
?
?
?
?
?
?
?
?
Name
?
?
?
?
0
0
Function
15 LDRV
0: When VIF=1.6-2.0 V
Output pins drive current control
1: When VIF=2.7-3.6 V
14-9 Nothing is placed here. These should be fixed at “0”.
8 BIGEND
0: Little Endian
FIFO port Endian
1: Big Endian
7-0 Nothing is placed here. These should be fixed at “0”.
<<Note>>
*1) The BIGEND bit is common to all of the FIFO ports and available for the FIFO ports only. The BIGEND bit
doesn’t affects register access.
rev.1.00
2006.3.14
page 23 of 127
M66596FP/WG
The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the
DMA1CFG register controls the input/output pins used for the DMA1 interface and the D1FIFO port.
DMA0 pin configuration register [DMA0CFG]
DMA1 pin configuration register [DMA1CFG]
15
?
?
?
?
14
13
DREQA BURST
0
0
0
-
Bit
12
11
?
?
?
?
?
?
?
?
10
DACKA
0
0
Name
9
0
0
8
DFORM
0
0
<Address: 0CH>
<Address: 0EH>
7
0
0
6
5
4
DENDA PKTM DENDE
0
0
0
0
0
0
3
?
?
?
?
Function
15 Nothing is placed here. This should be fixed at “0”.
14 DREQA
This specifies the active state for the DREQx_N
DREQx_N signal polarity selection
pin.
0: Low active
1: High active
13 BURST
0: Cycle steal transfer
Burst mode
1: Burst transfer
12-11 Nothing is placed here. These should be fixed at “0”.
10 DACKA
This specifies the active state for the DACKx_N
DACKx_N signal polarity selection
pin.
0: Low active
1: High active
9-7 DFORM
011: Only the DACKx_N signal is used (CPU
DMA transfer signal selection
bus).
000: The Address signal + the RD_N/WRx_
signals are used (CPU bus).
010: The DACKx_N + the RD_N/WRx_N
signals are used (CPU bus).
100: The DACKx_N signal is used (split bus).
110: The DACK0_N + the DSTB0_N signal
are used (split bus).
001, 101, 111: Reserved
6 DENDA
This specifies the active state of the DENDx_N
DEND0_N signal polarity selection
pin.
0: Low active
1: High active
5 PKTM
0: The DENDx_N signal is asserted in transfer
Packet mode
units.
1: The DENDx_N signal is asserted each time
an amount of data corresponding to the buffer
size is transferred.
4 DENDE
0: The DENDx_N signal is disabled
DENDx_N signal enabled
(Hi-Z output).
1: The DENDx_N signal is enabled.
3 Nothing is placed here. It should be fixed at “0”.
2 OBUS
0: The OBUS mode is enabled.
OBUS operation disabled
1: The OBUS mode is disabled.
1-0 Nothing is placed here. These should be fixed at "0”.
2
OBUS
0
0
1
0
?
?
?
?
?
?
?
?
S/W
H/W
Note
R/W
R
-
R/W
R
2.5.3
*3)
R/W
R
-
R/W
R
3.4.3
*3)
R/W
R
-
R/W
R
2.5.3
3.4.3.4
*2)
R/W
R
2.5.3
3.4.3.4
R/W
R
3.5
<<Notes>>
*2) The PKTM bit is valid only when the data receiving direction (reading from the buffer memory) is set. If the
DxFIFO port is being used in the data writing direction, “PKTM=0” should be set.
*3) The “DFORM=110” setting is valid only when the DMA channel 0 is set.
Also, the following should not be set: "DFORM=001”,"DFORM=101” and"DFORM=111”.
rev.1.00
2006.3.14
page 24 of 127
M66596FP/WG
2.5.1
Output pins drive current control
The output pins drive capability should be set using the LDRV bit of the PINCFG register, to match the VIF
power supply.
The output pins are the SD7-0, D15-0, INT_N, DREQx_N, DENDx_N, and SOF_N pins.
2.5.2
FIFO port access Endian
Table 2.7 and Table 2.8 show the byte Endian operation of the controller. (The controller uses Little Endian.) When
the CPU of user-system is Big-endian, software should be set the BIGEND bit to “1” of the PINCFG register.
Table 2.7 Endian operation when using 16-bit access
BIGEND
0
1
b15 – b8
Odd-numbered addresses
Even-numbered addresses
b7 – b0
Even-numbered addresses
Odd-numbered addresses
Table 2.8 Endian operation when using 8-bit access
BIGEND
0
1
2.5.3
b15 – b8
Writing: invalid
Reading: invalid
Writing: valid
Reading: valid
b7 – b0
Writing: valid
Reading: valid
Writing: invalid
Reading: invalid
DMA signal control
When transferring data using the DMA interface, the DMA operations (assertion and negation of the DREQx_N and
DENDx_N signals, and the DMA transfer mode) should be specified to match the user system, using the BURST,
PKTM, DENDE, and OBUS bits of the DMAxCFG register. The DMA signals are valid for the selected pipe(s) as
long as DMA transfers are enabled using the DREQE bit of the DxFIFOSEL register, which will be explained
later. The DREQx_N pin is asserted when the buffer memory of the pipe is in the Buffer Ready (BRDY) state.
rev.1.00
2006.3.14
page 25 of 127
M66596FP/WG
2.6 FIFO ports
The transmission and reception buffer memory of the controller uses the FIFO. The FIFO port registers should be
used to access the buffer memory. There are three FIFO ports: the CFIFO port, D0FIFO port, and D1FIFO port.
Each FIFO port is configured of a port register that handles reading of data from the buffer memory and writing of
data to the memory, a selection register used to select the pipe assigned to the FIFO port, a control register, and
registers used specifically for port functions (an SIE register used exclusively for the CFIFO port, and a transaction
counter register used exclusively for the DxFIFO port).
The Notes noted below apply to each of the FIFO ports.
1. The DCP buffer memory can only be accessed through the CFIFO port.
2. Accessing the buffer memory using DMA transfer can be done only through the DxFIFO port.
3. Accessing the DxFIFO port using the CPU has to be done in conjunction with the functions and restrictions of
the DxFIFO port.(Using the transaction counter, etc.)
4. When using functions specific to the FIFO port, the selected pipe cannot be changed.
(Using the transaction counter, signal input/output through DMA-related pins, etc.)
5. Registers corresponding to a FIFO port never affect other FIFO ports.
6. The same pipe should not be assigned to two or more separate FIFO ports.
7. There are two sorts of buffer memory states; when the access right is on the CPU side and it is on the SIE
side. When the buffer memory access right is on the SIE side, the memory cannot be properly accessed from
the CPU.
8. The pipe configuration,i.e. PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPE1CTR registers of the pipe
selected by the CURPIPE bit should not be changed.
CFIFO port register [CFIFO]
D0FIFO port register [D0FIFO]
D1FIFO port register [D1FIFO]
<Address: 10H>
<Address: 14H>
<Address: 18H>
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
15-0 FIFOPORT
FIFO port
8
7
FIFOPORT
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
This handles reading of received data from the R/W
buffer memory, or writing of the sent data to the
buffer memory.
R/W
3.4
*1)
Function
<<Note>>
*1) Only the CFIFO port can be used for DCP access of the buffer memory.
Accessing the buffer memory using DMA transfers can only be done through the D0FIFO and D1FIFO ports.
rev.1.00
2006.3.14
page 26 of 127
M66596FP/WG
CFIFO port selection register [CFIFOSEL]
D0FIFO port selection register [D0FIFOSEL]
D1FIFO port selection register [D1FIFOSEL]
15
RCNT
0
0
0
14
13
12
REW DCLRM DREQE
0
0
0
0
0
0
0
0
0
Bit
11
?
?
?
?
10
9
8
7
MBW TRENB TRCLR DEZPM
0
0
0
0
0
0
0
0
0
0
0
0
Name
15 RCNT
Read Count mode
<Address: 1EH>
<Address: 24H>
<Address: 2AH>
6
?
?
?
?
5
ISEL
0
0
0
4
3
2
?
?
?
?
?
?
?
?
0
0
0
Function
0: The DTLN bit is cleared when all of the
reception data has been read.
1: The DTLN bit is decremented when the
reception data is read.
0: Invalid.
1: The buffer pointer is rewound.
0: The Auto Buffer Clear mode is disabled.
1: The Auto Buffer Clear mode is enabled.
1
CURPIPE
0
0
0
0
S/W
H/W
Note
R/W
R
0
0
0
14 REW
R(0)/W R/W(0) 3.4.2.2
Buffer pointer rewind
R/W
R
3.4.3.5
13 DCLRM
*2)
This is the Auto Buffer Memory clear
mode accessed after the data for the
specified pipe has been read.
12 DREQE
0: Output is disabled.
R/W
R
3.4.3
DREQ signal output enabled
1: Output is enabled.
*2)
11 Nothing is placed here. This should be fixed at “0”.
10 MBW
0: 8-bit width
R/W
R
3.4.2
FIFO port access bit width
1: 16-bit width
*4)
9 TRENB
0: The transaction counter function is invalid. R/W
R
3.4.2.5
Transaction counter enabled
1: The transaction counter function is valid.
*2)
8 TRCLR
0: Invalid
R(0)/
R
3.4.2.5
Transaction counter clear
1: The current count is cleared.
W(1)
*2)
7 DEZPM
0: No packet is added.
R/W
R
3.4.3.3
Zero-Length Packet Added mode
1: The packet is added.
*2)
6 Nothing is placed here. This should be fixed at “0”.
0: This selects reading from the buffer
R/W
R
3.4
5 ISEL
Access direction of the FIFO port when memory.
*3)
DCP is selected
1: This selects writing to the buffer memory.
4-3 Nothing is placed here. These should be fixed at “0”.
R/W
R
3.4
2-0 CURPIPE
000: DCP / No specification
*5)
FIFO port access pipe specification
001: Pipe 1
010: Pipe 2
011: Pipe 3
100: Pipe 4
101: Pipe 5
110: Pipe 6
111: Pipe 7
<<Notes>>
*2) The DCLRM, DREQE, TRENB, TRCLR and DEZPM bits are valid for the D0/D1FIFOSEL registers. The
DCLRM, TRENB and TRCLR bits are valid when the receiving direction (reading from the buffer memory) has been
set for the pipe specified by the CURPIPE bit. The DEZPM bit is valid when the sending direction (writing to the
buffer memory) has been set for the pipe specified by the CURPIPE bit.
*3) The ISEL bit is valid only when DCP is selected using the CFIFO port selection register. Software should set the
ISEL bit according to the folowing (a) or (b).
(a) The setting to CURPIPE bit to DCP (“CURPIPE=”0”) and setting to ISEL bit should be done at the same
time.
(b) First software sets CURPIPE bit to DCP (“CURPIPE=”0”), then it sets ISEL bit after 200ns or more.
*4) Once reading from the buffer memory has begun, the access bit width of the FIFO port cannot be changed until
all of the data has been read. Also, the bit width cannot be changed from the 8-bit width to the 16-bit width
while data is being written to the buffer memory.
*5) Specifying"CURPIPE=0"using the D0/D1FIFOSEL register will be interpreted as no pipe having been specified.
Also, the pipe number should not be changed while DREQ output is enabled.
*6) Don’t set the same pipe to CURPIPE of C/D0 / D1FIFOSEL register.
rev.1.00
2006.3.14
page 27 of 127
M66596FP/WG
CFIFO port control register [CFIFOCTR]
D0FIFO port control register [D0FIFOCTR]
D1FIFO port control register [D1FIFOCTR]
15
BVAL
0
0
0
14
BCLR
0
0
0
13
FRDY
0
0
0
12
11
10
9
<Address: 20H>
<Address: 26H>
<Address: 2CH>
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
DTLN
?
?
?
?
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
0
0
0
Function
15 BVAL
0: Invalid
R/ W(1) R/W
Buffer Memory Valid flag
1: Writing ended
14 BCLR
0: Invalid
R(0)/ R/W(0)
CPU Buffer Clear
1: Clears the buffer memory on the CPU side. W(1)
13 FRDY
0: FIFO port access is disabled.
R
W
FIFO Port Ready
1: The FIFO port can be accessed.
12 Nothing is placed here. This should be fixed at “0”.
11-0 DTLN
The length of the reception data can be
R
W
Reception Data Length
confirmed.
Note
3.4.2
*7)
3.4.2
*8), *9)
3.4.4
*10)
3.4.4
*8)
<<Notes>>
*7) Writing “1” to the BVAL bit is valid when the direction of the data packet is the sending direction (when data is
being written to the buffer memory). When the direction is the receiving direction, “BVAL=0” should be set.
*8) The BCLR bit and DTLN bit are valid for the buffer memory on the CPU side. Software should set “BCLR=1” or
refer DTLN bit after making sure that “FRDY=1”.
*9) Using the BCLR bit to clear the buffer should be done with the pipe invalid state by the pipe configuration
(“PID=NAK”).
*10) The FRDY bit requires an access cycle of at least 450 ns after the pipe has been selected.
CFIFO port SIE register [CFIFOSIE]
15
TGL
0
0
0
14
13
SCLR SBUSY
0
0
0
0
0
0
Bit
<Address: 22H>
12
11
10
9
8
7
6
5
4
3
2
1
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
S/W
H/W
Note
Name
Function
15 TGL
0: Invalid
Access Right Switch
1: Switches access right
14 SCLR
0: Invalid
SIE Buffer Clear
1: Clears buffer memory on SIE side
13 SBUSY
0: SIE is not being accessed.
SIE Buffer Busy
1: SIE is being accessed.
12-0 Nothing is placed here. These should be fixed at “0”.
R(0)/ R/W(0) 3.4.2.3
W(1)
*11)
R(0)/ R/W(0) 3.4.2.4
W(1)
*12)
R
W 3.4.2.3
<<Note>>
*11) The function of the TGL bit is to set the buffer memory on the SIE side to the CPU side. Set “PID=NAK” and
check the SBUSY bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then write the TGL bit
(toggle operation). This bit is valid only for pipes for which the reception direction (reading from the buffer
memory) has been set.
*12) The function of the SCLR bit is to clear the buffer memory on the SIE side. Set “PID=NAK” and check the
SBUSY bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then clear the buffer. This bit is
valid only for pipes for which the sending direction (writing to the buffer memory) has been set.
rev.1.00
2006.3.14
page 28 of 127
M66596FP/WG
D0 transaction counter register [D0FIFOTRN]
D1 transaction counter register [D1FIFOTRN]
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
15-0 TRNCNT
Transaction counter
<Address: 28H>
<Address: 2EH>
8
7
TRNCNT
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
3.4.2.5
*13)
Function
Writing: Sets the number of DMA transfer
transactions.
Reading: Reads the number of transactions.
<<Note>>
*13) The transaction counter is valid when data is being read from the buffer memory.
The number of transactions can be read while counting is taking place only if the TRENB bit of the DxFIFOSEL
register is “1”. If “TRENB=0”, the set number of transactions can be read.
rev.1.00
2006.3.14
page 29 of 127
M66596FP/WG
2.7 Interrupts enabled
Interrupts enabled register 0[INTENB0]
15
VBSE
0
0
-
14
RSME
0
0
-
13
SOFE
0
0
0
Bit
12
DVSE
0
0
0
<Address: 30H>
11
10
9
8
7
CTRE BEMPE NRDYE BRDYE URST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
SCFG
0
0
0
4
SUSP
0
0
0
3
WDST
0
0
0
2
RDST
0
0
0
1
CMPL
0
0
0
0
SERR
0
0
0
Function
S/W
H/W
Note
15
VBSE
VBUS interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
14
RSME
Resume interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
13
SOFE
Frame number refresh interrupts enabled
DVSE
Device state transition interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
R/W
R
CTRE
0: Interrupt output disabled
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
2.7.1
2.7.8
3.2.9
2.7.1
2.7.8
3.2.10
2.7.1
3.2.8
2.7.1
2.7.2
3.2.6
2.7.1
2.7.3
3.2.7
2.7.1
3.2.5
2.7.1
3.2.4
2.7.1
3.2.3
2.7.2
3.2.6
R/W
R
2.7.2
3.2.6
R/W
R
2.7.2
3.2.6
R/W
R
2.7.2
3.2.6
R/W
R
2.7.3
3.2.7
R/W
R
2.7.3
3.2.7
R/W
R
2.7.3
3.2.7
R/W
R
2.7.3
3.2.7
12
11
Name
6
SADR
0
0
0
Control transfer stage transition interrupts enabled 1: Interrupt output enabled
10
9
8
7
6
5
4
3
2
1
0
rev.1.00
BEMPE
0: Interrupt output disabled
Buffer Empty interrupts enabled
1: Interrupt output enabled
NRDYE
0: Interrupt output disabled
Buffer Not Ready response interrupts enabled 1: Interrupt output enabled
BRDYE
0: Interrupt output disabled
Buffer Ready interrupts enabled
1: Interrupt output enabled
URST
0: DVST interrupt disabled at transition to
Default state transition notifications enabled default state
1: DVST interrupt enabled at transition to
default state
0: DVST interrupt disabled at transition to
SADR
Address state transition notifications enabled address state
1: DVST interrupt enabled at transition to
address state
SCFG
0: DVST interrupt disabled at transition to
Configuration state transition notifications
configuration state
enabled
1: DVST interrupt enabled at transition to
configuration state
SUSP
0: DVST interrupt disabled. at transition to
Suspend state transition notifications enabled suspend state
1: DVST interrupt enabled at transition to
suspend state
WDST
0: CTST interrupt disabled at transition to
Control write transfer status stage transition status stage of control write transfer
notifications enabled
1: CTST interrupt enabled at transition to
status stage of control write transfer
RDST
0: CTST interrupt disabled at transition to
Control read transfer status stage transition status stage of control read transfer
notifications enabled
1: CTST interrupt enabled at transition to
status stage of control read transfer
CMPL
0: CTST interrupt are disabled at end of
Control transfer end notifications enabled
control transfer
1: CTST interrupt enabled at end of control
transfer
SERR
0: CTST interrupt disabled at detection of
Control transfer sequence error notifications control transfer sequence error
enabled
1: CTST interrupt enabled at detection of
control transfer sequence error
2006.3.14
page 30 of 127
M66596FP/WG
<<Note>>
None in particular
Interrupt enabled register 1[INTENB1]
15
?
?
?
?
14
BCHGE
0
0
-
13
?
?
?
?
Bit
12
DTCHE
0
0
0
<Address: 32H>
11
10
9
8
7
6
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Name
5
4
SIGNE SACKE
0
0
0
0
0
0
3
?
?
?
?
Function
15 Nothing is placed here. These should be fixed at “0”.
14 BCHGE
0: Interrupt output disabled
USB bus change interrupt enabled
1: Interrupt output enabled
2
1
BRDYM INTL
0
0
0
0
0
PCSE
0
0
-
S/W
H/W
Note
R/W
R
2.7.1
2.7.4
2.7.8
3.2.11
R/W
R
2.7.1
2.7.5
3.2.12
*1), *2)
R/W
R
R/W
R
2.7.1
2.7.6
3.2.14
*1)
2.7.1
2.7.7
3.2.13
*1)
R/W
R
*3)
R/W
R
3.2.1
R/W
R
*4)
13 Nothing is placed here. This should be fixed at “0”.
12 DTCHE
Full-Speed detach detect interrupt
enabled
0: Interrupt output disabled
1: Interrupt output enabled
11-6 Nothing is placed here. This should be fixed at “0”.
5 SIGNE
0: Interrupt output disabled
Setup transaction error detect interupt
1: Interrupt output enabled
enabled
4
SACKE
Setup transaction complete interrupt
enabled
3
2
Nothing is placed here. This should be fixed at “0”.
BRDYM
0: Software clears BRDY interrupt status
BRDY interrupt status clear timing control 1: The controller clears BRDY interrupt status
INTL
0: Edge sensing
Interrupt output sensing control
1: Level sensing
PCSE
0: USB resume detectionm, VBUS interrupt
returning fact selection from low-power
detection during suspend, or CS_N signal
sleep mode
input
1: USB resume detectionm, or VBUS interrupt
detection during suspend
1
0
0: Interrupt output disabled
1: Interrupt output enabled
<<Notes>>
*1) DTCHE, SIGNE, SACKE bit are effective only at the time of a Host mode.
*2) The DTCHE bit is effective only at the time of Full-Speed mode.
Please perform detach detection by S/W, such as detecting ignore packet from peripheral device at the time of
Hi-Speed mode.
*3) When software sets "BRDYM=1", it will set “INTL=1” also.
*4) PCSE bit shoud be set after “USBE=1” setting.
rev.1.00
2006.3.14
page 31 of 127
M66596FP/WG
BRDY interrupt enabled register [BRDYENB]
<Address: 36H>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
4
3
PIPEBRDYE
0
0
0
0
0
0
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPEBRDYE
0: Interrupt output disabled
BRDY interrupts for the each pipe is
1: Interrupt output enabled
enabled.
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
2.7.1
3.2.3
*5)
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
2.7.1
3.2.4
*6)
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
2.7.1
3.2.5
*7)
<<Note>>
*5) The bit numbers correspond to the pipe numbers.
NRDY interrupt enabled register [NRDYENB]
<Address: 38H>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
4
3
PIPENRDYE
0
0
0
0
0
0
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPENRDYE
0: Interrupt output disabled
NRDY interrupts for the each pipe is
1: Interrupt output enabled
enabled.
<<Note>>
*6) The bit numbers correspond to the pipe numbers.
BEMP interrupt enabled register [BEMPENB]
<Address: 3AH>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPEBEMPE
0: Interrupt output disabled
BEMP interrupts for the each pipe is
1: Interrupt output enabled
enabled.
<<Note>>
*7) The bit numbers correspond to the pipe numbers.
rev.1.00
2006.3.14
page 32 of 127
4
3
PIPEBEMPE
0
0
0
0
0
0
M66596FP/WG
2.7.1
Interrupt masks
The VBSE, RSME, SOFE, DVSE, CTRE, BEMPE, NRDYE, and BRDYE bits of the INTENB0 register and BCHGE,
DTCHE, SIGNE, SACKE of INTENB1 register operate as interrupt mask bits. Each of the bits should be used
to specify whether interrupt signal output is enabled or disabled for the INT_N pin.
The BRDYENB register, NRDYENB register and BEMPENB register operate as the BRDY interrupt mask bit,
the NRDY interrupt mask bit, and the BEMP interrupt mask bit, respectively, for the each corresponding pipe.
2.7.2
Device state transition interrupts
The URST, SADR, SCFG, and SUSP bits of the INTENB0 register operate as interrupt mask bits for the device
state transition interrupt (DVST). If a factor is disabled, no device state transition interrupt is issued in
response to the pertinent factor. However, the device state (DVSQ) transits in keeping with the circumstances.
This function is effective only at the time of a peripheral mode.
2.7.3
Control transfer stage transition interrupts
The WDST, RDST, CMPL and SERR bits of the INTENB0 register should be used to set the interrupt factors
for the control transfer stage transition interrupt (CTRT). If a factor is disabled, no control transfer stage
transition interrupts are issued in response to the pertinent factor.
This function is effective only at the time of a peripheral mode.
2.7.4
USB bus change interrupt
Interruption can be generated when a USB bus state changes. This interruption enable with the BCHGE bit of
INTENB1 register. This interruption is used for the peripheral connection and detection of a remote wakeup
signal in the Host mode. Please do not enable interruption during communication (at the time of "UACT=1"
setup). The bus change interruption is generated whichever it has chosen of Host and Peripheral mode.
2.7.5
Full-Speed detach detect interrupt
When Host mode, interruption can be generated when peripheral device is detached at the time of Full-Speed
mode. This interruption enable with the DTCHE bit of INTENB1 register.
2.7.6
Setup transaction error detect interupt
Interruption can be generated when the ACK packet from peripheral device isn’t able to be received at the
time of sending setup transaction at Host mode. This interruption enable with the SIGN bit of INTENB1 register.
2.7.7
Setup transaction complete interrupt
Interruption can be generated when the ACK packet from peripheral device is received at the time of sending
setup transaction at Host mode. This interruption enable with the SACKE bit of INTENB1 register.
2.7.8
Operations in the low-power sleep state
The VBSE, RSME, BCHG interrupts are generated in the low-power sleep state as well..
rev.1.00
2006.3.14
page 33 of 127
M66596FP/WG
2.8 SOF control register
SOF pin configuration register [SOFCFG]
15
14
13
12
11
10
9
<Address: 3CH>
8
7
6
5
4
3
2
1
0
0
0
?
?
?
?
?
?
?
?
S/W
H/W
Note
R/W
R
3.10.1
*1),*2)
SOFM
?
?
?
?
?
?
?
?
?
?
?
?
Bit
?
?
?
?
?
?
?
?
?
?
?
?
Name
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Function
15-4 Nothing is placed here. These should be fixed at “0”.
3-2 SOFM
This selects the SOF pulse output mode.
SOF pin function setting
00: SOF pulse output disabled
01: SOF pulse output in units of 1 ms
10: uSOF output in units of 125 us
11: Reserved
1-0 Nothing is placed here. These should be fixed at “0”.
0
0
<<Notes>>
*1) With Full-Speed operation, (when “HSE=0” has been set, or the RHST bit indicates “RHST=0” as the result of
the reset handshake), “SOFM=10” should not be set.
*2) This bit should be set after a reset handshake has been completed, or when recovering from the low-power
sleep state, and should not be changed during subsequent USB communication.
rev.1.00
2006.3.14
page 34 of 127
M66596FP/WG
2.9 Interrupt statuses
Interrupt status register 0[INTSTS0]
15
14
VBINT RESM
0
0
0
0
-
13
SOFR
0
0
0
Bit
12
DVST
0
0
1
0
11
CTRT
0
0
0
10
BEMP
0
0
0
<Address: 40H>
9
NRDY
0
0
0
Name
8
7
BRDY VBSTS
?
0
0
?
0
6
0
0
0
0
5
DVSQ
0
0
0
0
4
0
0
1
0
3
VALID
0
0
0
Function
2
0
0
0
1
CTSQ
0
0
0
S/W
H/W
Note
R/W
W
3.2.9
3.2.10
*3)
3.2.10
*3)
3.2.8
*3)
3.2.6
*3)
3.2.7
*3)
15 VBINT
VBUS interrupt status
0: VBUS interrupts not issued
1: VBUS interrupts issued
14 RESM
Resume interrupt status
13 SOFR
Frame number refresh interrupt status
12 DVST
Device state transition interrupt status
11 CTRT
Control transfer stage transition interrupt
status
0: Resume interrupts not issued
R/W
1: Resume interrupts issued
0: SOF interrupts not issued
R/W(0)
1: SOF interrupts issued
0: Device state transition interrupts not issued R/W(0)
1: Device state transition interrupts issued
0: Control transfer stage transition interrupts R/W(0)
not issued
1: Control transfer stage transition interrupts
issued
0: BEMP interrupts not issued
R
1: BEMP interrupts issued
0: NRDY interrupts not issued
R
1: NRDY interrupts issued
0: BRDY interrupts not issued
R
1: BRDY interrupts issued
0: VBUS pin is “L” level
R
1: VBUS pin is “H” level
000: Powered state
R
001: Default state
010: Address state
011: Configured state
1xx: Suspended state
10 BEMP
Buffer Empty interrupt status
9 NRDY
Buffer Not Ready interrupt status
8 BRDY
Buffer Ready interrupt status
7 VBSTS
VBUS input status
6-4 DVSQ
Device state
3
VALID
Setup packet reception
2-0 CTSQ
Control transfer stage
0: Not detected
1: Setup packet reception
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (NoData) status stage
110: Control transfer sequence error
111: Reserved
W
W
W
W
W
0
0
0
0
W
3.2.5
*1)
3.2.4
*1)
3.2.3
*1)
3.2.9
*2)
3.2.6
R/W(0)
W
3.2.7
R
W
3.2.7
W
W
W
<<Note>>
*1) The BEMP, BRDY and NRDY bits are cleared when all of the factors for each pipe on correcponding registers
have been eliminated, i.e. BEMPSTS, BRDYSTS and NRDYSTS.
*2) The VBUS input status based on the VBSTS bit requires that chattering be eliminated using software.
*3) If multiple factors are being generated among the VBINT, RESM, SOFR, DVST, and CTRT bits, an access cycle
of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.
rev.1.00
2006.3.14
page 35 of 127
M66596FP/WG
Interrupt status register 1[INTSTS1]
15
?
?
?
?
14
BCHG
0
0
-
13
SOFR
0
0
0
Bit
12
DTCH
0
0
0
11
?
?
?
?
10
BEMP
0
0
0
Name
<Address: 42H>
9
NRDY
0
0
0
8
BRDY
0
0
0
7
6
?
?
?
?
?
?
?
?
5
SIGN
0
0
0
4
SACK
0
0
0
Function
15 Nothing is placed here. These should be fixed at “0”.
14 BCHG
0: BCHG Interrupts not issued
USB bus change interrupt status
1: BCHG Interrupts issued
13 SOFR
This bit is a mirror bit of a 40H SOFR bit.
Frame number refresh interrupt status 0: SOF Interrupts not issued
1: SOF Interrupts issued
12 DTCH
0: DTCH Interrupts not issued
Full-Speed detach detect interrupt status 1: DTCH Interrupts issued
11 Nothing is placed here. This should be fixed at “0”.
10 BEMP
This bit is a mirror bit of a 40H BEMP bit.
Buffer Empty interrupt status
0: BEMP interrupts not issued
1: BEMP interrupts issued
9 NRDY
This bit is a mirror bit of a 40H NRDY bit.
Buffer Not Ready response interrupt
0: NRDY interrupts not issued
status
1: NRDY interrupts issued
8 BRDY
This bit is a mirror bit of a 40H BRDY bit.
Buffer Ready interrupt status
0: BRDY interrupts not issued
1: BRDY interrupts issued
7-6 Nothing is placed here. This should be fixed at “0”.
5 SIGN
0: SIGN interrupts not issued
Setup transaction error detect interrupt 1: SIGN interrupts issued
status
4 SACK
0: SACK interrupts not issued
Setup transaction complete interrupt
1: SACK interrupts issued
status
3-0 Nothing is placed here. This should be fixed at “0”.
3
2
1
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
S/W
H/W
Note
R/W
W
3.2.11
R/W(0)
W
3.2.8
2.9.1
R/W
W
3.2.12
*4),*5)
R
W
2.9.1
3.2.5
R
W
2.9.1
3.2.4
R
W
2.9.1
3.2.3
R/W
R
3.2.14
*4)
R/W
R
3.2.13
*4)
<<Notes>>
*4) DTCH, SIGN, SACK bit are effective only at the time of a Host mode.
*5) The DTCH bit is effective only at the time of Full-Speed mode.
Please perform detach detection by S/W, such as detecting ignore packet from peripheral device at the time of
Hi-Speed mode.
rev.1.00
2006.3.14
page 36 of 127
M66596FP/WG
BRDY interrupt status register [BRDYSTS]
<Address: 46H>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
4
3
PIPEBRDY
0
0
0
0
0
0
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPEBRDY
0: Interrupts are not issued.
BRDY interrupt status for theeach pipe 1: Interrupts are issued.
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W(0) W(1)
3.2.3
*6)
<<Note>>
*6) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an
access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.
NRDY interrupt status register [NRDYSTS]
<Address: 48H>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
4
3
PIPENRDY
0
0
0
0
0
0
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPENRDY
0: Interrupts are not issued.
NRDY interrupt for the each pipe
1: Interrupts are issued.
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W(0) W(1)
3.2.4
*7)
<<Note>>
*7) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an
access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.
BEMP interrupt status register [BEMPSTS]
<Address: 4AH>
15
14
13
12
11
10
9
8
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Bit
Name
Function
15-8 Nothing is placed here. These should be fixed at “0”.
7-0 PIPEBEMP
0: Interrupts are not issued.
BEMP interrupt for the each pipe
1: Interrupts are issued.
4
3
PIPEBEMP
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W(0) W(1)
3.2.5
*8)
<<Note>>
*8) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an
access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.
2.9.1
Mirror bits of INTSTS0 registor and INTSTS1
SOFR, BEMP, NRDY, BRDY bit of INTSTS1 register are mirror bits of INTSTS0 register. When software reads,
the same value as the same bit of INTSTS0 register can be read. When it writes, the same value as the same bit of
INTSTS0 register is written in.
rev.1.00
2006.3.14
page 37 of 127
M66596FP/WG
2.10 Frame number register
Frame number register [FRMNUM]
15
14
OVRN CRCE
0
0
0
0
0
0
13
12
?
?
?
?
?
?
?
?
Bit
11
SOFRM
0
0
0
<Address: 4CH>
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
5
FRNM
0
0
0
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
W
2.10.1
*1)
2.10.1
Function
15 OVRN
0: No error
R/W(0)
Overrun / Underrun
1: Error issued
14 CRCE
0: No error
R/W(0)
Reception data error
1: Error issued
13-12 Nothing is placed here. These should be fixed at “0”.
11 SOFRM
0: Interrupt asserted upon SOF reception and R/W
Frame number update interrupt mode timer interpolation.
1: Interrupt asserted if SOF is damaged or
missing.
10-0 FRNM
The frame number can be confirmed.
R
Frame number
W
R
2.10.2
3.2.8
*1)
W
2.10.2
<<Note>>
*1) Frame number update interrupts are not issued for uSOF packet detection other than “UFRNM=0”.
micro frame number register [UFRMNUM]
<Address: 4EH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Bit
Name
Function
15-3 Nothing is placed here. These should be fixed at "0".
2-0 UFRNM
The micro frame number can be confirmed.
micro frame
<<Note>>
*2) When using Full-Speed operation, “000” is normally read with this bit.
rev.1.00
2006.3.14
page 38 of 127
0
0
0
0
1
UFRNM
0
0
0
S/W
H/W
Note
R
W
2.10.2
*2)
0
0
0
M66596FP/WG
2.10.1 Isochronous errors
With this controller, data transfer errors that occur in isochronous transfers can be confirmed using the OVRN
bit and the CRCE bit of the FRMNUM register. In isochronous transfers, error notification by the NRDY
interrupt can be differentiated using the OVRN bit and the CRCE bit between data buffer errors and packet
errors.
Table 2.9 and Table 2.10 show the conditions under which the OVRN bit and CRCE bit are set to “1”.
Table 2.9 Error information when an NRDY interrupt is issued in an isochronous transfer reciving direction
Bit status
“OVRN=1"
Issued when:
Data packet is
received
“CRCE=1"
Data packet is
received
Issue conditions
Detected error
A new data packet is received Reception data buffer
overrun
before reading of buffer
memory is completed
A CRC error, or, a bit stuffing Received packet error
error is detected
Operation
The new data packet is
thrown out
The new data is packet
thrown out
Table 2.10 Error information when an NRDY interrupt is issued in an isochronous transfer sending direction
Bit status
"OVRN=1"
Issued when:
IN token is
received
"CRCE=1"
Not issued
Issue conditions
Detected error
Operation
An in-token is received before Transmission data buffer Zero-Length packet
underrun
transmission
writing to buffer memory is
completed
2.10.2 SOF interrupts and frame numbers
The SOFR interrupt operation mode should be selected using the SOFRM bit of the FRMNUM register. Also,
the current frame number can be confirmed using the FRNM bit of the FRMNUM register and the UFRNM bit of
the UFRNUM register.
In the peripheral mode, with this controller, the frame numbers are refreshed at the timing at which SOF
packets are received. If the controller is unable to detect an SOF packet because the packet has been corrupted,
or for another reason, the FRNM value is retained until a new SOF packet is received. At that point, the FRNM
bit based on the SOF interpolation timer is not refreshed. Also, the UFRNM bit is incremented in response to a
uSOF packet being received.
rev.1.00
2006.3.14
page 39 of 127
M66596FP/WG
2.11 USB address (low-power recovery)
USB address/low-power status recovery register [RECOVER]
15
14
13
12
11
10
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
Bit
9
STSRECOV
0
0
<Address: 50H>
8
7
6
5
4
0
0
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
Name
3
USBADDR
0
0
0
0
Function
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R
3.1.7
*1),*2)
R/W
3.1.7
*1),*2)
15-11 Nothing is placed here. These should be fixed at “0”.
10-8 STSRECOV
Status recovery after the low-power sleep state R/W
Status recovery
000: reserved
001: Full-Speed Default state
010: Full-Speed Address state
011: Full-Speed Configured state
100: reserved
101: Hi-Speed Default state
110: Hi-Speed Address state
111: Hi-Speed Configured state
7 Nothing is placed here. This should be fixed at "0".
6-0 USBADDR
USB address confirmation and recovery
R/W
USB address
<<Notes>>
*1) When a recovery has been made from the low-power sleep state to the normal mode, the communication speed,
device state and USB address have to be returned to the values backed up by the control program software.
“STSRECOV=x00” should not be set.
*2) RECOVER register is effective only at the time of peripheral mode. When operating in host mode, the
peripheral address should be set by DEVSEL bit of PIPEMAXP register.
2.12 USB request register
The USB request register is used to store setup requests for control transfers. The values of USB requests that
have been received are stored here when peripheral mode is selected. The USB requests to be sent should be set here
when host mode is selected.
USB request type register [USBREQ]
15
14
13
0
0
0
0
0
0
0
0
0
0
0
0
12
11
bRequest
0
0
0
0
0
0
0
0
Bit
9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
15-8 bRequest
Request
7-0 bmRequestType
Request type
<<Note>>
None in particular
rev.1.00
2006.3.14
<Address: 54H>
10
page 40 of 127
Function
4
3
bmRequestType
0
0
0
0
0
0
0
0
S/W
The USB request bRequest value is peripheral
stored here.
mode:R
Host mode:R/W
The USB request bmRequestType peripheral
is stored here.
mode:R
Host mode:R/W
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
H/W
peripheral
mode:W
Host mode:R
peripheral
mode:W
Host mode:R
Note
3.6.1
3.6.2
3.6.1
3.6.2
M66596FP/WG
USB request value register [USBVAL]
15
14
13
12
11
10
<Address: 56H>
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
wValue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
0
0
0
0
0
0
0
0
0
0
0
0
Name
0
0
0
0
Function
15-0 wValue
Value
S/W
The USB request wValue
value is stored here.
H/W
Note
peripheral
peripheral
mode:R
mode:W
Host mode:R/W Host mode:R
3.6.1
3.6.2
<<Note>>
None in particular
USB request index register [USBINDX]
<Address: 58H>
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
8
7
Windex
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
15-0 wIndex
Index
S/W
The USB request wIndex
value is stored here.
H/W
Note
peripheral
peripheral
mode:R
mode:W
Host mode:R/W Host mode:R
3.6.1
3.6.2
<<Note>>
None in particular
USB request length register [USBLENG]
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
15-0 wLength
Length
2006.3.14
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
The USB request wLength
value is stored here.
<<Note>>
None in particular
rev.1.00
<Address: 5AH>
8
7
wLength
0
0
0
0
0
0
0
0
page 41 of 127
S/W
H/W
peripheral
peripheral
mode:R
mode:W
Host mode:R/W Host mode:R
Note
3.6.1
3.6.2
M66596FP/WG
2.13 DCP configuration
When data communication is being carried out using control transfers, the default control pipe should be used.
DCP configuration register [DCPCFG]
<Address: 5CH>
15
14
13
12
11
10
9
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Bit
Name
8
CNTMD
0
0
0
7
6
5
?
?
?
?
?
?
?
?
?
?
?
?
4
DIR
00
0
3
2
1
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
S/W
H/W
Note
R/W
R
3.4.1
*1)
R/W
R
3.6.1
*2)
Function
15-9 Nothing is placed here. These should be fixed at “0”.
8 CNTMD
0: Non-continuous transfer mode
Continuous transfer mode
1: Continuous transfer mode
7-5 Nothing is placed here. These should be fixed at “0”.
4 DIR
Control transfer direction in the host mode.
Transfer direction
0: Receiving (Control read data stage and
Control write status stage)
1: Sending (Control write data stage and
Control read status stage)
7-0 Nothing is placed here. These should be fixed at “0”.
<<Notes>>
*1) Because the DCP buffer memory is used for both control read transfers and control write transfers, the CNTMD
bit will serve as the bit common to both, regardless of the transfer direction.
*2) This bit should be set to “0” in the peripheral mode.
DCP maximum packet size register [DCPMAXP]
15
14
DEVSEL
0
0
0
0
0
0
<Address: 5EH>
13
12
11
10
9
8
7
6
5
4
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
1
1
1
0
0
0
0
0
0
Bit
Name
Function
3
MXPS
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R
3.6.1
*3)
R
3.3
*4)
This specifies the device adress for the DCP at R/W
Host mode.
00 : Address 0
01 : Address 1
02 : Address 2
03 : Address 3
13-7 Nothing is placed here. These should be fixed at “0”.
6-0 MXPS
This specifies the maximum packet size for the R/W
Maximum packet size
DCP.
15-14 DEVSEL
Device select
<<Notes>>
*3) This bit should be set “00” in the peripheral mode.
*4) This should not be set to anything other than the USB specification. Also, because b2-b0 bits are fixed at “0”,
writing to these is invalid.
rev.1.00
2006.3.14
page 42 of 127
M66596FP/WG
DCP control register [DCPCTR]
15
14
BSTS SUREQ
0
0
0
0
0
0
13
?
?
?
?
Bit
12
?
?
?
?
11
?
?
?
?
<Address: 60H>
10
?
?
?
?
Name
15 BSTS
Buffer Status
14 SUREQ
Request to transmit SETUP packet
9
?
?
?
?
8
7
6
SQCLR SQSET SQMON
1
0
0
1
0
0
1
0
0
5
?
?
?
?
Function
4
?
?
?
?
3
?
?
?
?
2
CCPL
0
0
0
0
1
S/W
H/W
0
PID
0
0
0
0
0: Buffer access is disabled.
R
W
1: Buffer access is enabled.
A SETUP packet is transmitted by setting this R/W(1) R/W(0)
bit to 1.
0: Invalid
1: transmit SETUP packet
14-9 Nothing is placed here. These should be fixed at “0”.
8 SQCLR
0: Invalid
R(0)/
R
Toggle Bit Clear
1: Specifies DATA0
W(1)
7 SQSET
0: Invalid
R(0)/
R
Toggle Bit Set
1: Specifies DATA1
W(1)
6 SQMON
0: DATA0
R
W
Toggle Bit Confirm
1: DATA1
5-3 Nothing is placed here. These should be fixed at “0”.
2 CCPL
0: Invalid
R(0)/ R/W(0)
Control Transfer End enabled
1: The control transfer is ended.
W(1)
R/W
R/W
1-0 PID
00: NAK response
Response PID
01: BUF response (in keeping with the buffer
state)
10: STALL response
11: STALL response
0
0
0
0
Note
3.4.1.1
*5)
3.6.1
*11)
3.3
*7),*8)
3.3
*7),*8)
3.3
*9)
3.6.2
*6)
0
3.6
*10)
<<Notes>>
*5) The direction of buffer access, writing or reading, is depend on setting of ISEL bit.
*6) In the peripheral mode the CCPL bit is cleared to “0” right after the SETUP token has been received.
In the host mode this bit should be set “CCPL=0”(not use).
*7) If the SQSET bits and the SQCLR bits of the DCPCTR register and the PIPExCTR registers are being changed
in succession (the PID sequence toggle bits of multiple pipes are being changed in succession), an access cycle of
at least 200 ns is required.
*8) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,
“PID=NAK” should be set.
*9) In the Peripheral mode the SQMON bit is initialized to “1” by the controller right after the SETUP token of the
control transfer has been received.
*10) In the peripheral mode the PID bit is cleared to “00” right after the SETUP token has been received. And at the
time of occurring of a transmission error etc., PID bits are set up by the controller and transmission is ended.
*11) When SUREQ bit is set to 1, it is set to 0 by H/W after SETUP transaction sending out.
While the SUREQ bit is 1, do not write in USBREQ, USBVAL, USBINDX, and a USBLENG register.
rev.1.00
2006.3.14
page 43 of 127
M66596FP/WG
2.14 Pipe configuration register
The PIPE1-7 settings should be set using the PIPESEL, PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, and
PIPExCTR registers.
After selecting the pipe using the PIPESEL register, set the functions of the pipe using the PIPECFG, PIPEBUF,
PIPEMAXP and PIPEPERI registers. The PIPExCTR register can be set separately from the pipe selection specified
with the PIPESEL register, with no relation between them.
For an H/W reset, S/W reset, USB bus reset, and when shifting to the low-power sleep state, the pertinent bits for
not only the selected pipe, but all of the pipes are initialized.
Pipe window selection register [PIPESEL]
<Address: 64H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Bit
Name
15-3 Nothing is placed here. These should be fixed at “0”.
2-0 PIPESEL
000: Not selected
Pipe window selection
001: Pipe 1
010: Pipe 2
011: Pipe 3
100: Pipe 4
101: Pipe 5
110: Pipe 6
111: Pipe 7
Function
0
0
0
0
1
PIPESEL
0
0
0
S/W
H/W
Note
R/W
R
*1)
<<Note>>
*1) When"PIPESEL=000" is set, “0” is read from all of the bits of the five related registers noted above.
rev.1.00
2006.3.14
page 44 of 127
0
0
0
M66596FP/WG
Pipe configuration register [PIPECFG]
15
14
13
12
11
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
TYPE
0
0
0
0
Bit
10
BFRE
0
0
0
Name
15-14 TYPE
Transfer type
<Address: 66H>
9
8
7
DBLB CNTMD SHTNAK
0
0
0
0
0
0
0
0
0
6
5
?
?
?
?
?
?
?
?
4
DIR
0
0
0
3
0
0
0
Function
00: Pipe use disabled
01: Bulk transfer
10: Interrupt transfer
11: Isochronous transfer
13-11 Nothing is placed here. These should be fixed at “0”.
10 BFRE
0: BRDY interrupt upon sending or receiving of
BRDY interrupt operation specified
data
1: BRDY interrupt upon reading of data
9 DBLB
0: Single buffer
Double buffer mode
1: Double buffer
8 CNTMD
0: Non-continuous transfer mode
Continuous transfer mode
1: Continuous transfer mode
7 SHTNAK
0: Pipe continued at end of transfer
Pipe disabled at end of transfer
1: Pipe disabled at end of transfer
6-5 Nothing is placed here. These should be fixed at “0”.
4 DIR
0: Receiving (OUT transfer)
Transfer direction
1: Sending (IN transfer)
3-0 EPNUM
Specifies the end point number for the pertinent
End point number
pipe
2
1
EPNUM
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
3.3
*2)
R/W
R
3.4.3.6
*3)
R/W
R
R/W
R
R/W
R
3.4.1.5
*4)
3.4.1.6
*5)
3.3
R/W
R
R/W
R
3.3
<<Notes>>
*2) By the pipe number selected in the PIPESEL bit of a PIPESEL register, the value can be set as follows.
When using PIPE1-5, this bit can select "TYPE=00", "TYPE=01", or "TYPE=11".
When using PIPE6-7, this bit should be set "TYPE=10".
*3) If "BFRE=1” is set, BRDY interrupts are not generated when the buffer is set to the data writing direction.
*4) The DBLB bit is valid when PIPE1-5 are selected.
The procedure to change the DBLB bit for a PIPE is as following;
(a) Single buffer to double buffer (“DBLB=0” to “DBLB=”1”);
Set the PID bit to “NAK” for the pertinent pipe → “ACLRM=1” → (wait at least 100ns) → “ACLRM=0”
→ “DBLB=”1” → Set the PID bit to “BUF” for the pipe
(b) Double buffer to singlee buffer (“DBLB=1” to “DBLB=”0”);
Set the PID bit to “NAK” for the pertinent pipe → “DBLB=”0” → “ACLRM=1” → (wait at least 100ns) →
“ACLRM=0” → Set the PID bit to “BUF” for the pipe
*5) The CNTMD bit is valid when bulk transfer (“TYPE=01”) is selected using PIPE1-5. “CNTMD=1” should not be
set when isochronous transfer has been selected (“TYPE=11”).
The CNTMD bit should not be set “1” for PIPE6-7.
rev.1.00
2006.3.14
page 45 of 127
M66596FP/WG
Pipe buffer setting register [PIPEBUF]
15
14
13
?
?
?
?
0
0
0
0
0
0
12
BUFSIZE
0
0
0
Bit
<Address: 68H>
11
10
9
8
7
6
5
4
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
Name
3
BUFNMB
0
0
0
Function
15 Nothing is placed here. This should be fixed at “0”.
14-10 BUFSIZE
Specifies the size of the pertinent pipe.
Buffer Size
(from 0: 64 bytes to 0x1F: 2KB)
9-7 Nothing is placed here. These should be fixed at “0”.
6-0 BUFNMB
Specifies the buffer number for the pertinent
Buffer Number
pipe.(From 0x4 to 0x5F)
2
1
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R/W
R
3.4.1
*6)
R/W
R
3.4.1
*7)
<<Notes>>
*6) The valid value for the BUFSIZE bit depends on the selected PIPE by the PIPESEL bit of the PIPESEL register.
When using PIPE1-5, this bit can select “BUFSIZE=00-1F”
When using PIPE6-7, writing to this bit is invalid.
*7) The BUFNMB bit can be set to match the user system when PIPE1-5 are selected.
"BUFNMB=0-3"is used exclusively for the DCP."BUFNMB=4-5"is allocated to PIPE6-7.
When using PIPE6, writing to this bit is invalid, and "BUFNMB=4” is always used for reading.
When using PIPE7, writing to this bit is invalid, and “BUFNMB=5” is always used for reading.
Pipe maximum packet size register [PIPEMAXP]
15
14
DEVSEL
0
0
0
0
0
0
<Address: 6AH>
13
12
11
10
9
8
7
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
6
5
MXPS
0
0(1)*9)
0
0(1)
0
0(1)
Function
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/W
H/W
Note
R
*8)
R
3.3
*9),
*10)
This specifies the device adress for the DCP in R/W
the Host mode.
00 : Address 0
01 : Address 1
02 : Address 2
03 : Address 3
14 Nothing is placed here. These should be fixed at “0”.
10-0 MXPS
Specifies the maximum packet size for the
R/W
Maximum Packet Size
pertinent pipe.
15 DEVSEL
Device select
<<Note>>
*8) This bit should be set “00” in the peripheral mode.
*9) The MXPS bit should be set to"0x00”, or the setting defined by the USB specification should be used.
*10) The default value of MXPS bit is "0x0" when "PIPSEL=0", and "0x40" when select "PIPESEL>0".
rev.1.00
2006.3.14
page 46 of 127
M66596FP/WG
Pipe timing control register [PIPEPERI]
15
14
13
?
?
?
?
?
?
?
?
?
?
?
?
Bit
12
IFIS
0
0
0
<Address: 6CH>
11
10
9
8
7
6
5
4
3
2
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Name
Function
15-13 Nothing is placed here. These should be fixed at “0”.
12 IFIS
0: The buffer is not flushed.
Isochronous IN buffer flush
1: The buffer is flushed.
11-3 Nothing is placed here. These should be fixed at “0”.
2-0 IITV
Specifies the interval timing as IITV-th power
Interval error detection spacing
of 2.
0
0
0
0
1
IITV
0
0
0
S/W
H/W
Note
R/W
R
3.9.5
R/W
R
3.9.3
*11)
0
0
0
<<Note>>
*11) In the peripheral mode the IITV bit is valid only when isochronous transfer is selected. It can be set only when
PIPE1-2 are selected.
For OUT-direction: An interval error occurs upon a NRDY interrupt caused by a token not having been issued.
For IN-direction: When the controller doesn't receive IN-token until the time indicated by IITV bit, it detects an
interval error and flushs the buffer.
In the host mode the IITV bit is valid only when isochronous and interrupt transfer is selected. The IITV bit
controls the interval of a transaction.
rev.1.00
2006.3.14
page 47 of 127
M66596FP/WG
PIPE1 control register [PIPE1CTR]
PIPE2 control register [PIPE2CTR]
PIPE3 control register [PIPE3CTR]
PIPE4 control register [PIPE4CTR]
PIPE5 control register [PIPE5CTR]
PIPE6 control register [PIPE6CTR]
PIPE7 control register [PIPE7CTR]
15
14
BSTS INBUFM
0
0
0
0
0
0
13
?
?
?
?
Bit
12
?
?
?
?
11
?
?
?
?
10
?
?
?
?
Name
15 BSTS
Buffer Status
14 INBUFM
Sending buffer status monitor
<Address: 70H>
<Address: 72H>
<Address: 74H>
<Address: 76H>
<Address: 78H>
<Address: 7AH>
<Address: 7CH>
9
8
7
6
ACLRM SQCLR SQSET SQMON
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
1
0
PID
?
?
?
?
?
?
?
?
?
?
?
?
Function
0: Buffer access is disabled.
1: Buffer access is enabled.
0: No data which can be transmitted in a buffer
1: The data which can be transmitted is in a buffer
memory.
13-10 Nothing is placed here. These should be fixed at “0”.
0: Disabled
9 ACLRM
Auto Buffer Clear mode
1: Enabled (all buffers are initialized)
8 SQCLR
0: Invalid
Toggle Bit Clear
1: Specifies DATA0
7 SQSET
0: Invalid
Toggle Bit Set
1: Specifies DATA1
6
2
0
0
0
0
?
?
?
?
0
0
0
0
S/W
H/W
Note
R
W
R
W
3.4.1.1
*12)
3.4.1.1
*13),
*14)
R(0)/ R/W(0) 3.4.1.4
W(1)
*15)
R(0)/
R 3.3*16),
W(1)
*17)
R(0)/
R
3.3
W(1)
*16),
*17)
R
W
3.3
SQMON
0: DATA0
Toggle Bit Confirm
1: DATA1
5-2 Nothing is placed here. These should be fixed at “0”.
R/W
R/W
3.3
1-0 PID
00: NAK response
0
Response PID
01: BUF response (in keeping with the buffer state)
*18)
10: STALL response
11: STALL response
<<Notes>>
*12) The direction of buffer access, writing or reading, is depend on setting of the DIR bit of the PIPECFG register.
*13) The INBUFM bit is valid when softwware sets the DIR bit to Sending-direction.
*14) The INBUFM bit is valid for PIPE1-5.
*15) Software should not set “ACLRM=1” for the PIPE whith selected by the CURPIPE bit of the CFIFOSEL,
DxFIFOSEL register. After "ACLRM=1", when setting up "ACLRM=0", Software need to wait at lease 100ns.
*16) If the SQCLR bits and the SQSET bits of the DCPCTR register and the PIPExCTR registers are being used to
change the data PID sequence toggle bit for several pipes in succession, an access cycle of at least 200 ns is
required.
*17) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,
“PID=NAK” should be set.
*18) The operation is as follows, when setting up PID=BUF.
Host mode and the transmitting direction (OUT).
A transaction is issued when there is transmitting data in a buffer.
A transaction is not issued when there is no transmitting data in a buffer.
Host mode and the receiving direction (IN).
A transaction is issued when there is no receiving data in a buffer.
A transaction is not issued when there is receiving data in a buffer.
Peripheral mode and the transmitting direction (OUT).
A ACK response and receiving a data , when there is no receiving data in a buffer.
A NAK response is carried out to a token, when there is a receiving data in a buffer.
Peripheral mode and the receiving direction (IN).
A Data is transmitted to a IN token.
A NAK response is carried out to a IN token, when there is a transmitting data in a buffer.
And at the time of occurring of a transmission error etc., PID bits are set up by the controller and transmission
is ended.
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M66596FP/WG
3 Description
of Operation
3.1 System control and oscillation control
This chapter describes the register operations that are necessary to the default settings of the controller, and the
registers necessary for power consumption control.
3.1.1
Resets
Table 3.1 shows a table of controller resets. For information on the initialized states of the registers following the
various reset operations, please refer to Chapter 2, Registers.
Table 3.1 Types of Resets
Name
H/W reset
S/W reset
Operation
”L” level input from the RST_N pin
Operation using the USBE bit of the SYSCFG
register
Automatically detected by the controller from the
D+ and D- lines in tne Peripheral mode
USB bus reset
3.1.2
Bus interface settings
Table 3.2 shows the bus interface settings for the controller.
Table 3.2 Bus interface settings
3.1.3
Register name
PINCFG
PINCFG
Bit name
LDRV
BIGEND
DMAxCFG
DMAxCFG
DMAxCFG
DMAxCFG
INTENB1
DREQA
DACKA
DENDA
OBUS
INTL
Setting contents
Control setting for the drive current
Byte Endian setting for the CPU being connected
This bit is effective in access to a FIFO register
Active setting for the DREQx_N pin
Active setting for the DACKx_N pin
Active setting for the DENDx_N pin
OBUS mode setting
Output sensing setting for the INT_N pin
Selection of the function
This controller can select either a Host function or a Peripheral function by software. To select USB function for
the controller, set the DCFM bit of the SYSCFG register. Changing the DCFM bit (writing access) should be done
with the internal clock stopped (“SCKE=0”).
3.1.4
Enabling Hi-Speed operation
With this controller, either Hi-Speed operation or Full-Speed operation can be selected as the USB communication
speed (communication bit rate), using software. To enable Hi-Speed operation for the controller, set the HSE bit of
the SYSCFG register to “1”. Changing the HSE bit should be done with the internal clock stopped (“SCKE=0”).
If Hi-Speed operation has been enabled, the controller executes the reset handshake protocol, and the USB
communication speed is set automatically. The results of the reset handshake can be confirmed using the RHST bit
of the DVSTCTR register.
If Hi-Speed operation has been disabled, the controller will use Full-Speed operation.
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M66596FP/WG
3.1.5
USB data bus resistor control
Figure 3.1 shows a diagram of the connections between the controller and the USB connectors.
For the Peripheral mode, the controller has a built-in pull-up resistor for the D+ signal. “1” should be set for the
DPRPU bit of the SYSCFG register, then the D+ line is pulled up. The pull-up power supply is AFE33V.
For the Host mode, the controller has a built-in pull-down resistor for the D+ and D- signals. “1” should be set for
the DPRPD bit of the SYSCFG register, then the D+ and D- lines are pulled down.
Also, the controller has a built-in terminal resistor for use when the D+ and D- signals are operating at Hi-Speed,
and a built-in output resistor for Full-Speed operation. The controller automatically switches the built-in resistor
after connection with the PC, by means of reset handshake, suspended state and resume detection. If a disconnection
from the PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0).
If “0” is set for the DPRPU bit of the SYSCFG register in the Peripheral mode, the pull-up resistor (or the terminal
resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection.
+5V
(at the Host mode)
M66596
Impedance control has to be taken into
consideration when designing the D+
and D- lines.
VBUS
1
2
3
4
DM
DP
RERFIN
5.6KΩ
Vbus
DD+
GND
USB connector
Figure 3.1 UBS connector connections
3.1.6
Clock supply control
Figure 3.2 shows a block diagram of the controller clock control. Frequency of the input clock for the XIN pin
should be selected using the XTAL bit of the SYSCFG register, while the oscillation buffer is enabled using the XCKE
bit and the clock supply is controlled using the RCKE, PLLC, and SCKE bits. For information on the register control
timing, please refer to 3.1.8, State transition timing.
Clock control unit
Input
clock
XCKE
(bit13)
RCKE
(bit12)
PLLC, SCKE
(bit11, bit10)
Oscillation
buffer
Low-power
control
Divider
circuit
PLL
PCUT
(bit1)
Auto clock supply
ATCKM
(bit8)
Figure 3.2 Clock control block
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Internal
clock
M66596FP/WG
3.1.7 Low power consumption control
3.1.7.1 Overview of Low-power sleep state
In order to reduce power consumption, the controller is equipped with a function for setting a low-power sleep
state.
Controlling the clock and the low-power sleep state enables reduced power consumption when communication is not
being carried out, such as in the suspended state or disconnected state. In order to coordinate the relationship
between the controller clock supply being enabled and disabled in low-power sleep state, the values shown in Table
3.3 indicate the correspondence between the controller state and the value of the SYSCFG register, while Figure
3.3 shows the transitions in the controller state.
For the timing at which the transitions between the various states take place, and the register control timing, please
refer to 3.1.8 .
Table 3.3 Correspondence between the controller state and SYSCFG register value
Controller state
H/W reset
Normal operating state
Low-power sleep state
Values of the various SYSCFG register bits
XTAL=0, XCKE=0, RCKE=0, PLLC=0, SCKE=0,
ATCKM=0, HSE=0, DPRPD=0, DPRPU=0,
FSRPC=0, PCUT=0, USBE=0
XTAL=xx *1), XCKE=1, RCKE=1, PLLC=x *1),
SCKE=1, ATCKM=x *1), HSE=x *1), DPRPD=x*1),
DPRPU=x *1), FSRPC=x *1), PCUT=0, USBE=1
XTAL=xx *1), XCKE=0, RCKE=0, PLLC=0,
SCKE=0, ATCKM=x *1), HSE= x *1), DPRPD=x*1),
DPRPU=x *1), FSRPC=x *1), PCUT=1, USBE=1
Explanation
In this state, the clock is supplied to
the controller, and USB
communication is enabled.
In this state, USB communication is
not carried out, such as when
communication is suspended or a
cable is disconnected.
*1) x indicates that the value is set by the user is retained.
H/W reset
Default setting
Attached
Suspended,
detached
Normal operating
state
Low-power sleep
Resume,
attached
Figure 3.3 Controller state transitions (using low-power sleep state)
At the Hsot mode, if Remote Wake Up signal is received when suspend state, it is necessary to supply an internal
clock (SCKE) within 1ms after signal detection, and to start a resume signal output. For this reason, when you
enable Remote Wake Up , do not stop the internal clock, and a setup of a Low-power sleep state.
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M66596FP/WG
3.1.7.2 Overview of Clock stop state
This controller is equipped with the setting function of the low power consumption state by clock stop as well as
M66291, M66591, and M66592. Software is transplantable for this controller from M66291, M66591, and M66592 by
fewer changes.
In the states where the controller is not communicating such as suspend and a not connect state, low power
consumption by clock stop is realized. Correspondence of the state of the controller and the value of a SYSCFG
register is shown in Table 3.4. The transitions in the controller state is shown in Figure 3.4.For the timing at which
the transitions between the various states take place, and the register control timing, please refer to 3.1.8.
Moreover, when you use the low power consumption state by clock stop, please use the auto clock supply function
("ATCKM=1").
Table 3.4 Correspondence betweek the controller state and SYSCFG register value
Controller state
H/W reset
Values of the various SYSCFG register bits
XTAL=00,XCKE=0,RCKE=0,PLLC=0,SCKE=0,ATK
CM=0,HSE=0,DPRPU=0,FSRPC=0,PCUT=0,USB
E=0
Normal operating state XTAL=xx *1),XCKE=1,RCKE=1,PLLC=x
*1),SCKE=1,ATCKM=1,HSE=x
*1),DPRPD=x*1),DPRPU=x*1),FSRPC=x,PCUT=0,
USBE=1
Clock stop state
XTAL=xx
*1),XCKE=0,RCKE=0,PLLC=0,SCKE=0,ATCKM=1
,HSE= x
*1),DPRPD=x*1),DPRPU=x*1),FSRPC=x*1),PCUT
=0,USBE=1
*1) x indicates that the value is set by the user is retained.
Explanation
In this state, the clock is supplied to
the controller, and USB
communication is enabled.
In this state, USB communication is
not carried out, such as when
communication is suspended or a
cable is disconnected.
H/W reset
Default setting,
Attached
Suspend,
Detached
Normal operating
state
Clock stop
Resume,
Attached
Figure 3.4 Controller state transitions(Clock stop mode)
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M66596FP/WG
3.1.7.3 Low-power sleep state
The low-power sleep state is set by setting “1” for the PCUT bit of the SYSCFG register. For information on the
sequence in which settings are entered for the low-power sleep state, please refer to Chapter 3.1.8.2 , and for
information on register control timing, please refer to the timing diagram noted later (Figure 3.6 Low-power control
timing diagram).
In the low-power sleep state, of the registers set by software, only registers other than those noted below are
initialized. After returning to the normal operating state, the settings must be re-entered using software. Table 3.5
shows the registers that are not initialized when the controller is in the low-power sleep state.
Table 3.5 Registers that are not initialized in the low-power sleep state
Register
SYSCFG
PINCFG
DMAxCFG
INTENB0/
INTSTS0
Bit
XTAL
ATCKM
HSE
DCFM
DMRPD
DPRPU
FSRPC
USBE
LDRV
DREQA
VBSE / VBINT
RSME / RESM
INTENB1/
INTSTS1
rev.1.00
BCHGE / BCHG
2006.3.14
Description
This is retained as system information.
This is retained as system information.
This is retained as system information.
This is retained as system information.
This is retained as system information.
This is retained as system information.
This is retained as system information.
This is retained as system information.
The state of the output pin drive current settings is retained.
The polarity of the DREQ0_N pin and the DREQ1_N pin are retained.
When "VBSE=1", if there was any change to the VBUS signal in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
When "RSME=1", if there was any change to the USB data bus in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
When "BCHGE=1", if there was any change to the USB data bus in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
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M66596FP/WG
3.1.7.4 Recovering from the low-power sleep state
If any of the events noted below occurs from the low-power sleep state, the controller notifies the CPU through the
INT_N pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the
low-power sleep state.
VBUS detection
: If a change in the VBUS pin was detected in the low-power sleep state
RESUME detection
: If a change in the state of the USB bus (J-State to K-State or SE0)was detected
when the state shifted from the suspended state to the low-power sleep state in the
Peripheral mode.
BUS CHANGE detection : If a change in the state of the USB bus was detected when the state to the
low-power sleep state state during the suspended state
When the PCSE bit of INTENB1 register is set to "0", the low-power sleep state is also canceled by the operations
noted below, and the controller returns to the normal operating state.
Dummy writing to the 0x7E address of the controller (no actual writing is
done to this address).
When the system has returned from the low-power sleep state to the normal state, some of the controller registers
need to be returned to the values in effect prior to the transition to the low-power sleep state. Of the registers for
which the settings have to be returned, special registers are available that are used for re-setting data in the
read-only registers.
Table 3.6 shows the re-settings for the read-only registers for which the settings have to be returned.
Table 3.6 Re-settings for read-only registers for which settings have to be returned
Register
DVSTCTR
INTSTS0
Bit
Method for re-setting registers
Setting the USB communication speed and device state using the STSRECOV bit
of the RECOVER register before shifting to the low-power sleep state recovers the
values for the RHST bit and DVSQ bit.
RECOVER
USBADDR
The USB device address prior to the shift to the low-power sleep state is set in the
USBADDR bit of the RECOVER register.
PIPExCTR
SQMON
The sequence toggle bits for the various pipes prior to the low-power sleep state
are set using the SQSET bit or the SQCLR bit of PIPExCTR. *1)
*1) The SQMON bit of the DCPCTR register is initialized when the SETUP stage ends, so it is not necessary to
return to the state in effect prior to the normal operating state.
RHST
DVSQ
3.1.7.5 Recovering from the clock stop state
If any of the events noted below occurs from the clock stop state, the controller notifies the CPU through the INT_N
pin. The interrupt factor related to those events should be enabled, before sofware sets the controller to the clock stop
state.
VBUS detection
: If a change in the VBUS pin was detected in the clock stop state.
RESUME detection
: In the suspended state of Peripheral mode if a change in the state of the USB bus
(J-State to K-State/SE0)was detected.
BUS CHAGE detection : If a change in the state of the USB bus was detected. It is used when detecting attach
a peripheral , detach a perripheral, and Remote Wake Up in the Host mode.
3.1.7.6 Auto clock supply function
This controller is equipped with an auto clock supply function. With the auto clock supply function, the controller
automatically implements a series of sequence control operations, from the oscillation stabilization standby timing to
the supply of the internal clock, when the system is returning from the low-power sleep state or from the clock stop
mode to the normal operating state. This function is enbaled by setting “1” for the ATCKM bit of the SYSCFG
register and following events are occur.. For information on specific register control, please refer to Chapter
3.1.8.3 .
RESUME detection
In the suspended state of Peripheral mode if a change in the state of the USB bus (J-State to
K-State/SE0)was detected.
If Software set “XCKE=1” of SYSCFG register.
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3.1.7.7 Oscillation enable by Hardware
In the following cases, this controller enables an oscillation automatically ("XCKE=1"). By using in accordance
with an automatic clock supply function, timing design is easy.
-
-
rev.1.00
RESUME detection
In the suspended state of Peripheral mode if a change in the state of the USB bus (J-State to
K-State/SE0)was detected.
Return from the low-power sleep state
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M66596FP/WG
3.1.8 State transition timing
3.1.8.1 Starting the internal clock supply (from the H/W reset state to the normal operating state)
Figure 3.5 shows a diagram of the clock supply start control timing of the controller. The transition from the H/W
reset state to the normal operating state should be done through operation of the bits at the timing noted below.
(1)
Software enables the oscillation buffer.
"XCKE=1"
(2)
Software waits for oscillation to stabilize.
(The oscillation stabilization time varies depending
on the oscillator.)
(3)
Software enables the reference clock suppliance
"RCKE=1", "PLLC=1"
and the PLL operation
(4)
Software waits for the PLL to lock.
(A waiting time of at least 8.3 us is necessary.)
(5)
Software enables the internal clock suppliance. "SCKE=1"
Start of internal
clock supply
procedure
(3)
(1)
(2) Approximately 1.5 ms
(varies depending on oscillation probe)
(5)
(4) min 8.3us
XCKE
RCKE
PLLC
SCKE
PCUT
Figure 3.5 Clock supply start control timing
3.1.8.2 Stopping the internal clock supply (from the normal operating state to the low-power sleep state)
Figure 3.6 shows a diagram of the low-power control timing from the normal operating state to the low-power sleep
state. The transition from the normal operating state to the low-power sleep state should be done through operation
of the bits at the timing noted below.
(1)
Software disables the internal clock suppliance. "SCKE=0"
(2)
Software waits until the internal clock stops. (A waiting time of at least 300 ns is necessary.)
(3)
Software disables the PLL.
"PLLC=0"
(4)
Software waits for the PLL to stop.
(A waiting time of at least 300 ns is necessary.)
(5)
Software disables reference clock suppliance. "RCKE=0"
(6)
Software waits until the reference clock stops. (A waiting time of at least 300 ns is necessary.)
(7)
Software sets the bit for low-power sleep state. "PCUT=1"
(8)
The controller disables the oscillation buffer.
"XCKE=0(H/W)" *1)
*1) The software must not set the XCKE bit to "0".
Start of transit to (1)
the low power
state
(3)
(2) min 300ns
(5)
(4) min 300ns
(7) (8)
(6) min 300ns
XCKE(H/W)
RCKE
PLLC
SCKE
PCUT
Figure 3.6 Transition control timing to the low-power sleep state
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M66596FP/WG
3.1.8.3 Starting the internal clock supply (from the low-power sleep state to the normal operating state:
Auto clock supply function enabled)
Figure 3.7 shows a diagram of the timing at which the transition from the low-power sleep state to the normal
operating state takes place when the auto clock supply function is enabled (“ATCKM=1”). When the auto clock
supply function is enabled, the controller carries out register control, so after an interrupt is generated, the
transition to the normal operating state is completed simply by waiting for the amount of time that access is disabled.
No operation of the registers using the softwear is necessary.
In the Peripheral mode when operation has been resumed from the suspended state using the USB Bus Reset
signal, it is necessary to recover to the normal operating state within 3 ms after the data line change has been
detected so that the controller can begin the reset handshake protocol. When the auto clock supply function is
enabled, the controller waits automatically for oscillation to stabilize and then carries out clock supply control and
handles the reset handshake. Because there is a signal output time of 10 ms for the USB Bus Reset signal and of 20
ms for the Resume signal, the control program is provided with plenty of allowance to process the recovery to the
normal state.
The recovery sequence when the auto clock supply function is enabled is as shown below.
(1)
(2)
(3)
(4)
(5)
*1)
An interrupt is generated to recover from the low-power sleep state, and the INT_N pin is asserted.
(Or, the control program writes dummy data to the 0x7E address to cause the controller to recover.)
At the same time, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
The softwear directs the system to wait until access is enabled. (A waiting time of at least 2.5 ms is
necessary.)
The controller automatically enables RCKE, PLLC, and SCKE.
The softwear resets the registers that have been in the held state before going into the low-power sleep state.
*1)
In the Peripheral mode when the system has recovered from the low-power sleep state to the normal operating
state, the USB communication speed and the device state recovery settings have to be set in the STSRECOV bit
of the RECOVER register, and the USB address in the USBADDR bit of that register, for recovery to take place.
If the auto clock supply function has been enabled, however, the recovery settings for the above bits should be
entered after the DVSQ bit has been confirmed. This is because, if recovery has been made using the USB Bus
Reset signal, there is a possibility that the controller has initialized the device state and the USB address to the
default state, in which case rewriting the register values to the waiting state will cause erroneous operation.
The recovery settings are written to the RECOVER register using the procedure outlined below.
If “DVSQ=000”, recovery is made by a method other than the USB Bus Reset signal. The USB
communication speed, device state, and USB address should be returned to the state they were in prior to
shifting to the low-power sleep state, by writing to the RECOVER register.
If “DVSQ=001”, recovery is made using the USB Bus Reset signal. The recovery settings should not be
entered by writing to the RECOVER register.
Also, in the low-power sleep state, there are registers that are initialized by the controller. When recovery has
been made to the normal operating state, the initialized registers should be reset to match the user system.
Low-power sleep
state recovery (1),(2)
(4)
(3)2.5ms (access disabled)
XCKE(H/W)
RCKE(H/W)
PLLC(H/W)
SCKE(H/W)
PCUT(H/W)
INT_N
Event
CS_N
Figure 3.7 Recovery control timing from the low-power sleep state with “ATCKM=1”
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M66596FP/WG
3.1.8.4 Stopping the internal clock supply (From a normal operating state to clock stop state)
The timing diagram of the transition from the normal operation state to the clock stop state of the controller is
shown in Figure 3.8. The transitions should be operated according to the following sequence.
(1) Software disables the internal clock suppliance.
"SCKE=0"
(2) Software waits until an internal clock stops.
(A waiting time of at least 300 ns is necessary.)
(3) Software disables the PLL.
"PLLC=0"
(4) Software waits for the PLL to stop.
(A waiting time of at least 300 ns is necessary.)
(5) Software disables reference clock suppliance.
"RCKE=0"
(6) Software waits until the reference clock stops. (A waiting time of at least 300 ns is necessary.)
(7) Software disables the oscillation buffer.
"XCKE=0"
Start of transit to (1)
the clock stop
(3)
(2) min 300ns
(5)
(4) min 300ns
(7)
(6) min 300ns
XCKE
RCKE
PLLC
SCKE
Figure 3.8 Transition control timing to the clock stop state
3.1.8.5 Starting the internal clock supply (From the clock stop state to the normal operating state: with
"ATCKM=1")
The timing diagram from the clock stop state to the normal operation state is shown in Figure 3.9. The timing
diagram is in the case of the auto clock supply function is enabled ("ATCKM=1"; recommended setting).
In this case, the controller operates registers when resume signal is detected. The controller changes to the normal
operation state by waiting for access prohibition time after resume interruption is generated. The register operation
by software is not required. If VBUS interrupt is occurs, the softwear need to enable the oscillation buffer
(1) The controller detects the resume signal or VBUS changes on a USB bus, and the INT_N pin is asserted.
(2) When resume signal is received, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
When VBUS change occurs, the softwear needs to enable the oscillation buffer. "XCKE=1.
(3) The softwear waits until access is enabled. (A waiting time of at least 2.5 ms is necessary.)
(4) The controller automatically enables RCKE, PLLC, and SCKE during (3).
(5) Software performs resume processing depending on the interrupt factor, resume or attachment.
Clock stop
(4)
(5)
(1),(2)
recovery
XCKE
(3) 2.5ms (access disabled)
Resume :H/W
VBUS chage :S/W
RCKE(H/W)
PLLC(H/W)
SCKE(H/W)
INT_N
Event
CS_N
Figure 3.9 Recovery control timing from the clock stop state with “ATCKM=1”
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M66596FP/WG
3.1.8.6 Starting the internal clock
(From the clock stop state to the normal operating state : with “ATCKM=0”)
The timing diagram from the clock stop state to the normal operation is shown in Figure 3.10. The diagram is in
the case of the auto clock supply function is disabled ("ATCKM=0"). When the auto clock supply function is disabled,
register control is performed by software. Softwear should operate registers according to the following sequence.
(1) The controller detects the resume on a USB bus or attachment of the USB cable, and the INT_N pin is
asserted.
(2) When the resume is detected, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
When attachment of USB cable is detected, software enables the oscillation buffer. "XCKE=1(S/W)"
(3) The software waits for oscillation to stabilize. *1)
(The oscillation stabilization time varies depending
on the oscillator.)
(4) The software enables the reference clock suppliance
"RCKE=1", "PLLC=1"
and the PLL operation
(5) The software waits for the PLL to lock.
(A waiting time of at least 8.3 us is necessary.)
(6) The software enables the internal clock suppliance.
"SCKE=1"
(7) Software performs depending on the interrupt factor, resume or attachment.
*1) When it returns with a USB bus reset signal from the suspend state, it is necessary to return to the normal
operation state less than 3ms and the controller start a reset handshake protocol. For this reason, when an
auto clock supply function is disabled, it is necessary to perform a processings to oscillation stability waiting
and clock supply by software within 3ms.
Clock stop
recovery
(4)
(1),(2)
(3)
XCKE
Resume :H/W
VBUS chage :S/W
(6)
(5) min 8.3us
RCKE(H/W)
PLLC(H/W)
SCKE(H/W)
INT_N
Event
Figure 3.10 Recovery control timing from the clock stop state with “ATCKM=0”
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3.2 Interrupt functions
3.2.1
An overview of interrupt functions
Table 3.7 shows the interrupt functions of the controller.
Table 3.7 Interrupt functions
Bit
Interrupt name
VBINT
VBUS interrupt
RESM
Resume interrupt
SOFR
Frame No.
Refresh interrupt
Cause of interrupt
When a change in the state of the VBUS input pin has
been detected (change in both edge, ”L”→”H”, ”H” →”L”)
When a change in the state of the USB bus has been
detected in the suspended state
(J-State→K-State or J-State→SE0)
<Host mode>
When an SOF packet with a different frame number
has been transmited
<Peripheral mode>
When “SOFRM=0” :
When an SOF packet with a different frame number
When “SOFRM=1” :
DVST
Device State
Transition interrupt
CTRT
Control Transfer
Stage Transition
interrupt
BEMP
Buffer Empty
interrupt
NRDY
Buffer Not Ready
interrupt
BRDY
Buffer Ready
interrupt
USB bus change
interrupt
BCHG
SACK
SIGN
rev.1.00
Setup Transaction
complete
Setup Transaction
Error detect
2006.3.14
When the controller detects a corruption of an SOF
packet
When a device state transition has been detected
USB bus reset detected
Suspend state detected
Set Address request received
Set Configuration request received
When a stage transition has been detected in a control
transmission
Setup stage completed
Control write transfer status stage transition
Control read transfer status stage transition
Control transfer completed
Control transfer sequence error occurred
When transmission of all of the data in the buffer
memory has been completed
When an excessive maximum packet size error has
been detected
<Host Mode>
When a STALL token received from a peripheral.
When the response from abc is unreceivable(Pachet
ignore).
<Peripheral mode>
When an IN token has been received and there is no
data that can be sent to the buffer memory
When an OUT token has been received and there is
no area in which data can be stored in the buffer
memory, so reception is not possible
When a CRC error or bit stuffing error occurred in
isochronous transfer
When the buffer is ready (reading or writing is enabled)
When a USB bus state changes. Please do not enable
interruption during communication (at the time of
"UACT=1" setup). The bus change interruption is
generated whichever it has chosen of Host and
Peripheral mode.
When the ACK packet from peripheral device is received
at the time of sending setup transaction at Host mode.
When the ACK packet from peripheral device is not
received at the time of sending setup transaction at Host
mode.
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Related
status
VBSTS
3.2.9
-
3.2.10
Host,
Peripheral
-
3.2.8
Peripheral
DVSQ
3.2.6
Peripheral
CTSQ
3.2.7
Host,
Peripheral
PIPEBE
MP
3.2.5
Host,
Peripheral
PIPEN
RDY
3.2.4
Host,
Peripheral
Host,
Peripheral
PIPEB
RDY
-
3.2.3
3.2.11
Host
-
3.2.13
Host
-
3.2.14
Mode
Host,
Peripheral
Peripheral
Note
M66596FP/WG
DTCH
Full-Speed detach
detect
When Host mode, interruption can be generated when
peripheral device is detached at the time of Full-Speed
mode. Please perform detach detection by S/W, such as
detecting ignore packet from peripheral device at the
time of Hi-Speed mode.
Host
-
3.2.12
Table 3.8 shows the INT_N pin operations of the controller. If multiple interrupt causes have occurred, the method
used for INT_N pin output can be set using the INTL bit of the INTENB1 register. The operation setting for the
INT_N pin should be set to match the user system.
Table 3.8 INT_N pin operations
INT_N pin
operation
INTL setting
Edge sensing
(“INTL=0”)
Level sensing
(“INTL=1”)
When one interrupt cause occurred
“L” level output until the cause has been
eliminated
“L” level output until the cause has been
eliminated
When multiple interrupt causes occurred
When one cause is eliminated, the 32 clock tim
e is negated (“H” pulse output) at 48 MHz.
“L” level is output until all of the causes have
been eliminated.
<Edge sensing>
Cause 1 occurs
Cause 2 occurs
Cause 1 cleared
Cause 2 cleared
Interrupt cause 1
Interrupt cause 2
INT_N pin
Negated interval
<Level sensing>
Cause 1 occurs
Cause 2 occurs
Cause 1 cleared
Interrupt cause 1
Interrupt cause 2
INT_N pin
Figure 3.11 INT_N pin operation
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Cause 2 cleared
M66596FP/WG
Figure 3.12 shows a diagram relating to controller interrupts.
INTENB0
URST
INTENB0
USB reset detected
INTSTS0
SADR
VBSE
INT_N
Set_Address detected
VBINT
Edge /
Level
Generation
Circuit
SCFG
RSME
Set_Configuration detected
RESM
SUSP
SOFE
Suspended state detected
SOFR
WDST
Control Write
Data Stage
RDST
Control Read
Data Stage
CMPL
Control Transfer
End
SERR
NRDY
Control Transfer
Error
BRDY
Control Transfer
Setup Receive
DVSE
DVST
CTRE
CTRT
BEMPE
BEMP
NRDYE
BRDYE
BEMPENB
b7
… b1 b0
BCHGE
BCHE
BEMPSTS
DTCHE
DTCH
SIGNE
b7
.
.
.
.
.
SIGN
b1
SACKE
b0
SACK
INTENB1
INTSTS1
NRDYENB
b7 …
b1 b0
NRDYSTS
b7
.
.
.
.
.
b1
b0
BRDYENB
b7 …
b1 b0
BRDYSTS
b7
.
.
.
.
.
b1
b0
Figure 3.12 Items relating to interrupts
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3.2.2
Operation and notes in a clock stop state
VBINT, RESM, and BCHG generate a interrupt status in the clock stop(include low-power sleep state) . When
clearing the interrupt status VBINT, RESM, and BCHG in the clock stop state, it is necessary to write "0" in the bit of
an interrupt status register, then to write in "1" further.
3.2.3
BRDY interrupt
The BRDY interruption is generated whichever it has chosen of Host and Peripheral mode.
Table 3.9 shows the conditions under which the controller sets “1” to a pertinent bit of the BRDYSTS register.
Under above condition, the controller generats BRDY interrupt, if software enables PIPERDYE bit of the BRDYENB
register and BRDYE bit of the INTENB0 register. Figure 3.13 shows the timing at which BRDY interrupts are
generated..
The conditions for elimination the BRDY bit of the INTSTS0 register are depend on the setting of the BRDYM bit of
the INTENB1 register. Table 3.10 shows the conditions.
Under the conditions noted below in the Peripheral mode, a Zero-Length packet is sent for an IN token, and the
BRDY interrupt is not generated.
- When “0x000” is set in the MXPS bit of the PIPEMAXP register for a pipe, and the transfer type of the pertinent
pipe is bulk IN.
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Table 3.9 Conditions under which a BRDY interrupt is generated
Access
direction
Reading
Transfer
direction
Receive
Pipe
BFRE
DBLB
Conditions under which a BRDY interrupt is generated
DCP
-
-
1-7
0
0
(1) or (2) bellow;
(1) Short packet reception including , Zero-Length packet reception
(2) Buffer is full by reception
(1) (2) or (3) bellow;
(1) Short packet reception including , Zero-Length packet reception
(2) Buffer is full by reception *1)
(3) Transaction Counter End when buffer is not full
(1), (2), (3) or (4) bellow
(1) One of (a) to (c) conditions is occur when both buffers are waiting
for receiption
1
(a) a short packet reception including a Zero-Length packet reception
(b) One buffer of two is full by reception *1)
(c) Transaction Counter End when a buffer is not full
1
Writing
Transmit
Don’t
Care
DCP
1-7
0
0
1-7
0
1
(2) Reading is complete of a buffer, when both buffer are waiting for
reading
(3) Software set “BCLR=1” to clear a buffer, when both buffer are
waiting for reading
(4) Software set “TGL=1”, when SIE side buffer has a data In the
continuous transfer mode.
(1), (2) or (3) bellow
(1) Zero-Length packet reception
(2) After a short packet reception, reading data of the packet is
complete.
(3) After Transaction Counter End reading data of the last packet is
complete,.
Doesn’t take place
(1), (2), (3) or (4) bellow;
(1) Software set direction of transfer to transmitting
(2) Packet transmission is completed
(3) Software set “ACLRM=1”, when there are data waiting to
transmitted
(4) Software set “SCLR=1”, when there are data waiting to transmitte
(1), (2), (3), (4) or (5) bellow;
(1) Software set direction of transfer to transmitting
(2) Data is enabled to be transmitted, when there are no buffer
waiting to be transmitted.
(3) Data is enabled to be transmitted,, when there are no buffer
waiting to be transmitted.
(a) A buffer is full by writing
(b) Software set “BVAL=1” to enable the buffer is ready to tarnsmit
(c) DMAC asserts DEND signal to make a buffer be ready to transmit
1
Don’t
Care
(4) Software set “ACLRM=1”, when there are data waiting to
transmitted
(5) Software set “SCLR=1”, when there are data waiting to transmitte
Doesn’t take place
*1) Buffer full shows the following cases.
- In continuous mode ("CBTMD=1" setup), the data of buffer size is received.
- In not continuous mode ("CNTMD=0") , the data of the Max packet size is received.
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If a Zero-Length packet has been received, the pertinent bit of the BRDYSTS register goes to “1”, but the data of
the pertinent packet cannot be read. The buffer should be cleared (“BCLR=1”) after clearing the BRDYSTS register.
With PIPE1-PIPE7, if DMA transfer is being carried out in the reading direction, interrupts can be generated in
transfer units, by setting the BFRE bit of the PIPECFG register.
Zero-Length packet reception
Data packet reception using BFRE = 0 (Short Packet / Transaction Counter / Buffer Full)
USB bus
Token Packet
BRDY interrupt
Zero-Length Packet /
Short Data Packet /
Data Packet (Full)
(Transaction Count)
ACK Handshake
A BRDY interrupt is generated because
reading from the buffer is enabled.
Data packet reception using BFRE = 1 (Short Packet / Transaction Counter)
USB bus
Token Packet
Short Data Packet /
Data Packet
(Transaction Count)
BRDY interrupt
ACK Handshake
Buffer Read
A BRDY interrupt is generated
because the transfer has ended.
Packet transmission
USB bus
Token Packet
Data Packet
ACK Handshake
Buffer Write
BRDY interrupt
A BRDY interrupt is generated because
writing to the buffer is enabled.
Figure 3.13 Timing at which BRDY interrupts are generated
The conditions on which this controller clears the BRDY bit of INTSTS0 register change with setting values of the
BRDYM bit of INTENB1 register. BRDY bit clear conditions are shown in Table 3.10.
Table 3.10 Conditions for elimination of the BRDY bit
BRDYM
Conditions for elimination of the BRDY bit
0
When software clears all enabled bits of the BRDYSTS register, the controller clears the BRDY
bit.
1
When the controller clears all BSTS bits which corresponding to BRDY interrupt enebled pipe,
the controller clears the BRDY bit.
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3.2.4
NRDY interrupt
Chapter 3.2.4.1 ,3.2.4.2 show the conditions under which NRDY interrupts are generated. The cause of a NRDY
for the various pipes should be confirmed using the pertinent bit of the NRDYSTS register. If an interrupt has been
disabled using the NRDYE bit of the INTENB0 register, the interrupt request is set in the pertinent bit of the
NRDYSTS register. When all of the bits of the NRDYSTS register are cleared using the user system control program,
the controller clears the NRDY bit of the INTSTS0 register.
3.2.4.1 NRDY interrupt in the Host mode
The followings are the generating conditions of NRDY interruption in the Host mode..
(a) When STALL is received from a peripheral to the token which transmitted.
(b) When there is no response from a peripheral to the token which transmitted.
(c) When Isochronous transfer, the following errors occurred at the time of Iso transmission.
- Bit stuffing error
- CRC error
- Max packet size over error
- Over run error, under run error
* However, when the controller doesn’t receive ACK packet in the SETUP transaction, the controller generate
SIGN interrupt.
3.2.4.2 NRDY interrupt in the Peripheral mode
The followings are the generating conditions of NRDY interruption in the Peripheral mode..
(a) For data transmission
If an IN token has been received (data underrun) when the PID bit of the PIPExCTR register is in the
"PID=BUF" and there is no data to be sent in the buffer memory
(b) For data is reception
- If an OUT token or a PING token has been received (data overrun) when the PID bit of the PIPExCTR
control register is
in the "PID=BUF" and there is no area in the buffer memory where data can be stored
- In a bulk transfer, when the maximum packet size has not been set (“MXPS=0”) and an OUT token or
a PING token has been received
- When a CRC error, bit stuffing error, interval error has occurred during an isochronous transfer
- When a token is recived other than interval frame duaring an isochronous transfer.
Figure 3.14 shows the timing at which the controller generates NRDY interrupts.
Data transfer
USB bus
IN Token Packet
NAK Handshake
OUT Token Packet
Data Packet
PING Packet
NAK Handshake
NRDY interrupt
Data reception
USB bus
NAK Handshake
NRDY interrupt
(CRC error, etc.)
USB bus
NRDY interrupt
Figure 3.14 Timing at which NRDY interrupts are generated
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3.2.5
BEMP interrupt
The BEMP interruption is generated whichever it has chosen of Host and Peripheral mode. The (1), (2) shows the
conditions under which BEMP interrupts are generated. The cause of a BEMP for the various pipes should be
confirmed using the pertinent bit of the BEMPSTS register. If an interrupt has been disabled using the BEMPE bit of
the INTENB0 register, the interrupt request is set in the pertinent bit of the BEMPSTS register. When all of the bits
of the BEMPSTS register are cleared by softwear, the controller clears the BEMP bit of the INTSTS0 register. If a
pipe is under the conditions such as (1)(a), (1)(b), or (2) bellow, the controller sets “1” to a pertinent bit of the
BEMPSTS register. In this case, the controller generats BEMP interrupt, if software enables PIPENBEMPE bit of the
BEMPENB register and BEMPE bit of the INTENB0 register. When software clears all enabled bits of the BEMPSTS
register, the controller clears the BEMP bit.
(1)
When the sending direction (writing to the buffer memory) has been set
When all of the data stored in the buffer memory has been sent
If a double buffer is being used for the buffer memory, however, the following conditions are observed.
(a) A BEMP interrupt is generated if the buffer on one side is empty and sending of data from the buffer on the
opposite side has been completed.
(b) A BEMP interrupt is generated if data consisting of less than eight bytes is being written to the buffer on
one side and sending of data from the buffer on the opposite side has been completed.
(c) A BEMP interrupt is not generated if data consisting of eight bytes or more is being written to the buffer on
one side and sending of data from the buffer on the opposite side has been completed.
(2)
When the receiving direction (reading of the buffer memory) has been set
If the size of the data packet that was received exceeded the maximum packet size
At this point, if the other maximum packet size parameters were set to a value other than “0” ("MXPS≠0"),
the controller sets the PID bit of the pertinent pipe to “STALL”.
Figure 3.15 shows the timing at which BEMP interrupts are generated.
Peripheral device data sending
USB bus
IN Token Packet
Data Packet
ACK Handshake
OUT Token Packet
Data Packet
STALL Handshake
BEMP interrupt
Peripheral device data
USB bus
BEMP interrupt
Figure 3.15 Timing at which BEMP interrupts are generated
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3.2.6
Device state transition interrupt
Figure 3.16 shows a diagram of the controller device state transitions. In the Peripheral mode, the controller
controls device states and generates device state transition interrupts. However, recovery from the suspended state
(Resume signal detection) is detected by means of the Resume interrupt. The device state transition interrupt can be
set when interrupts are enabled or disabled individually, using the INTENB0 register. Also, the device state that
underwent a transition can be confirmed using the DVSQ bit of the INTSTS0 register.
When making a transition to the default state, the device state transition interrupt is generated after the reset
handshake protocol has been completed.
Suspended state detection
(When SUSP=”1”, DVST is set to “1”)
Powered
State
Suspended
State
(DVSQ="000")
(DVSQ="100")
Resume (RESM is set to “1”)
USB bus reset detection
(When URST=”1”, DVST is set to “1”)
Suspended state detection
(When SUSP=”1”, DVST is set to “1”)
USB bus reset detection
(When URST=”1”,
DVST is set to “1”)
Default
State
Suspended
State
(DVSQ="001")
(DVSQ="101")
Resume (RESM is set to “1”)
SetAddress execution
(Address=0)
(When URST=”1”,
DVST is set to “1”)
SetAddress execution
(When SADR=”1”, DVST is set to “1”)
Suspended state detection
(When SUSP=”1”, DVST is set to “1”)
Address
State
Suspended
State
(DVSQ="010")
(DVSQ="110")
Resume (RESM is set to “1”)
SetConfiguration
execution
(ConfigurationValue=0)
(When SADR=”1”, DVST
is set to “1”)
SetConfiguration execution
(ConfigurationValue?0)
(When SCFG=”1”, DVST is set to “1”)
Suspended state detection
(When SUSP=”1”, DVST is set to “1”)
Configured
State
Suspended
State
(DVSQ="011")
(DVSQ="111")
Resume (RESM is set to “1”)
Note: The URST, SADR, SCFG and SUSP bits in parentheses are the bits that are permitted when the controller
sets the DVST bit to “1” when the pertinent stage transition is generated (interrupt enable register 0
[INTENB0]). Stage transitions are carried out even if setting the DVST bit to “1” is inhibited by these bits.
Figure 3.16 Device state transitions
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3.2.7
Control transfer stage transition interrupt
Figure 3.17 shows a diagram of how the controller handles the control transfer stage transition. In the Peripheral
mode, the controller controls the control transfer sequence and generates control transfer stage transition interrupts.
Control transfer stage transition interrupts can be enabled or disabled individually, using the INTENB0 register.
Also, the transfer stage that underwent a transition can be confirmed using the CTSQ bit of the INTSTS0 register.
The control transfer sequence errors are noted below. If an error occurs, the PID bit of the DCPCTR register goes to
“1X” (STALL).
(1)
During control read transfers
(a) At the IN token of the data stage, an OUT or PING token is received when there have been no data
transfers at all
(b) An IN token is received at the status stage
(c) A packet is received at the status stage for which the data packet is "DATAPID=DATA0”
(2)
During control write transfers
(a) For the OUT token of the data stage, when there have been no ACK responses at all, the IN token is
received
(b) A packet is received at the data stage for which the first data packet is "DATAPID=DATA0"
(c) At the status stage, an OUT or PING token is received
(3)
During control write no-data transfers
(a) At the status stage, an OUT or PING token is received
At the control write transfer stage, if the number of received data elements exceeds the wLength value of the USB
request, it cannot be recognized as a control transfer sequence error. Also, at the control read transfer status stage,
packets other than Zero-Length packets are received by an ACK response being carried out, and the transfer ends
normally.
If a CTRT interrupt occurs in response to a sequence error (“SERR=1”), the “CTSQ=110” value is held until
“CTRT=0” is written from the user system (the interrupt status is cleared). Because of this, while “CTSQ=110” is
being held, the CTRT interrupt that ends the setup stage will not be generated even if a new USB request is received.
(The controller holds the setup stage end, and after the interrupt status has been cleared by software, a setup stage
end interrupt is generated.)
Setup token received
Setup token received
“CTSQ=110”
Control transfer
sequence error
5
Error detected
If errors are detected at all stages in
the box, IN token reception is valid.
Setup token
received
“CTSQ=000”
Setup stage
ACK sent
“CTSQ=001”
1 Control read data
stage
OUT token
“CTSQ=010”
ACK sent
2 Control read status
stage
4
“CTSQ=000”
Idle stage
4
ACK sent
“CTSQ=011”
1 Control write data
stage
ACK sent
IN token
“CTSQ=100”
ACK received
3 Control write status
stage
“CTSQ=101”
Control write
ACK received
1 no-data status stage
CTRT interrupts
1. Setup stage completed
2. Control read transfer status stage transition
3. Control write transfer status stage transition
4. Control transfer completed
5. Control transfer sequence error
Figure 3.17 Control transfer stage transitions
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3.2.8
Frame refresh interrupt
Figure 3.18 shows an example of the SOFR interrupt output timing of the controller.
In the Host mode, the SOFR interrupt is generated when the frame number is refreshed,
In the Peripheral mode, the SOFR interrupt is generated, when the frame number is refreshed, or a damaged SOF
packet is detected. The interrupt operation should be specified using the SOFRM bit of the FRMNUM register.
(1) When “SOFRM=0” is selected
The SOFR interrupt is generated at the timing at which the frame number is refreshed (intervals of
approximately 1 ms). Interrupts are generated by the internal interpolation function even if an SOF packet is
damaged or missing. During Hi-Speed communication as well, interrupts are generated at the timing at which
the frame number is refreshed (intervals of approximately 1 ms).
(2) When “SOFRM=1” is selected
The SOFR interrupt is generated when SOF packets are damaged and when they are missing. During Hi-Speed
communication, the interrupt is generated only if the first packet of a uSOF packet with the same frame number
is damaged or missing.
(Corrupted and missing SOFs are recognized by the SOF interpolation function. For detailed information, please
refer to Chapter 0, SOF interpolation function.)
* SOFRM bit should not be set “SFRM=1” in the Host mode.
In the Peripheral mode, if the controller detects a new SOF packet during Full-Speed operation, it refreshes the
frame number and generates an SOFR interrupt. However, if the system does not enter the µSOF lock state during
Hi-Speed operation, the frame number is not refreshed, and no SOFR interrupt is generated. Also, the SOF
interpolation function is not activated. The µSOF lock state is the state in which uSOF packets with different frame
numbers are received twice in succession without an error occurring .
The conditions under which µSOF lock monitoring begins, and under which µSOF lock monitoring stops, are as
noted below.
(1)
Conditions under which µSOF lock monitoring begins
USBE=1 and the internal clock (SCKE) is being supplied
(2)
Conditions under which µSOF lock monitoring stops
USBE=0 (S/W reset) or a USB bus reset is received, or a suspended state is detected
Peripheral Device
uSOF packet
uSOF number
6
Frame number
7
0
1
2
3
4
5
6
7
0
SOF interpolation
3
1
2
3
4
5
6
7
0
4
1
6
SOFR interrupt
(SOFRM=0)
SOF interpolation function
(SOFRM=1)
SOF missing
uSOF Lock
uSOF packet
uSOF number
7
0
1
6
SOF interpolation
7
0
7
0
1
7
0
1
2
7
SOF interpolation
uSOF lock
SOFR interrupt
Not locked
Not locked
SOF interpolation, missing
Figure 3.18 Example of SOFR interrupt output timing
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3.2.9
VBUS interrupt
The VBUS interruption is generated whichever it has chosen of Host and Peripheral mode. If there has been a
change in the VBUS pin, the VBUS interrupt is generated. The level of the VBUS pin can be detected using the
VBSTS bit of the INTSTS0 register. Confirmation can be made of whether the host controller is connected or
disconnected using the VBUS interrupt. However, if the user system is booted with the host controller connected, the
first VBUS interrupt is not generated, because there is no change in the VBUS pin.
This interruption is generated where a clock is stoped (low-power sleep state is included).
3.2.10 Resume interrupt
In the Peripheral mode, the RESM interrupt is generated if the device state is the suspended state, and the USB
bus state has changed (from the J-State to the K-State, or from the J-State to SE0). Recovery from the suspended
state is detected by means of the Resume interrupt.
In the Host mode, the RESM interrupt is not generated. Please detect change of a USB bus using BCHG
interruption.
This interruption is generated where a clock is stoped (low-power sleep state is included).
3.2.11 USB bus change interrupt
Interruption can be generated when a USB bus state changes. This interruption enable with the BCHGE bit of
INTENB1 register. This interruption is used for the peripheral connection and detection of a remote wakeup signal in
the Host mode. Please do not enable interruption during communication (at the time of "UACT=1" setup). The bus
change interruption is generated whichever it has chosen of Host and Peripheral mode.
This interruption is generated where a clock is stoped (low-power sleep state is included).
3.2.12 Full-Speed detach detect interrupt
In the Host mode, interruption can be generated when peripheral device is detached at the time of Full-Speed
mode. This interruption enable with the DTCHE bit of INTENB1 register. In the case of Hi-Speed mode, it does not
generate. In order to detect detach in Hi-Speed mode, when there is no response from peripheral, judging it as detach
etc. needs to be processed.
This interruption is not generated where a clock is stoped (low-power sleep state is included). Detection of detach
should use BCHG interruption during suspend state.
3.2.13 Setup transaction complete interrupt
Interruption can be generated when the ACK packet from peripheral device is received at the time of sending
setup transaction at Host mode. This interruption enable with the SACKE bit of INTENB1 register.
3.2.14 Setup transaction error detect interupt
Interruption can be generated when the ACK packet from peripheral device isn’t able to be received at the time of
sending setup transaction at Host mode. This interruption enable with the SIGN bit of INTENB1 register.
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3.3 Pipe control
Table 3.11 shows the pipe setting items of the controller. With USB data transfers, data communication has to be
carried out using the logic pipe called the end point. This controller has eight pipes that are used for data transfers.
Settings should be entered for each of the pipes in conjunction with the specifications of the user system.
Table 3.11 Pipe setting items
Register
name
DCPCFG
PIPECFG
Bit name
TYPE
BFRE
DBLB
CNTMD
DIR
EPNUM
SHTNAK
PIPEBUF
DCPMAXP
PIPEMAXP
PIPEPERI
DCPCTR
PIPExCTR
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Setting contents
Specifies the transfer
type
Selects the BRDY
interrupt mode
Selects a single or double
buffer
Selects continuous
transfer or
non-continuous transfer
Selects transfer direction
(reading or writing)
End point number
Selects disabled state for
pipe when transfer ends
BUFSIZE
Buffer memory size
BUFNMB
Buffer memory number
MXPS
Maximum packet size
IFIS
Buffer Flush
IITV
Interval Counter
BSTS
INBUFM
ACLRM
Buffer Status
IN Buffer Monitor
Auto Buffer Clear
SQCLR
Sequence Clear
SQSET
Sequence Set
SQMON
Sequence Confirm
PID
Response PID
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Note
Please refer to Chapter 3.3.1 Transfer types
PIPE1-5: Can be set
Please refer to Chapters 3.4.3.5 and 3.4.3.6 .
PIPE1-5: Can be set
Please refer to Chapter 3.4.1.5 .
DCP: Can be set
PIPE1-2: Can be set (can be set only when bulk transfer has
been selected)
PIPE3-5: Can be set
With continuous transmission and reception, the buffer size
should be set to an integer multiple of the payload.
Please refer to Chapter 3.4.1.6 .
IN or OUT can be set.
Please refer to Chapter 3.4.2.1 (DCP is controlled by ISEL).
Please refer to Chapter 3.3.2 End point number.
PIPE1-2: Can be set (can be set only when bulk transfer has
been selected)
PIPE3-5: Can be set
Please refer to Chapter 3.3.7 Auto NAK function.
DCP: Cannot be set (fixed at 256 bytes)
PIPE1-5: Can be set (can be specified up to a maximum of 2
KB in 64-byte units)
PIPR6-7: Cannot be set (fixed at 64 bytes)
Please refer to Chapter 3.4.1
DCP: Cannot be set (areas fixed at 0-3)
PIPE1-5: Can be set (can be specified in areas 6-4F)
PIPE6-7: Cannot be set (areas fixed at 4-5)
Please refer to Chapter 3.4.1.
Please refer to Chapter 3.3.3 Maximum packet size setting
PIPE1-2: Can be set (only when isochronous transfer has been
selected)
PIPE3-7: Cannot be set
Please refer to Chapter 3.9.5.
PIPE1-2: Can be set (only when isochronous transfer has been
selected)
PIPE3-7: Cannot be set
Please refer to Chapter 3.9.3.
Please refer to Chapter 3.4.1.1 (also related to DIR / ISEL)
Please refer to Chapter 3.4.1.1 (also related to DIR / ISEL)
Enabled / disabled setting can be set when buffer memory
reading is set.
Please refer to Chapter 3.4.1.4 .
Clears the data toggle bit.
Please refer to Chapter 3.3.6 Data PID sequence bit.
Sets the data toggle bit.
Please refer to Chapter 3.3.6 Data PID sequence bit.
Confirms the data toggle bit.
Please refer to Chapter 3.3.6 Data PID sequence bit.
Please refer to Chapter 3.3.4 Response PID.
M66596FP/WG
3.3.1 Transfer types
The TYPE bit of the PIPEPCFG register is used to specify the type of transfer for the various pipes. The types of
transfer that can be set for the pipes are noted below.
DCP: No setting is necessary (fixed at control transfer).
PIPE1-2: These should be set to bulk transfer or isochronous transfer.
PIPE3-5: These should be set to bulk transfer.
PIPE6-7: These should be set to interrupt transfer.
3.3.2 End point number
The EPNUM bit of the PIPEPCFG register is used to set the end point numbers for the various pipes. DCP is fixed
at end point 0. The other pipes can be set from end point 1 to end point 15.
DCP: No setting is necessary (fixed at end point 0).
PIPE1-7: “1” to “15” should be selected and set.
However, these should be set so that the combination of the DIR bit and the EPNUM bit is a unique combination.
3.3.3 Maximum packet size setting
The MXPS bit of the DCPMAXP register and the PIPEMAXP register is used to set the maximum packet size for
the various pipes. DCP and PIPE1-5 can be set to any of the maximum pipe sizes defined by USB specification. For
PIPE6-7, 64 bytes is the upper limit for the maximum packet size. The maximum packet size should be set before
beginning the transfer (“PID=BUF”).
DCP: “64” should be set when using Hi-Speed operation.
DCP: Select and set “8”, “16”, “32” or “64” when using Full-Speed operation.
PIPE1-5: “0” or “512” should be set when using Hi-Speed bulk transfer.
PIPE1-5: Select and set “0”, “8”, “16”, “32” or “64” when using Full-Speed bulk transfer.
PIPE1-2: Set a value between “1” and “1024” when using Hi-Speed isochronous transfer.
PIPE1-2: Set a value between “1” and “1023” when using Full-Speed isochronous transfer.
PIPE6-7: Set a value between “1” and “64”.
*The High-Bandwidth transfers used with interrupt transfers and isochronous transfers are not supported.
Also, setting “MXPS=0” for pipes when bulk transfer is being used results in the following operations in the
Peripheral mode. In the Host mode do not set "MAXP=0".
(1)
Bulk IN: Data cannot be written to the buffer memory.
When “PID=BUF” is set, a Zero-Length packet is sent in response to an IN token.
The BRDY, NRDY, and BEMP interrupts are not generated.
(2)
Bulk OUT: The data in the received data packets cannot be stored in the buffer memory.
When “PID=BUF” is set, the NAK response is sent in response to an OUT token.
In this case, NRDY interrupts are generated, but BRDY and BEMP interrupts are not.
3.3.4 Response PID
The PID bit of the DCPCTR register and PIPExCTR register is used to set the response PID for each pipe.
(1)
Host mode
(a)
Response PID specifies execution of a transaction.NAK setting : A pipe is in a prohibition state. A
transaction is not executed.
(b)
BUF setting : A transaction is executed based on the status of the buffer memory.
(c)
STALL setting : A pipe is in a prohibition state. A transaction is not executed.
* The setup transaction of DCP is executed by operation of a SUREQ bit.
(2)
Peripheral mode
Response PID specifies the response to the transaction from a host.
(a) NAK setting
: The “NAK response” is always returned in response to the generated transaction.
(b) BUF setting
: Responses are made to transactions based on the status of the buffer memory.
(c) STALL setting : The “STALL” response is always returned in response to the generated transaction.
* For setup transactions, an “ACK response” is always returned, regardless of the PID setting, and the USB
request is stored in the register.
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The controller may carry out writing to the PID bit, depending on the results of the transaction.
(1)
Host mode
(a) NAK setting
:
In the following cases, it becomes "PID=NAK" and issue of a token is stopped automatically.
- When a peripheral device ignores the token other than isochronous transfer.
- When the packet which is not normal is received during transmission other than isocronous transfer.
- When a short packet is received, if the SHTNAK bit of the PIPECFG register has been set to “1” for bulk
transfer,
- When the transaction counter has ended, if the SHTNAK bit of the PIPECFG register has been set to “1” for
bulk transfers.
(b) BUF setting
The controller doesn’t set up “PID=BUF”.
(c) STALL setting :
In the following cases, it becomes "PID=STALL" and issue of a token is stopped automatically.
- When the “STALL” packet from a peripheral device is received..
- When an error has been detected in a received data packet indicating that the data size
exceeds the maximum packet size
(2)
(a)
(b)
Peripheral mode
NAK setting
:
- When the SETUP token is received normally (DCP only)
- When a short packet is received, if the SHTNAK bit of the PIPECFG register has been set to “1” for bulk
transfers
- When the transaction counter has ended, if the SHTNAK bit of the PIPECFG register has been set to “1” for
bulk transfers
STALL setting :
- When an error has been detected in a received data packet indicating that the data size
exceeds the maximum packet size
- When a control transfer stage transition error has been detected
3.3.5 Registers that should not be set in the USB communication enabled (“PID=BUF”) state
ISEL bit of the CFIFOSEL register (applies only when DCP is selected)
TGL and SCLR bits of the CFIFOSIE register
DCLRM, TRENB, TRCLR, and DEZPM bits of the DxFIFOSEL register
TRNCNT bit of the DxFIFOTRN register
The various bits of the DCPCFG and DCPMAXP registers
The various bits of the DCPCTR register (except for the CCPL bit)
The various bits of the PIPECFG, PIPEBUF, and PIPEMAXP registers
The various bits of the PIPEPERI and PIPExCTR registers
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3.3.6 Data PID sequence bit
The controller toggles the data PID sequence bit when data is transferred normally. Next, the sequence bit of
the data PID that was sent can be used to confirm the SQMON bit of the DCPCTR register and the PIPExCTR
register. When data is sent, the sequence bit switches at the timing at which the ACK handshake is received,
and when data is received, the sequence bit switches at the timing at which the ACK handshake is sent. Also,
the SQCLR bit and the SQSET bit of the DCPCTR register and the PIPExCTR register can be used to change the
data PID sequence bit.
In control transfer of Peripheral mode, this controller sets up a sequence bit automatically at the time of stage
changes. It is set to DATA0 at the setup stage end, and it answers by DATA1 on a status stage. A set up
sequence bit by software is not required. In control transfer of Host mode, it is necessary to set up a sequence bit
by software at the stage changes.
Even when which of Host and Peripheral is chosen, after ClearFeature request etc. needs to set up a data PID
sequence bit by software.
With pipes for which isochronous transfer has been set, sequence bit operation cannot be carried out using the
SQSET bit.
3.3.7 Auto NAK function
The controller has a function that disables pipe operation (“Response PID=NAK”) at the timing at which the
final data packet of a transaction is received (the controller automatically distinguishes this based on reception
of a short packet or the transaction counter) by setting the SHTNAK bit of the PIPECFG register to “1”.
When a double buffer is being used for the buffer memory, using this function enables reception of data
packets in transfer units. Also, if pipe operation has been disabled, the pipe has to be set to the enabled state
again (“Response PID=BUF”) using software.
This function can be used for operation only when using bulk transfers.
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3.4 Buffer memory
This chapter explains operation about the buffer memory which this controller contains. When there is no
description, both a Host and Peripheral are the same operation.
3.4.1
Buffer memory allocation
Figure 3.19 shows an example of a buffer memory map for the controller. The buffer memory is an area shared by
the user system control CPU and the controller. In the buffer memory status, there are times when the access right
to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to the controller (SIE
side).
The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise one block, and
the memory areas are set using the first block number of the number of blocks (specified using the BUFNMB and
BUFSIZE bits of the PIPEBUF register). Moreover, three FIFO ports are used for access to the buffer memory
(reading and writing data). A pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE
bit of the C/DxFIFOSEL register.
The buffer statuses of the various pipes can be confirmed using the BSTS bit of the DCPCTR register and
PIPExCTR register. Also, the access right of the FIFO port can be confirmed using the FRDY bit of the C/DxFIFOCTR
register.
FIFO Port
CFIFO Port
Buffer memory
PIPEBUF reg
PIPE0
BUFNMB=0, BUFSIZE=3
PIPE6
BUFNMB=4, BUFSIZE=0
PIPE7
BUFNMB=5, BUFSIZE=0
PIPE5
BUFNMB=6, BUFSIZE=3
PIPE1
BUFNMB=10, BUFSIZE=7
PIPE2
BUFNMB=18, BUFSIZE=3
PIPE3
BUFNMB=22, BUFSIZE=7
PIPE4
BUFNMB=28, BUFSIZE=2
CURPIPE=6
D0FIFO Port
CURPIPE=1
D1FIFO Port
CURPIPE=3
Figure 3.19 Example of buffer memory map
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3.4.1.1 Buffer status
Table 3.12 shows the buffer status. The buffer memory status can be confirmed using the BSTS bit and the
INBUFM bit. The access direction for the buffer memory can be specified using either the DIR bit of the
PIPExCFG register or the ISEL bit of the CFIFOSEL register (when DCP is selected). INBUFM is valid for
transmitting direction of PIPE1-5.
For a sending direction pipe uses double buffer, software can refer the BSTS bit to monitor the buffer
memory status of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the case like
the BEMP interrupt may not show bufer empty status because the CPU (DMAC) writes data slowly, software
can use the INBUFM bit to tell the end of sending.
Table 3.12 Buffer statuses by BSTS bit and the BSTS bit
ISEL or DIR
0 (receiving
direction)
0 (receiving
direction)
BSTS
0
1 (sending
direction)
1 (sending
direction)
0
1
1
Buffer memory state
There is no received data, or data is being received. Reading from the CPU is
inhibited.
There is received data, or a Zero-Length packet has been received. Reading from
the CPU is allowed.
However, because reading is not possible when a Zero-Length packet is received,
the buffer must be cleared.
The transmission has not been finished. Writing to the CPU is inhibited.
Writing to the CPU is allowed.
(1) “DBLB=0”(Single buffer) ; The transmission has been finished.
(2) “DBLB=1”(Double buffer) ; The transmission for one side of the buffer has
been finished.
Table 3.13 Buffer statuses by INBUFM bit and the INBUFM bit
ISEL or DIR
0 (receiving
direction)
1 (sending
direction)
1 (sending
direction)
INBUF
M
Invalid
Buffer memory state
Invalid
0
The transmission has been finished. There is no transmitting data.
1
There is transmitting data.
3.4.1.2 Buffer clearing
Table 3.14 shows the clearing of the buffer memory by the controller. The buffer memory can be cleared using
the four bits indicated below.
Table 3.14 Buffer clearing
Bit name
Register
Function
Clearing
method
rev.1.00
2006.3.14
BCLR
CFIFOCTR register
DxFIFOCTR register
Clears the buffer
memory on the CPU
side
SCLR
CFIFOSIE register
DCLRM
DxFIFOSEL register
ACLRM
PIPExCTR register
Clears the buffer
memory on the SIE
side
This is the Auto Buffer
Clear mode, in which all
of the received packets
are destroyed.
See 3.4.1.4
Cleared by writing “1”
Cleared by writing “1”
In this mode, after the
data of the specified
pipe has been read,
the buffer memory is
cleared automatically.
See 3.4.3.5
“1”: Mode valid
“0”: Mode invalid
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“1”: Mode valid
“0”: Mode invalid
M66596FP/WG
3.4.1.3 Buffer areas
Table 3.15 shows the FIFO buffer memory map of the controller. The buffer memory has special fixed areas to
which pipes are assigned in advance, and user areas that can be set by the user. The buffer for the DCP is a
special fixed area that is used both for control read transfers and control write transfers. The PIPE6-7 area is
assigned in advance, but the area for pipes that are not being used can be assigned to PIPE1-5 as a user area.
The settings should ensure that the areas of the various pipes do not overlap. Also, the buffer size should not be
specified using a value that is less than the maximum packet size.
Table 3.15 Buffer memory map
Buffer memory no.
0–3
Buffer size
256 bytes
Pipe setting
DCP special fixed area
4
5
6 – 4F
64 bytes
64 bytes
4736 bytes
Fixed area for PIPE6
Fixed area for PIPE7
PIPE1-5 user area
Note
Single buffer, continuous transfers
enabled
Single buffer
Single buffer
Double buffer can be set, continuous
transfers enabled
3.4.1.4 Auto Buffer Clear mode function
With this controller, all of the received data packets are discard if the ACLRM bit of the PIPExCTR register is
set to “1”. If a normal data packet has been received, however, the ACK response is returned to the host
controller. This function can be set only in the buffer memory reading direction.
Also, if the ACLRM bit is set to “1” and then to “0”, the buffer memory of the pertinent pipe can be cleared
regardless of the access direction. An access cycle of at least 100 ns is required between “ACLRM=1” and
“ACLRM=0”.
3.4.1.5 Buffer memory specifications (single / double setting)
Either a single or double buffer can be selected for PIPE1-5, using the DBLB bit of the PIPExCFG register. The
double buffer is a function that assigns two memory areas specified with the BUFSIZE bit of the PIPEBUF
register to the same pipe. Figure 3.20 shows an example of buffer memory settings for the controller.
Buffer memory
PIPEBUF reg
64 Byte
BUFSIZE=0,
DBLB=0
64 Byte
64 Byte
BUFIZE=0,
DBLB=1
128 Byte
BUFSIZE=1,
DBLB=0
Figure 3.20 Example of buffer memory settings
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3.4.1.6 Buffer memory operation (continuous transfer setting)
Either the continuous transfer mode or the non-continuous transfer mode can be selected, using the CNTMD
bit of the DCPCFG register and the PIPExCFG register. This selection is valid for pipes 0-5.
The continuous transfer mode function is a function that sends and receives multiple transactions in succession.
When the continuous transfer mode is set, data can be transferred without interrupts being issued to the CPU,
up to the buffer sizes assigned for each of the pipes.
In the continuous sending mode, the data being written is divided into packets of the maximum packet size
and sent. If the data being sent is less than the buffer size (short packet, or the integer multiple of the maximum
packet size is less than the buffer size), “BVAL=1” must be set after the data being sent has been written.
In the continuous reception mode, interrupts are not issued during reception of packets up to the buffer size,
until the transaction counter has ended, or until a short packet is received.
Figure 3.21 shows an example of buffer memory operation for the controller.
CNTMD=0
CNTMD=1
When packet is received
When packet is received
Max Packet Size
Max Packet Size
Not used area
Interrupt issued
Max Packet Size
CNTMD=0
CNTMD=1
When packet is sent
When packet is sent
Max Packet Size
Max Packet Size
Not used area
Sending enabled
Interrupt issued
Max Packet Size
Sending enabled
Figure 3.21 Example of buffer memory operation
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3.4.2
FIFO port functions
Table 3.16 shows the settings for the FIFO port functions of the controller. When data writing is being
accessed, writing data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data. To enable sending of data before the buffer is full (or before the
maximum packet size for non-continuous transfers), the BVAL bit of the C/DxFIFOCTR register (or the DEND
signal when using DMA transfers) must be set to end the writing. Also, to send a Zero-Length packet, the BCLR
bit of the same register must be used to clear the buffer and then the BVAL bit set in order to end the writing.
When accessing reading, reception of new packets is automatically enabled if all of the data has been read.
However, data cannot be read when a Zero-Length packet is being received (DTLN=0), so the BCLR bit of the
register must be used to releasethe buffer. The length of the data being received can be confirmed using the
DTLN bit of the C/DxFIFOCTR register.
Table 3.16 FIFO port function settings
Register name
C/DxFIFOSEL
Reference
Bit name
REW
DCLRM
Function
Buffer memory rewind (re-read, re-write)
Automatically clears data received for a specified
pipe after the data has been read
3.4.4.2
3.4.1.2
3.4.3.5
DREQE
Asserts DREQ signal
3.4.3
MBW
TRENB
FIFO port access bit width
Enables transaction counter operation
3.4.2.1
3.4.2.5
TRCLR
Clears the current number of transactions
3.4.2.5
C/DxFIFOCTR
DEZPM
ISEL
BVAL
Zero-Length packet addition mode
FIFO port access direction
Ends writing to the buffer memory
DxFIFOTRN
BCLR
DTLN
TRNCNT
Clears the buffer memory on the CPU side
Confirms the length of received data
Sets the received transaction count
3.4.3.3
3.4.2.1
3.4.2.4
3.4.2
3.4.1.2
3.4.2
3.4.2.5
TGL
SCLR
CPU / SIE buffer toggle
Clears the buffer memory on the SIE side
3.4.2.3
3.4.2.4
DEND
Ends writing to the buffer memory
3.4.3.4
CFIFOSIE
(excluding
DCP)
External pin
Note
For DxFIFO
only
DMA transfer
assumed
For DxFIFO
only
For DxFIFO
only
For DxFIFO
only
For DMA only
For DCP only
For DxFIFO
only
For CFIFO only
For CFIFO only
For DMA
transfer only
3.4.2.1 FIFO port selection
Table 3.17 shows the pipes that can be selected with the various FIFO ports. The pipe to be accessed is
selected using the CURPIPE bit of the C/DxFIFOSEL register. After the pipe has been selected, “FRDY=1” should
be confirmed before accessing the FIFO port.
Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction
conforms to the DIR bit of the PIPExCFG register. However, the ISEL bit determines this only for the DCP.
Table 3.17 FIFO port access categorized by pipe
Pipe
DCP
PIPE1~PIPE7
Access method
CPU access
CPU access
DMA access
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Port that can be used
CFIFO port register
CFIFO port register
DxFIFO port register
DxFIFO port register
M66596FP/WG
3.4.2.2 REW bit
It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then
continue processing using the current pipe once again. The REW bit of the C/DxFIFOSEL register is used for
this.
If a pipe is selected when the REW bit is set to “1” and at the same time the CURPIPE bit of the C/DxFIFOSEL
register is set, the pointer used for reading from and writing to the buffer memory is reset, and reading or
writing can be carried out from the first byte. Also, if a pipe is selected with “0” set for the REW bit, data can be
read and written in continuation of the previous selection, without the pointer used for reading from and writing
to the buffer memory being reset.
To access the FIFO port, “FRDY=1” must be confirmed after selecting a pipe.
3.4.2.3 Reading the buffer memory on the SIE side (CFIFO port reading direction)
Even in the “FRDY=0” state, when data cannot be read from the buffer memory, confirming the SBUSY bit in
the CFIFOSIE register and setting “1” for the TGL bit makes it possible for the controller to read and access data
on the SIE side. “PID=NAK” should be set and “SBUSY=0” confirmed, and then “TGL=1” written. The controller
is then able to read data from the CFIFO register. This function can be used only in the buffer memory reading
direction. Also, the BRDY interrupt is generated by operation of the TGL bit.
“1” should not be written for the TGL bit in the following circumstances.
When DCP is selected
While the buffer memory is being read
Pipes in the buffer memory writing direction
3.4.2.4 Clearing the buffer memory on the SIE side (CFIFO port writing direction)
The controller can cancel data that is waiting to be sent, by confirming the SBUSY bit of the CFIFOSIE
register and setting “1” for the SCLR bit.
“PID=NAK” should be set and “SBUSY=0” confirmed, and then “SCLR=1” written. The controller is then able
to write new data from the CFIFO register. This function can be used only in the buffer memory writing direction.
Also, the BRDY interrupt is generated by operation of the SCLR bit.
“1” should not be written for the SCLR bit in the following circumstances.
When DCP is selected
While data is being written to the buffer memory
Pipes in the buffer memory reading direction
3.4.2.5 Transaction counter (DxFIFO port reading direction)
When the specified number of transactions have been completed in the data packet receiving direction, the
controller is able to recognize that the transfer has ended. The transaction counter is a function that operates
when the pipe selected by means of the DxFIFO port has been set in the direction of reading data from the buffer
memory. The transaction counter has a TRNCNT register that specifies the number of transactions and a
current counter that counts the transactions internally. When the current counter matches the number of
transactions specified in the TRNCNT register, reading is enabled for the buffer memory. The current counter of
the transaction counter function is initialized by the TRCLR bit, so that the transactions can be counted again
starting from the beginning. The information read by the TRNCNT register differs depending on the setting of
the TRENB bit.
TRENB=0: The set transaction counter value can be read.
TRENB=1: The value of the current counter that counts the transactions internally can be read.
a)
b)
a)
b)
rev.1.00
The conditions for changing the CURPIPE bit are as noted below.
The CURPIPE bit should not be changed until the transaction for the specified pipe has ended.
The CURPIPE bit cannot be changed if the current counter has not been cleared.
The operation conditions for the TRCLR bit are as noted below.
If the transactions are being counted and “PID=BUF”, the current counter cannot be cleared.
If there is any data left in the buffer, the current counter cannot be cleared.
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3.4.3 DMA transfers (DxFIFO port)
3.4.3.1 An overview of DMA transfers
For pipes 1 to 7, the FIFO port can be accessed using the DMAC.
For DMA transfers, there are two modes that can be selected. One is the cycle steal transfer mode, in which the
DREQ signal is asserted each time a data element (8 or 16 bits) is transferred. The other is the burst transfer mode,
in which the DREQ signal continues to be asserted until all of the data in the buffer memory has been transferred.
For information regarding the timing, please refer to Chapter 4, Electrical characteristics.
The unit of transfer to the FIFO port (8 or 16 bits) should be selected using the MBW bit of the DxFIFOSEL register,
and the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected pipe should not
be changed during the DMA transfer.
3.4.3.2 Selecting the DMA control signal
The DFORM bit of the DMAxCFG register should be used to select the pin to be used in the DMA transfer.
Table 3.18 shows the DMA control pins of the controller. Figure 3.22 shows the DMA control signal.
Table 3.18 DMA control pins
Register
Pin
Access
method
ADDR
Note
+CS
DREQE
DFORM
DATA BUS DREQ DACK RD/WR
DSTB
CP bus 0
0
0
0
0
CPU
v
v
CPU access
CPU bus 1
1
0
0
0
CPU
v
v
v
DMA with CPU bus
CPU bus 2
1
0
1
0
CPU
v
v
v
*2)
DMA with CPU bus
CPU bus 3
1
0
1
1
CPU
v
v
*2)
DMA with CPU bus
SPLIT bus 1
1
1
1
0
SPLIT
v
v
v
Split bus *1)
SPLIT bus 2
1
1
0
0
SPLIT
v
v
Split bus
*1) This access method can be set only in relation to the D0FIFO port. Also, if using the D0FIFO port with this
setting and also using the D1FIFO port, the D1FIFO port should be used with the setting “DFROM=000”.
*2) When this access method is set CS_N pin shoul be held inactive (should be held in the high state) while the
DMAC accsesses to the DxFIFO port.
DMA transfer on CPU bus 1
DMA transfer on CPU bus 2
DREQ
DACK
RD/WR
CS
ADDR
D15-0
DEND
DMA transfer on split bus 1
DMA transfer on split bus 2
DREQ
DACK
DSTB
SD7-0
DEND
Figure 3.22 DMA control pins operation by FIFO port accessing methods
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3.4.3.3 Zero-Length packet addition mode (DxFIFO port writing direction)
With this controller, it is possible to add and send one Zero-Length packet after all of the data has been sent,
under the conditions noted below, by setting “1” for the DEZPM bit of the DxFIFOSEL register. This function can
be set only if the buffer memory writing direction has been set (a pipe in the sending direction has been set for
the CURPIPE bit).
If the number of data bytes written to the buffer memory is a multiple of the integer for the maximum packet
size when the DEND signal is received
3.4.3.4 DEND pin
The controller is able to terminate DMA transfers that used the DEND pin. The DEND pin has separate input
and output functions, depending on the USB data transfer direction.
(1) Buffer memory reading direction
The DEND pin becomes an output pin, making it possible to notify the external DMA controller of the final
data transfer. The conditions under which the DEND signal is asserted can be set using the PKTM bit of
DMAxCFG register.
Table 3.19 shows the DEND pin assertion conditions for the controller.
Table 3.19 DEND pin assertions
Event
Transaction
count ended
BRDY
Reception of short
Reception of
Reception of
generated upon packet other than
Zero-Length
Zero-Length packet
reception of
Zero-Length packet packet when buffer when buffer is
PKTM
packet
is not empty
empty *1
0
Asserted
Not asserted
Asserted
Asserted
Asserted
1
Asserted
Asserted
Asserted
Asserted
Not asserted
*1) With reception of a Zero-Length packet when the buffer is empty, the DREQ signal is not asserted.
(2) Buffer memory writing direction
The DEND pin becomes the input pin, and data can be sent from the buffer memory (the same situation as
when “BVAL=1” is set).
3.4.3.5 DxFIFO auto clear mode (DxFIFO port reading direction)
If “1” is set for the DCLRM bit of the DxFIFOSEL register, the controller automatically clears the buffer
memory of the pertinent pipe when reading of the data from the buffer memory has been completed.
Table 3.20 shows the packet reception and buffer memory clearing processing for each of the various settings.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a situation occurs
that necessitates clearing of the buffer. This makes it possible to carry out DMA transfers without involving the
control program. This function can be set only in the buffer memory reading direction.
Table 3.20 Packet reception and buffer memory clearing processing
Register setting
Buffer status when packet is received
Buffer full
Zero-Length packet reception
Normal short packet reception
Transaction count ended
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DCLRM = “0”
BFRE=0
BFRE=1
Doesn’t need to Doesn’t need to
be cleared
be cleared
Needs to be
Needs to be
cleared
cleared
Doesn’t need to Needs to be
be cleared
cleared
Doesn’t need to Needs to be
cleared
be cleared
DCLRM = “1”
BFRE=0
BFRE=1
Doesn’t need to Doesn’t need to
be cleared
be cleared
Doesn’t need to Doesn’t need to
be cleared
be cleared
Doesn’t need to Doesn’t need to
be cleared
be cleared
Doesn’t need to Doesn’t need to
be cleared
be cleared
M66596FP/WG
3.4.3.6 BRDY interrupt timing selection function
By setting the BFRE bit of the PIPECFG register, it is possible to keep the BRDY interrupt from being
generated when a data packet consisting of the maximum packet size is received.
When using DMA transfers, this function can be used to generate an interrupt only when the last data item
has been received. The “last data item” refers to the reception of a short packet, or the ending of the transaction
counter. When a short packet has been received, the BRDY interrupt is generated after the received data has
been read. When the BRDY interrupt is generated, the length of the data received in the last data packet to have
been received can be confirmed.
Table 3.21 shows the timing at which the BRDY interrupts are generated by the controller.
Table 3.21Timing at which BRDY interrupts are generated
Register setting
BFRE = “0”
BFRE = “1”
When packet is
Buffer full
Not generated
received
When packet is
Zero-Length packet received
When packet is received
received
When packet is
When reading of the received data from
Normal packet received
received
the buffer memory has been completed
When packet is
When reading of the received data from
Transaction counter ended
received
the buffer memory has been completed
This function is valid only in the direction of reading from the buffer memory. In the writing direction, the BFRE bit
should be fixed at “0”.
Buffer state when packet is received
3.4.4
Timing at which the FIFO port can be accessed
This chapter explains the access timing to FIFO port. When there is no description, both a Host and Peripheral are
the same operation.
3.4.4.1 Timing at which the FIFO port can be accessed when switching pipes
Figure 3.23 shows a diagram of the timing up to the point where the FRDY bit and DTLN bit are determined when
the pipe specified by the FIFO port has been switched (the CURPIPE bit of the C/DxFIFOSEL register has been
changed).
If the CURPIPE bit has been changed, access to the FIFO port should be carried out after waiting 450 ns after
writing to the C/DxFIFOSEL register.
The same timing applies with respect to the CFIFO port, when the ISEL bit is changed.
Writing of the CURPIPE bit
WR N
CURPIPE
PIPE-A
FRDY
PIPE-A
DTLN
PIPE-A
PIPE-B
PIPE-B
Indefinite
Indefinite
max 100ns
PIPE-B
max 450ns
min 20ns
Figure 3.23 Timing at which the FRDY and DTLN bits are determined after changing a pipe
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3.4.4.2 Timing at which the FIFO port can be accessed after reading/writing has been completed when
using a double buffer
Figure 3.24 shows the timing at which, when using a pipe with a double buffer, the other buffer can be accessed after
reading from or writing to one buffer has been completed.
When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns after the access made
just prior to toggling.
The same timing applies when a short packet is being sent based on the “BVAL=1” setting using the IN direction
pipe.
Access just prior to buffer toggling
WR_N /
RD_N
PIPE-A
CURPIPE
FRDY
Buffer-A
DTLN
Buffer-A
Buffer-B
Indefinite
Buffer-B
max 300ns
min 20ns
Figure 3.24. Timing at which the FRDY and DTLN bits are determined after reading from or writing to a
double buffer has been completed
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3.5 Data setup timing
This section describes the OBUS bit used to select the timing of split bus.. When there is no description, both a
Host and Peripheral are the same operation.
With this controller, the timing of the SD0-7 and DEND pin can be changed as shown in Table 3.22, using the OBUS bit
of the DMAxCFG register The OBUS bit is a function that is valid only for DMA transfers using a split bus. When
using the CPU bus for DMA transfers, the setting of the OBUS bit is ignored.
Table 3.22 Differences in operation based on the value set for the OBUS bit
Direction
Reading
OBUS
bit setting
0
Operation
The SD0-7 and DEND signals are output on an ongoing basis, regardless of the control
signal *1)
The next data is output when the control signal is negated.
This assures data setup time for the DMAC and enables high-performance DMA transfers.
1
The SD0-7 and DEND signals are output after the control signal has been asserted.
The SD0-7 and DEND signals go to the Hi-Z state when the control signal is negated.
Writing
0
The SD0-7 and DEND signals can be input on an ongoing basis, regardless of the DACKx_N
signal.
The DMAC can output the next data before the DACKx_N signal is asserted.
This assures data setup time for the controller and enables high-performance DMA transfers.
1
The SD0-7 and DEND signals can be input only if the DACKx_N signal is asserted.
The SD0-7 and DEND signals are ignored if the DACKx_N signal is negated.
*1) “Control signal” refers to the DACKx_N signal if the DFORM[9-7] of the DMAxCFG register is “100”.
If the DFORM[9-7] is ”110”, it refers to both DACK0_N and DSTRB0_N. In this case, “assertion of the control
signal” means the state in which either DACK0_N or DSTRB0_N is asserted.
If “OBUS=0” is set in the reading direction, the SD0-7 and DEND signals are output on an ongoing basis, so please
be aware that sharing the bus with another device can cause the signals to collide.
If “OBUS=0” is set in the writing direction, the SD0-7 and DEND signals can be input on an ongoing basis, so the
user should make sure that the signals are not set to an intermediate potential.
Figure 3.25 shows a schematic diagram of the data setup timing based on the OBUS bit.
OBUS=1: Normal mode
OBUS=0: High-speed mode
DREQ
DACK
SD7-0
DEND
Figure 3.25 Schematic diagram of data setup timing
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3.6 Control transfers (DCP)
Data transfers of the data stage of control transfers are done using the default control pipe (DCP). The DCP buffer
memory is a 256-byte single buffer, and is a fixed area that is shared for both control reading and control writing.
The buffer memory can be accessed through the CFIFO port.
3.6.1 Host mode
3.6.1.1 Setup stage
S/W writes the data of an setup packet in USBREG register, USBVAL register, USBINDX register, and USBLENG
register. The controller transmits an setup packet by writing 1 in the SUREQ bit of DCPCTR register. After a
transaction ends the "SUREQ" bit, a controller writes in "0". During "SUREQ =1" does not operate the USB request
registers. The device address of a setup transaction is specified in the DEVSEL bit of a DCPMAXP register.
If the response from peripheral is received, the controller generates interrupt request (the SIGN bit or SACK bit of
INTSTS1 register). S/W can check a setup transaction result by these interrupt request.
The data packet of a setup transaction is always transmitted as DATA0.
3.6.1.2 Data stage
Communication of a data stage uses a DCP buffer memory. S/W sets up the access direction in the ISEL bit of a
CFIFOSEL register. Moreover, set up the transmission direction in the DIR bit of a DCPCFG register.
The 1st data packet of a data stage needs to communicate considering Data PID as DATA1. Data PID is set to
DATA1 by the SQSET bit of a DCPCFG register, and a transaction is performed by setting a PID bit as BUF. S/W
detects completion of data transmission by BRDY interruption and BEMP interruption. Data transmission of two or
more packets is possible by setting up continuous transfer mode. However, in the case of the receiving direction,
unless it becomes buffer full or receives a short packet, BRDY interruption does not occur.
Moreover, in control write transmission, control the last packet to become a short packet containing a Zero-Length
packet by S/W.
In the case of the data transmitting direction at the time of Hi-Speed communication, a PING packet is
transmitted. Control of a PING packet is the same as that of a bulk transfer. Please refer to Chapter 3.7.1.
3.6.1.3 Status stage
A status stage is data transmission of the Zero-Length packet. The communication direction is opposite to a data
stage. It is the data transmission which used the DCP buffer memory. A transaction is performed in the same
procedure as a data stage.
The 1st data packet of a status stage needs to communicate considering Data PID as DATA1. Data PID is set to
DATA1 by the SQSET bit of a DCPCFG register.
Reception of a Zero-Length packet should check receiving data length in the DTLN bit of the CFIFOCTR register
after BRDY interruption generating, and should perform a buffer memory clearance in a BCLR bit.
In the case of the data transmitting direction at the time of Hi-Speed communication, a PING packet is
transmitted. Control of a PING packet is the same as that of a bulk transfer. Please refer to Chapter 3.7.1.
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3.6.2 Peripheral mode
3.6.2.1 Setup stage
The controller always sends an ACK response in response to a setup packet that is normal with respect to the
controller. The operation of the contoller in the setup stage is noted below.
(1)
(2)
(3)
(4)
(5)
When a new USB request is received, the controller set following registers:
Set the VALID bit of the INTSTS0 register to “1”.
Set the PID bit of the DCPCTR register to “NAK”.
Set the CCPL bit of the DCPCTR register to “0”.
When a data packet is received right after the SETUP packet, the USB request parameters are stored in the
USBREQ, USBVAL, USBINDX and USBLENG registers.
Response processing with respect to the controller should always be carried out after first setting “VALID=0”. In
the “VALID=1” state, “PID=BUF” cannot be set, and the data stage cannot be terminated.
Using the function of the VALID bit, the controller is able to interrupt the processing of a request currently being
processed if a new USB request is received during a control transfer, and can send a response in response to the
newest request.
Also, the controller automatically judges the direction bit (bit 8 of the bmRequestType) and the request data
length (wLength) of the USB request that was received, and then distinguishes between control read transfers,
control write transfers, and control write no-data transfers, and controls the stage transition. For a wrong sequence,
the sequence error of the control transfer stage transition interrupt is generated, and the control program is notified.
For information on the stage control of the controller, please refer to Figure 3.17, Control transfer stage transition
diagram.
3.6.2.2 Data stage
Data transfers corresponding to USB requests that have been received should be done using the DCP. Before
accessing the DCP buffer memory, the access direction should be specified using the ISEL bit of the CFIFOSEL
register.
If the data being transferred is larger than the size of the DCP buffer memory, the data transfer should be carried
out using the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers.
With control write transfers during Hi-Speed operation, the NYET handshake response is carried out based on the
state of the buffer memory. For information on the NYET handshake, please refer to Chapter 3.7.2, NYET
handshake control.
3.6.2.3 Status stage
Control transfers are terminated by setting the CCPL bit to “1” with the PID bit of the DCPCTR register set to
“PID=BUF”.
After the above settings have been entered, the controller automatically executes the status stage in accordance
with the data transfer direction determined at the setup stage. The specific procedure is as follows.
(1) For control read transfers:
The Zero-Length packet is received from the USB host, and the controller sends an ACK response.
(2)
For control write transfers and no-data control transfers:
The controller sends a Zero-Length packet and receives the ACK response from the USB host.
The Zero-Length packet is received from the USB host, and the ACK response is sent.
3.6.2.4 Control transfer auto response function
The controller automatically responds to a normal SET_ADDRESS request. If any of the following errors occur in
the SET_ADDRESS request, a response from the S/W is necessary.
≠ "0x00"
(1)
Any transfer other than a control read transfer:
bmRequestType
≠ "0x00"
(2)
If a request error occurs:
wIndex
≠ "0x00"
(3)
For any transfer other than a no-data control transfer:
wLength
> "0x7F"
(4)
If a request error occurs:
wValue
= "011(Configured)"
(5)
Control transfer of a device state error:
DVSQ
For all requests other than the SET_ADDRESS request, a response is required from the correspondingsoftware.
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3.7 Bulk transfers (PIPE1-5)
The user can select the buffer memory specifications for bulk transfers (single / double buffer setting, or continuous
/ non-continuous transfer mode setting). The maximum size that can be set for the buffer memory is 2 KB. The buffer
memory state is controlled by the controller, with a response sent automatically for a PING packet / NYET
handshake. If “MXPS=0” has been set, the interrupt specifications are different from those of the other pipes. For
detailed information, please refer to 3.3.3 Maximum packet size setting.
3.7.1
PING packet control in the Host mode
Transmission of the PING packet of the OUT direction is automatically sent out by this controller. An initial state
is in a PING packet sending-out state as shown below. An OUT packet is sent out after receiving an ACK handshake.
If NAK or NYET is received, it will return to a PING sending-out state.
Moreover, this control is the same as a data stage and a status stage of control transfer.
1. OUT Data Transmitting Setup
2. PING Packet Transmission
3. ACK Handshake Reception
4. OUT Data Packet Transmission
5. ACK Handshake Reception
6. OUT Data Packet Transmission
:
7. NAK/NYET Handshake Reception
8. PING Packet Transmission
The factors from which this controller returns to transmission of a PING packet are H/W reset, S/W reset,
NYET/NAK handshake reception, the set of a sequence toggle bit, a clearance (SQSET, SQCLR), and a buffer
clearance (ACLRM) setup.
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3.7.2
NYET handshake control in the Peripheral mode
Table 3.23 shows the NYET handshake responses of the controller. The NYET response of the controller is made in
conformance with the conditions noted below. When a short packet is received, however, the response will be an ACK
response rather than a NYET packet response. The same applies to data stages of control write transfers.
Table 3.23 NYET handshake responses
Value set for PID Buffer memory
bit
state
NAK/STALL
BUF
Token
Response
Note
SETUP
IN/OUT/PING
SETUP
ACK
NAK/STALL
ACK
RCV-BRDY*1
OUT/PING
ACK
RCV-BRDY*2
OUT
NYET
If an OUT token is received, a data packet is
received.
Notification of whether a data packet is received
or cannot be received
Notification of whether a data packet is received
or cannot be received
Notification that reception is not possible
Notification that reception is not possible
Data packet transmission
TRN-NRDY
-
RCV-BRDY*2
OUT (Short)
ACK
RCV-BRDY*2
PING
ACK
RCV-NRDY
OUT / PING
NAK
TRN-BRDY
IN
DATA0 / 1
TRN-NRDY
IN
NAK
*1) Buffer memory is state is as following;
RCV-BRDY*1: When an OUT/PING token is received, there is space in the buffer memory for two or more
packets.
RCV-BRDY*2: When an OUT token is received, there is only enough space in the buffer memory for one packet.
RCV-NRDY: When a PING token is received, there is no space in the buffer memory.
TRN-BRDY: When an IN token is received, there is data to be sent in the buffer memory.
TRN-NRDY: When an IN token is received, there is no data to be sent in the buffer memory.
3.8 Interrupt transfers(PIPE6-7)
In the Peripheral mode, the controller carries out interrupt transfers in accordance with the timing controlled by
the host controller. For interrupt transfers, PING packets are ignored (no response is sent), and the ACK, NAK and
STALL responses are carried out without an NYET handshake response being made.
In the Host mode, this controller can set up the transmitting timing of a token by interval counter. This controller
does not transmit a PING token at the time of interruption out transmission. When NYET from peripheral is
received, this controller carries out the same operation as ACK reception.
The controller does not support High-Bandwidth transfers of interrupt transfers.
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3.8.1 Interval counter in the Host mode
3.8.1.1 Overview
Set the interval of a transaction as the IITV bit of PIPEPERI at the Interrupt transfer. This controller sends out the
token of Interrupt transfer according to the IITV bit.
3.8.1.2 Initialization of a counter
The conditions on which this controller initializes an interval counter are as follows.
(1) H/W reset
IITV bit is initialized.
(2) S/W reset
IITV bit is initialized.
(3) The return from Low-power sleep state
An IITV bit is initialized.
(4) Buffer memory initialization by ACLRM
A count is initialized although an IITV bit is not initialized. By setting an ACLRM bit to 0, the setting value of
IITV is counted from the beginning.
In the following cases, an interval counter is not initialized.
(1) USB bus reset, USB suspensd
An IITV bit is not initialized. By setting a UACT bit to 1, a count is started from the value before considering
as USB bus reset or a USB suspend state.
3.8.1.3 When a token is not transmitted
When as follows, a token is not transmitted even if it is the transmitting timing of a token. In such a case,
execution of a transaction is tried at the next interval.
(1) When PID is set as NAK or STALL
(2) When a buffer memory is not empty at the time of transmission of the IN direction (reception).
(3) When there is no transmitting data in a buffer memory at the time of transmission of the OUT direction
(transmission).
3.9 Isochronous transfers(PIPE1-2)
The controller is equipped with the following functions pertaining to isochronous transfers.
(1)
Notification of isochronous transfer error information
(2)
Interval counter (specified by the IITV bit)
(3)
Isochronous IN transfer data setup control (IDLY function)
(4)
Isochronous IN transfer buffer flush function (specified by the IFIS bit)
(5)
SOF pulse output function
The controller does not support the High-Bandwidth transfers of isochronous transfers.
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3.9.1
Error detection with isochronous transfers
The controller has a function for detecting the error information noted below, so that when errors occur in
isochronous transfers, software can control them. Table 3.24 and Table 3.25 show the order in which errors are
confirmed, and the interrupts that are generated.
(1)
PID errors
If the PID is illegal
(2)
CRC errors and bit stuffing errors
If an error occurs in the CRC of the packet being received, or the bit stuffing is illegal
(3)
Maximum packet size exceeded
The maximum packet size exceeded the set value.
(4)
Overrun and underrun errors
(a) In the Host mode
- When a buffer memory is not empty at the time of transmission of the IN direction
- When there is no transmitting data in a buffer memory at the time of transmission of the OUT
direction
(b) In the Peripheral mode
- When a buffer memory is not empty at the time of the OUT token is received.
- When there is no transmitting data in a buffer memory at the time of the IN token is received.
(5)
Interval errors
In the Peripheral mode, The following cases are interval error.
- During an isochronous IN transfer, the In token could not be received during the interval frame.
- During an isochronous OUT transfer, the OUT token is received out of the interval frame.
Table 3.24 Error detection when a token is received
Detection
priority
order
1
2
Error
PID errors
CRC error and bit stuffing errors
3
Overrun and underrun errors
4
Interval errors
Generated interrupt and status
No interrupt generated (ignored)
No interrupt generated (ignored)
NRDY interrupt, OVRN bit set
In the Host mode, the controller does
not transmit a token.
In the Peripheral mode, the controller
transmits a Zero-Length to IN token.
The controller does not receive a data
packet to an OUT token.
NRDY interrupt is generated in the
Peripheral mode.
Table 3.25 Error detection when a data packet is received
Detection
priority
order
1
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Error
PID errors
2
CRC error and bit stuffing errors
3
Maximum packet size exceeded error
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Generated interrupt and status
No interrupt generated (ignored)
NRDY interrupt generated
CRCE bit set
BEMP interrupt
PID set to ”STALL”
M66596FP/WG
3.9.2
DATA-PID
Because High-Bandwidth transfers are not supported, In the Peripheral mode, the DATA-PID added with the
USB 2.0 standard is supported as indicated below.
(1) IN direction:
(a) DATA0: Sent as data packet PID
(b) DATA1: Not sent
(c) DATA2: Not sent
(d) mDATA: Not sent
(2) OUT direction(when using Full-Speed operation):
(a) DATA0: Received normally as data packet PID
(b) DATA1: Received normally as data packet PID
(c) DATA2: Packet is ignored
(d) mDATA: Packet is ignored
(3) OUT direction(when using Hi-Speed operation):
(a) DATA0: Received normally as data packet PID
(b) DATA1: Received normally as data packet PID
(c) DATA2: Received normally as data packet PID
(d) mDATA: Received normally as data packet PID
3.9.3 Interval counter
3.9.3.1 An overview of operation
The isochronous interval can be set using the IITV bit of the PIPEPERI register. In the Peripheral mode, interval
counter is used for the function of a table. In the Host mode, the transmitting timing of a token is generated.
Table 3.26 The function of an interval counter in the Peripheral mode
Direction
IN
Function
IN buffer flush
OUT
Notification of a token not being received
Detection conditions
When a token cannot be normally received in the
interval frame during an isochronous IN transfer
When a token cannot be normally received in the
interval frame during an isochronous OUT transfer
The interval count is carried out when an SOF is received or for interpolated SOFs, so the isochronism can be
maintained even if an SOF is damaged. The frame interval that can be set is 2IITV(u) frames.
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3.9.3.2 Counter initialization in the Peripheral mode
The controller initializes the interval counter under the following conditions.
(1) H/W reset
The IITV bit is initialized.
(2) S/W reset by USBE bit
The IITV bit is initialized.
(3) The return from Low-power sleep state
The IITV bit is initialized.
(4) Buffer memory initialization by the ACLRM bit.
A count is initialized although an IITV bit is not initialized. By setting an ACLRM bit to 0, the setting value of
IITV is counted from the beginning.
After the interval counter has been initialized, the counter is started under the following conditions, when a
packet has been transferred normally.
(1)
An SOF is received following transmission of data in response to an IN token, in the “PID-BUF” state
(2)
An SOF is received after data following an OUT token is received in the “PID=BUF” state
The interval counter is not initialized under the conditions noted below.
(1)
The pipe is disabled
The “PID=NAK or STALL” setting temporarily stops the count, and the count resumes upon “PID=BUF”.
(2)
The USB is suspended and Bus reset
The count stops temporarily and then continues when SOF packet is received.
rev.1.00
2006.3.14
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M66596FP/WG
3.9.4
Setup of data to be transmitted using isochronous transfer in the Peripheral mode.
With isochronous data transmission using this controller at Peripheral mode, after data has been written to the
buffer memory, a data packet can be sent with the next frame in which an SOF packet is detected. This function is
called the isochronous transfer transmission data setup function, and it makes it possible to designate the frame
from which transmission began.
If a double buffer is being used for the buffer memory, transmission will be enabled for only one of the two buffers
even after the writing of data to both buffers has been completed, that buffer memory being the one to which the
data writing was completed first. For this reason, even if multiple IN tokens are received, the only buffer memory
that can be sent is one packet’s worth of data.
When an IN token is received, if the buffer memory is in the transmission enabled state, the controller transmits
the data. If the buffer memory is not in the transmission enabled state, however, a Zero-Length packet is sent and an
underrun error occurs.
Figure 3.26 shows an example of transmission using the isochronous transfer transmission data setup function
with the controller, when “IITV=0 (every frame)” has been set. Sending of a Zero-Length packet is displayed in the
illustration as “Null”, in a shaded box.
IN
Received token
Buffer A
Empty state
Writing in
progress
IN
IN
Writing completed
Buffer B
Transmission enabled state
Empty state
Empty state
Null
Sent packet
Null
Data-A
SOF packet
Buffer A
Empty state
Writing in
progress
Empty state
Buffer B
Writing in
progress
Transmission enabled state
IN
Received token
Empty state
Buffer A
Writing in
progress
Empty state
Buffer B
Writing completed
Writing in
progress
Send packet
IN
Transmission
enabled state
Buffer B
Writing in
progress
Empty state
Writing completed
Writing in
progress
Send packet
Null
Empty state
Writing in
progress
IN
Transmission
enabled state
IN
Empty state
IN
Writing in
progress
2006.3.14
page 95 of 127
Writing completed
Transmission
enabled state
Writing completed
Data-A
Empty state
Data-B
Null
Figure 3.26 Example of data setup function operation
rev.1.00
Writing completed
Transmission
enabled state
Data-A
IN
Empty state
IN
Writing completed
Null
Received token
Buffer A
Transmission enabled state
Writing completed
Empty state
Data-B
M66596FP/WG
3.9.5
Isochronous transfer transmission buffer flush
In the Peripheral mode if a (u) SOF packet is received without an IN token having been received in the interval
frame during isochronous data transmission, the controller operates as a IN token had been corrupted, and clears
the buffer for which transmission is enabled, putting that buffer in the writing enabled state.
If a double buffer is being used at that time and writing has been finished to both buffers, the buffer memory that
was cleared is seen as the data having been sent at the same interval frame, and transmission is enabled for the
other buffer memory.
The timing at which the operation of the buffer flush function begins varies depending on the value set for the
IITV bit.
(1)
If IITV=0
The buffer flush operation starts from the next frame after the pipe becomes valid.
(2)
In any case other than IITV=0
The buffer flush operation is carried out subsequent to the first normal transaction.
Figure 3.27 shows an example of the buffer flush function of the controller. When an unanticipated token prior to
the interval frame is received, the controller sends the written data or a Zero-Length packet are sent in accordance
with buffer state.
Buffer A
Empty state
Buffer B
Writing in
progress
Empty state
Writing completed
Writing in
progress
Transmission enabled state
Empty state
Writing completed
Writing in
progress
Writing completed
Transmission enabled state
Figure 3.27 Example of buffer flush function operation
Figure 3.28 shows an example of the controller generating an interval error. There are five types of interval errors,
as noted below. The interval error is generated at the timing indicated by c in the illustration, and the buffer flush
function is activated.
If the interval error occurs during an IN transfer, the buffer flush function is activated, and if it occurs during an
OUT transfer an NRDY interrupt is generated.
The OVRN bit should be used to distinguish between NRDY interrupts such as received packet errors and overrun
errors.
In response to tokens that are shaded in the illustration, responses occur based on the buffer memory status.
(1)
(2)
IN direction
(a) If the buffer is in the transmission enabled state, the data is transferred as a normal response .
(b) If the buffer is in the transmission disabled state, a Zero-Length packet is sent and an underrun error
occurs.
OUT direction
(a) If the buffer is in the reception enabled state, the data is received as a normal response.
(b) If the buffer is in the reception disabled state, the data is decarded and an overrun error occurs.
SOF
Normal transfer
Token
Token damaged
Token
Packet inserted
Token
Frame misaligned
Token
Frame misaligned
Token
Token delayed
Token
Token
1
Token
Token
1
Token
1
Token
Token
Token
Token
Token
Token
Token
1
Token
1
Token
1
Token
1
Token
Token
Figure 3.28 Example of interval error being generated when “IITV=1”
rev.1.00
2006.3.14
page 96 of 127
Token
M66596FP/WG
3.10 SOF interpolation function
In the Peripheral mode, if data could not be received at intervals of 1 ms (when using Full-Speed operation) or 125
µs (when using Hi-Speed operation) because an SOF packet was corrupted or missing, the controller interpolates the
SOF. The SOF interpolation operation begins when “USBE=1”, “SCKE=1” and an SOF packet is received. The
interpolation function is initialized under the following conditions.
(1)
H/W reset
(2)
S/W reset
(3)
USB bus reset
(4)
Suspend state detected
Also, the SOF interpolation operates under the following specifications.
(1)
125 µs/1 ms conforms to the results of the reset handshake protocol.
(2)
The interpolation function is not activated until an SOF packet is received.
(3)
After the first SOF packet is received, either 125 µs or 1 ms is counted at an internal clock of 48 MHz, and
interpolation is carried out.
(4)
After the second and subsequent SOF packets are received, interpolation is carried out at the previous
reception interval.
(5)
Interpolation is not carried out in the suspended state or while a USB bus reset is being received.
(With suspended transitions during Hi-Speed operation, interpolation continues for 3 ms after the last
packet is received.
The contorller supports the following functions based on the SOF detection. Those functions also operate normally
with SOF interpolation is also activated for the following functions, if the SOF packet was corrupted.
(1)
Refreshing of the frame number and micro-frame number
(2)
SOFR interrupt timing and uSOF lock
(3)
SOF pulse output
(4)
Isochronous transfer interval count
If an SOF packet is missing when Full-Speed operation is being used, the FRNM bit of the FRMNUM0 register is
not refreshed. If a µSOF packet is missing during Hi-Speed operation, the UFRNM bit of the FRMNUM1 register is
refreshed.
However, if a µSOF packet for which “µFRNM=000” is missing, the FRNM bit is not refreshed. If this happens, the
FRNM bit is not refreshed even if successive µSOF packets other than “µFRNM=000” are received normally.
3.10.1 SOF pulse output
When SOF output is enabled, the controller is able to output SOF signals at the timing at which the SOFs are
received. When the value of the SOFM bit of the SOFCFG register is “01” (1 ms SOF) or “10” (125µs SOF), pulses are
output from the SOF_N pin in the “L” active state. These are called “SOF signals”. For information on pulse timing,
please see Figure 3.29 The controller outputs SOF output based on SOF packet reception events or SOF
interpolation events at uniform intervals.
1ms(Full-Speed) / 125us(High-Speed)
SOF packet
USB Bus
SYNC
PID
FRAME
CRC5
SOF
minimun 640ns
Figure 3.29 SOF output timing
rev.1.00
2006.3.14
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M66596FP/WG
3.11 Communication schedule
3.11.1 The generation conditions of a transaction
In the Host mode, This controller generates a transaction according to the following conditions after supply of an
internal clock, and a setup of "UACT=1."
Table 3.27 The generation conditions of a transaction
Transaction
Setup
The data stage of control
transmission, status
stage, bulk transfer
*1)
*2)
*3)
*4)
Generation conditions
DIR
PID
IITV*2)
IN
BUF
Status of buffer
SUREQ
Set 1
Invalid
There is a
receiving area
OUT
BUF
Invalid
There is a
sending data
Interrupt transfer
IN
BUF
Effective
There is a
receiving area
OUT
BUF
Effective
There is a
sending data
Isochronous transfer
IN
BUF
Effective
*3)
OUT
BUF
Effective
*4)
It is shown that slashes are conditions which are unrelated to generation of a token.
The Effective means being generated only with the transmission frame by the interval counter. It is shown that
the Invalid is generated regardless of an interval counter.
The controller generates a transaction regardless of a receiving area. However, receiving data is canceled when
there is no receiving area.
The controller generates a transaction regardless of a sending data. However, when there is no transmitting
data, Zero-Length Packet is transmitted.
3.11.2 Communication schedule
This chapter explains the scheduling of transmission in the frame of this controller. After transmitting SOF ,
this controller transmits packets as follows.
(1) Execution of periodic transmission
The controller executes transactions, if it searches in order of PIPE1 ->PIPE2 ->PIPE6 ->PIPE7 and there is
a pipe in which the transaction of isochronous transfer or interrupt transfer is possible.
(2) Execute setup transaction of control transfer
DCP is checked, and if the setup transaction is possible, it will transmit.
(3) Execute bulk transfer, data stage and status stage of control transfer,
The controller searches PIPEs in following order. And a transaction will be executed if there is PIPE which
can execute the transaction of bulk, a control transmission data stage, and a control transmission status
stage.
The order of search : DCP -> PIPE1 -> PIPE2 -> PIPE3 -> PIPE4 -> PIPE5
When a transaction is executed, regardless of the response from Peripheral, it moves to the next PIPE.
Moreover, (3) will be repeated if there is time to transmit in a frame.
3.11.3 USB Communication enable
By setting the UACT bit of a DVSTCTR register as "1", transmission of SOF or uSOF is started and execution
of a transaction is enabled.
If a UACT bit is set as "0", transmission of SOF or uSOF will be stopped and it will be suspended. When
setting a UACT bit as 1->0, a controller stops sending packets, after it transmits next SOF or next uSOF.
rev.1.00
2006.3.14
page 98 of 127
M66596FP/WG
4 Electrical
characteristics
4.1 Absolute maximum ratings
Symbol
VDD
VIF
AFEA33V
AFED33V
AFEA15V
AFED15V
VBUS
VI(IO)
VO(IO)
Pd
Tstg
Item
Core power supply voltage
IO power supply voltage
USB transceiver analog 3.3V power supply voltage
USB transceiver digital 3.3V power supply voltage
USB transceiver analog 1.5V power supply voltage
USB transceiver digital 1.5V power supply voltage
VBUS input voltage
System interface input voltage
System interface output voltage
Power consumption
Storage
M66596FP(LQFP)
temperature
M66596WG(FBGA)
Rated value
-0.3~+2.4
-0.3~+4.0
-0.3~+4.0
-0.3~+4.0
-0.3~+2.4
-0.3~+2.4
-0.3~+5.5
-0.3 ~VIF+0.3
-0.3~VIF+0.3
400
-55~+150
-55~+125
Unit
V
V
V
V
V
V
V
V
V
mW
°C
°C
4.2 Recommended operating conditions
AFEA33V
Core power supply voltage
IO power supply voltage
1.8V supported
3.3V supported
USB transceiver analog 3.3V power supply voltage
Min.
1.35
1.6
2.7
3.0
Rated value
Typ.
1.5
1.8
3.3
3.3
Max.
1.65
2.0
3.6
3.6
AFED33V
USB transceiver digital 3.3V power supply voltage
3.0
3.3
3.6
V
AFEA15V
USB transceiver analog 1.5V power supply voltage
1.35
1.5
1.65
V
AFED15V
USB transceiver digital 1.5V power supply voltage
1.35
1.5
1.65
V
AFEA33G
USB transceiver analog supply GND
0
V
AFED33G
USB transceiver digital supply GND
0
V
AFEA15G
USB transceiver analog supply GND
0
V
AFED15G
USB transceiver digital supply GND
0
V
Supply GND
0
V
Symbol
Item
VDD
VIF
DGND
VI(IO)
VI(VBUS)
VO(IO)
Topr
tr, tf
rev.1.00
System interface input voltage
Input voltage(VBUS input only)
System interface output voltage
Ambient operating temperature
Input rise, fall times
Normal input
Schmitt trigger input
2006.3.14
page 99 of 127
0
0
0
-20
+25
VIF
5.25
VIF
+85
500
5
Unit
V
V
V
V
V
V
V
°C
ns
ms
M66596FP/WG
4.3 Electrical characteristics(ratings for VIF = 2.7~3.6V, VDD = 1.35~1.65V)
Symbol
VIH
VIL
VIH
VIL
VT+
Item
Measurement conditions
Rdv
"H" input voltage
"L" input voltage
"H" input voltage
"L" input voltage
Threshold voltage in
positive direction
Threshold voltage in
negative direction
Hysteresis voltage
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
Threshold voltage in
positive direction
Threshold voltage in
negative direction
"H" input current
"L" input current
"H" output current in off
status
"L" output current in off
status
Pull-down resistance
Rdt
Pull-down resistance
Icc(A)
Average supply current at
HS operation
Note
5
Note
6
Note
7
Icc(A)
Average supply current at
FS operation
Note
7
Icc(S)
Supply current in static
mode
Note
7
VTVTH
VOH
VOL
VOH
VOL
VOH
VOL
VT+
VTIIH
IIL
IOZH
IOZL
CIN
COUT
COUT
Pin capacitance (input)
Pin capacitance (input /
output)
Pin capacitance (D+, D-)
Xin
Note
1
AFEA33V = 3.6V
AFEA33V = 3.0V
VIF = 3.6V
VIF = 2.7V
VIF = 3.3V
Note
2
Min.
2.52
0
0.7VIF
0
1.4
Rated value
Typ.
0.5
Max.
3.6
0.9
3.6
0.3VIF
2.4
1.65
0.8
Xout
Note
3
Note
4
Note
5
Note
4
Note
8
V
1.4
0.4
2.4
0.5
1.65
V
VI = VIF
VI = GND
VO = VIF
10
-10
10
uA
uA
uA
VO = GND
-10
uA
IOH = -50 uA
IOL = 50 uA
IOH = -2 mA
IOL = 2 mA
VIF = 2.7V
IOH = -4 mA
IOL = 4 mA
AFED33V = 3.3V
VIF = 3.6V
V
V
V
V
V
V
V
V
V
V
V
V
V
AFEA33V =
3.0V
VIF = 2.7V
VIF = 3.6V
Unit
f(Xin) = 48 MHz
VDD = 1.65V, VIF = 3.6V,
AFEA33V, AFED33V = 3.6V,
AFEA15V, AFED15V = 1.65V
f(Xin) = 48 MHz
VDD = 1.65V, VIF = 3.6V,
AFEA33V, AFED33V = 3.6V,
AFEA15V, AFED15V = 1.65V
USB suspend state
(Host mode)
VIF = 3.6V
USB suspend state
(Peripheral mode)
VIF = 3.6V
USB cable detached
VIF = 3.6V
2.6
0.4
VIF-0.4
0.4
VIF-0.4
500
kΩ
50
kΩ
40
mA
18
mA
0.07
mA
0.27
0.07
mA
7
7
pF
pF
15
pF
Note 1: A6/ALE, A5-1, TEST, MPBUS input pin, and D15-7, D6/AD6-D1/AD1, D0, SD7-0, DEND0-1_N input / output pins
Note 2: CS_N, RD_N, WR0-1_N, DACK0_N, DACK1_N/DSTB0_N, RST_N input pins
Note 3: INT_N, SOF_N, DREQ0-1_N output pins, and DEND0-1_N input / output pin
Note 4: D15-7, D6/AD6-D1/AD1, D0, SD7-SD0 input / output pins
Note 5: VBUS input pin
Note 6: TEST input pin
Note 7: Supply current is the total of the VDD, VIF, AFEA33V, AFED33V, AFEA15V, and AFED15V currents
Note 8: Except D+ and Drev.1.00
2006.3.14
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M66596FP/WG
4.4 Electrical characteristics (ratings for VIF = 1.6~2.0V, VDD = 1.35~1.65V)
Symbol
Item
Xin
VIH
VIL
VIH
VIL
"H" input voltage
"L" input voltage
"H" input voltage
"L" input voltage
VT+
IOZL
Rdv
Threshold voltage in positive
direction
Threshold voltage in negative
direction
Hysteresis voltage
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
Threshold voltage in positive
direction
Threshold voltage in negative
direction
"H" input current
"L" input current
"H" output current in off
status
"L" output current in off status
Pull-down resistance
Rdt
Pull-down resistance
Icc(A)
Average supply current at HS
operation
Note
5
Note
6
Note
7
Icc(A)
Average supply current at FS
operation
Note
7
Icc(S)
Supply current in static mode
Note
7
VTVTH
VOH
VOL
VOH
VOL
VOH
VOL
VT+
VTIIH
IIL
IOZH
Note
1
Note
2
Measurement conditions
Min.
AFEA33V = 3.6V
AFEA33V = 3.0V
VIF = 2.0V
VIF = 1.6V
VIF = 1.8V
Rated value
Stand
ard
Max.
Unit
2.52
0
0.7VIF
0
3.6
0.9
2.0
0.3VIF
V
V
V
V
0.7
1.4
V
0.2
0.8
V
0.5
Xout
Note
3
Note
4
Note
5
AFEA33V
= 3.0V
VIF = 1.6V
IOH = -50 uA
IOL = 50 uA
IOH = -2 mA
IOL = 2 mA
VIF = 1.6V
IOH = -4 mA
IOL = 4 mA
AFED33V=3.3V
VIF = 2.0V
Note
4
VIF = 2.0V
1.4
0.4
2.4
V
V
V
V
V
V
V
V
0.5
1.65
V
10
-10
10
uA
uA
uA
-10
500
uA
kΩ
50
kΩ
40
mA
18
mA
0.07
mA
2.6
0.4
VIF-0.4
0.4
VIF-0.4
VI= VIF
VI = GND
Vo = VIF
Vo = GND
CIN
COUT
f(Xin) = 48 MHz
VDD = 1.65V, VIF = 2.0V,
AFEA33V, AFED33V = 3.6V,
AFEA15V, AFED15V = 1.65V
f(Xin) = 48 MHz
VDD = 1.65V, VIF = 2.0V,
AFEA33V, AFED33V = 3.6V,
AFEA15V, AFED15V = 1.65V
USB suspend state
(Host mode)
VIF = 2.0V
USB suspend state
(Peripheral mode)
VIF = 2.0V
USB cable detached
VIF = 2.0V
0.27
0.07
mA
Pin capacitance (input)
7
pF
Pin capacitance (input /
Note
7
pF
output)
8
COUT
Pin capacitance (D+, D-)
15
pF
Note 1: A6/ALE, A5-1, TEST, MPBUS input pins, and D15-7, D6/AD6-D1/AD1, D0, SD7-0, DEND0-1_N input / output pins
Note 2: CS_N, RD_N, WR0-1_N, DACK0_N, DACK1_N/DSTB0_N, RST_N input pins
Note 3: INT_N, SOF_N, DREQ0-1_N output pin, and DEND0-1_N input / output pin
Note 4: D15-7, D6/AD6-D1/AD1, D0, SD7-SD0 input / output pins
Note 5: VBUS input pin
Note 6: TEST input pin
Note 7: Supply current is the total of the VDD, VIF, AFEA33V, AFED33V, AFEA15V, AFED15V currents.
Note 8: Except D+ and Drev.1.00
2006.3.14
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M66596FP/WG
4.5 Measurement circuit
4.5.1
Pins except for USB buffer block
VDD
item
SW1
SW2
tdis(CTRL(LZ))
closed
open
D15-0,
tdis(CTRL(HZ))
SD7-0,
ta(CTRL(ZL))
DEND0_N,
ta(CTRL(ZH))
SW2 DEND1_N
open
closed
closed
open
open
closed
VDD
input
RL=1kΩ
SW1
Elements to
be measured
P.G.
CL
(1) Input pulse level : 0 ~ 3.3V, 0 ~ 1.8V
Input pulse rise/fall time : tr,tf=3ns
Input timing standard voltage : VIF/2
Output timing judge voltage : VIF/2
other output
(The tdis (LZ) is judged by 10% of the
output amplitude and the tdis (HZ) by
90% of the output amplitude.)
RL=1kΩ
50Ω
CL
GND
4.5.2
(2)The electrostatic capacity CL includes
the stray capacitance of the wire
connection and the input capacitance
of the probe.
USB buffer block (Full-Speed)
(1) The tr and tf are judged by the transition time of
the 10% amplitude point and 90% amplitude
point respectively.
VDD
(2) The electrostatic capacity CL includes the stray
capacitance of the wire connection and the
input capacitance of the probe.
D+
DP
Elements to
be measured
RL=15KΩ
CL
(3) The resistor RL exists only
when peripheral mode.
D-
DM
RL=15KΩ
CL
GND
4.5.3
USB buffer block (Hi-Speed)
(1) The tr and tf are judged by the transition time of
the 10% amplitude point and 90% amplitude
point respectively.
VDD
D+
(2) The electrostatic capacity CL includes the stray
capacitance of the wire connection and the
input capacitance of the probe.
toDP
Elements
be m
easured
RL=45Ω
CL
RL=45Ω
CL
DDM
GND
rev.1.00
2006.3.14
page 102 of 127
M66596FP/WG
4.6 Electrical characteristics(D+/D-)
4.6.1
DC characteristics
Symbol
Item
Measurement conditions
RREF
Ro
Reference resistance
FS driver
HS operation
output impedance
FS operation
Rpu
D+ pull-up resistance
Idle status
(Peripheral mode)
Transmitting and receiving status
Rpd
D+,D- pull-down resistance
(Host mode)
Input characteristics for Full-Speed operation
VIH
“H” input voltage
VIL
“L” input voltage
VDI
Differential input sensitivity
⏐(D+)-(D-)⏐
VCM
Differential common mode
range
Output characteristics for Full-Speed operation
AFEAVDD =
VOL
"L" output voltage
RL of 1.5KΩ to
3.0V
3.6V
VOH
"H" output voltage
RL of 15KΩ to
GND
VSE
Single-ended receiver
threshold voltage
VORS
Output signal crossover
CL=50 pF
voltage
Input characteristics for Hi-Speed operation
VHSSQ
Squelch detection threshold
voltage (differential)
VHSCM
Common mode range
Output characteristics for Hi-Speed operation
VHSOI
Idle state
VHSOH
“H” output voltage
VHSOL
“L” output voltage
VCHIRPJ
Chirp J output voltage
(differential)
VCHIRPK
Chirp K output voltage
(differential)
4.6.2
Min.
5.544
40.5
28
0.9
1.425
14.25
Rated value
Typ.
Max.
5.6
5.656
45
49.5
36
44
1.575
3.09
24.80
2.0
Unit
kΩ
Ω
Ω
kΩ
kΩ
kΩ
2.5
V
V
V
V
0.3
V
2.8
3.6
V
0.8
2.0
V
1.3
2.0
V
100
150
mV
-50
500
mV
-10.0
360
-10.0
700
10
440
10
1100
mV
mV
mV
mV
-900
-500
mV
0.8
0.2
0.8
AC characteristics(Full-Speed)
Symbol
Item
Tr
Rise transition time
Tf
Fall transition time
TRFM
Rise / fall time matching
rev.1.00
2006.3.14
Measurement conditions
10% to 90% of the data signal
amplitude
90% to 10% of the data signal:
amplitude
tr/tf
page 103 of 127
Min.
Rated value
Standa
Max.
rd
20
Unit
CL=50 pF
4
ns
CL=50 pF
4
20
ns
90
111.11
%
M66596FP/WG
4.7 Switching characteristics (VIF = 2.7~3.6V, or 1.6~2.0V)
Symbol
Item
Measurement
conditions /
other
ta (A)
Address access time
CL=50 pF
tv (A)
Time that data is valid after address
CL=10 pF
Time that data can be accessed after
control
Time that data is valid after control
CL=50 pF
ta (CTRL - D)
tv (CTRL - D)
ten (CTRL - D)
tdis (CTRL - D)
ta (CTRL - DV)
tv (CTRL – DV)
ta (CTRL - DendV)
tv (CTRL - DendV)
ta (CTRL - Dend)
tv (CTRL – Dend)
Time that data output is enabled after
control
Time that data output is disabled after
control
Time that data can be accessed after
control when split bus (DMA Interface)
Obus=0
Time that data can is valid after control
when split bus (DMA Interface) Obus=0
Time that DEND output can be accessed
after control when split bus (DMA
Interface) Obus=0
Time that DEND output is valid after
control when CPU bus and split bus
(DMA Interface) Obus=0
Time that DEND output can be accessed
after control when split bus (DMA
Interface) Obus=1
CL=10 pF
Min.
40
ns
2
ns
3
2
ns
4
2
ns
5
30
ns
6
30
ns
9
ns
10
ns
11
ns
12
ns
13
2
ns
14
2
ns
15
30
ns
16
70
ns
17
70
ns
18
ns
19
50
ns
20
250
ns
21
ns
22
2
30
CL=50 pF
CL=30 pF
CL=10 pF
2
CL=30 pF
CL=10 pF
30
2
CL=30 pF
30
tdis (CTRLH –Dreq)
Time that DREQ is disabled after control
ten (CTRL – Dreq)
Time that DREQ is enabled after control
30
twh (Dreq)
DREQ output "H" pulse width
20
td (CTRL - INT)
INT output negated delay time
twh (INT)
INT output “H” pulse width
td (DREQ - DV)
CL=10 pF
Ref.
no.
1
tdis (CTRL – Dreq)
tdis (CTRL-Dend)
Unit
ns
Time that DEND output is valid after
control when CPU bus and split bus
(DMA Interface) Obus=1
Time that DEND output is enabled after
control when CPU bus and split bus
(DMA Interface) Obus=1
Time that DEND output is disabled after
control when CPU bus and split bus
(DMA Interface) Obus=1
Time that DREQ is disabled after control
ten (CTRL – Dend)
Rated value
Typ.
Max.
CL=30 pF
650
Data access after DREQ begins to be
0
ns
23
asserted when split bus (DMA Interface)
Obus=0
td (DREQ - DendV) Time that DEND can be accessed after
0
ns
24
DREQ begins to be asserted when split
bus (DMA Interface) Obus=0
Key
ta: Access time, tv: Valid time, ten: Output enabled time, tdis: Output disabled time, td: propagation delay
(A): Address, (D): Data, (Dend): DEND, (CTRL): Control, (V): Obus=0
rev.1.00
2006.3.14
page 104 of 127
M66596FP/WG
4.8 Required timing conditions (VIF = 2.7~3.6V, or 1.6~2.0V)
Rated value
Typ.
Max.
Ref.
no.
30
ns
30
Address read setup time
0
ns
31
10
ns
32
thw (A)
Address setup time when using multiplex
bus
Address write hold time
0
ns
33
thr (A)
Address read hold time
30
ns
34
Address setup hold time when using
multiplex bus
ALE pulse width when using multiplex bus
0
ns
35
10
ns
36
Item
tsuw (A)
Address write setup time
tsur (A)
tsu (A - ALE)
th (A - ALE)
tw (ALE)
tdwr (ALE - CTRL)
CL=50 pF
Min.
7
ns
37
trec (ALE)
Write / read delay time when using multiplex
bus
ALE recovery time when using multiplex bus
0
ns
38
tw (CTRL)
Control pulse width (write)
30
ns
39
trec (CTRL)
Control recovery time (FIFO)
30
ns
40
trecr (CTRL)
Control recovery time (REG)
12
ns
41
Control pulse width (read)
30
ns
42
tsu (D)
Data setup time
20
ns
43
th (D)
Data hold time
0
ns
44
tsu (Dend)
DEND input setup time
30
ns
45
th (Dend)
DEND input hold time
0
ns
46
8-bit FIFO access
16-bit FIFO access
30
50
ns
ns
47
tw (cycle)
FIFO access
cycle time
8- / a6-bit FIFO access
when using multiplex bus
When using split bus, and
Obus=0
When using split bus, and
Obus=1 *1)
84
ns
12
ns
30
ns
30
ns
Control recovery time for burst transfers
12
ns
49
tsud (A)
DMA address write setup time
15
ns
50
thd (A)
DMA address write hold time
0
ns
51
twr (CTRL)
tw (CTRL_B)
Control pulse
width when
using burst
transfers
When using DMA transfers
with CPU bus
trec (CTRL_B)
Key
Measurement
conditions /
other
Unit
Symbol
48
tw (RST)
Reset pulse width time
100
ns
52
tst (RST)
Control starts time after reset
500
ns
53
tsuw: Write setup time, tsur: Read setup time, tsu: Setup time
thw: Write hold time, thr: Read hold time, th: Hold time, tw: Pulse width, twr: Read pulse width
tdwr: Read / write delay time, trec: Recovery time, trecr: Register recovery time
tsud: DMA setup time, thd: DMA hold time, tst: Start time
(A): Address, (D): Data, (CTRL): Control, (CTRL_B): Burst control, (ALE): ALE
*1) Only for data writing, when the DACK0_N signal is assuring an active period of at least 30 ns, the DSTB0_N
signal can be accessed at a minimum of 12 ns.
rev.1.00
2006.3.14
page 105 of 127
M66596FP/WG
4.9 Timing diagrams
Table 4.1 Index for register access timing diagram
Bus specification
Separate bus
Separate bus
Multiplex bus
Multiplex bus
access
CPU
CPU
CPU
CPU
R/W
WRITE
READ
WRITE
READ
INDEX
4.9.1.1
4.9.1.2.
4.9.2.1.
4.9.2.2
Note
CPU bus 0
CPU bus 0
CPU bus 0
CPU bus 0
Table 4.2 Index for FIFO port access
Access
Bus I/F
I/F specifications when DFORM OBUS
R/W
Note
INDEX
specifications *2)
operating
CPU
CPU bus 0
Separate bus
WRITE 4.9.1.1
CPU
CPU bus 0
Separate bus
READ
4.9.1.2.
CPU
CPU bus 0
Multiplex bus
WRITE 4.9.2.1.
CPU
CPU bus 0
Multiplex bus
READ
4.9.2.2
DMA
CPU bus 2
ACK+RD/WR
010
WRITE Cycle steal transfer
4.9.3.1 *1)
DMA
CPU bus 2
ACK+RD/WR
010
READ
Cycle steal transfer
4.9.3.2 *1)
DMA
SPLIT bus 1
ACK+STB
110
1
WRITE Cycle steal transfer
4.9.3.3 *1)
DMA
SPLIT bus 1
ACK+STB
110
1
READ
Cycle steal transfer
4.9.3.4 *1)
DMA
SPLIT bus 1
ACK+STB
110
0
WRITE Cycle steal transfer
4.9.3.3 *1)
DMA
SPLIT bus 1
ACK+STB
110
0
READ
Cycle steal transfer
4.9.3.5 *1)
DMA
CPU bus 1
Separate bus
000
WRITE Cycle steal transfer
4.9.3.6
DMA
CPU bus 1
Separate bus
000
READ
Cycle steal transfer
4.9.3.7
DMA
SPLIT bus 2
ACK only
100
1
WRITE Cycle steal transfer
4.9.3.8 *1)
DMA
SPLIT bus 2
ACK only
100
1
READ
Cycle steal transfer
4.9.3.9 *1)
DMA
SPLIT bus 2
ACK only
100
0
WRITE Cycle steal transfer
4.9.3.8 *1)
DMA
SPLIT bus 2
ACK only
100
0
READ
Cycle steal transfer
4.9.3.10 *1)
DMA
CPU bus 3
ACK only
011
WRITE Cycle steal transfer
4.9.3.11 *1)
DMA
CPU bus 3
ACK only
011
READ
Cycle steal transfer
4.9.3.12 *1)
DMA
CPU bus 2
Multiplex bus
000
WRITE Cycle steal transfer
4.9.4.1
DMA
CPU bus 2
Multiplex bus
000
READ
Cycle steal transfer
4.9.4.2
DMA
CPU bus 1
ACK+RD/WR
010
WRITE
Burst transfer
4.9.5.1 *1)
DMA
CPU bus 1
ACK+RD/WR
010
READ
Burst transfer
4.9.5.2 *1)
DMA
SPLIT bus 1
ACK+STB
110
1
WRITE
Burst transfer
4.9.5.3 *1)
DMA
SPLIT bus 1
ACK+STB
110
1
READ
Burst transfer
4.9.5.4 *1)
DMA
SPLIT bus 1
ACK+STB
110
0
WRITE
Burst transfer
4.9.5.3 *1)
DMA
SPLIT bus 1
ACK+STB
110
0
READ
Burst transfer
4.9.5.5 *1)
DMA
CPU bus 2
Separate bus
000
WRITE
Burst transfer
4.9.5.6
DMA
CPU bus 2
Separate bus
000
READ
Burst transfer
4.9.5.7
DMA
SPLIT bus 2
ACK only
100
1
WRITE
Burst transfer
4.9.5.8 *1)
DMA
SPLIT bus 2
ACK only
100
1
READ
Burst transfer
4.9.5.9 *1)
DMA
SPLIT bus 2
ACK only
100
0
WRITE
Burst transfer
4.9.5.8 *1)
DMA
SPLIT bus 2
ACK only
100
0
READ
Burst transfer
4.9.5.10 *1)
DMA
CPU bus 3
ACK only
011
WRITE
Burst transfer
4.9.5.11 *1)
DMA
CPU bus 3
ACK only
011
READ
Burst transfer
4.9.5.12 *1)
DMA
CPU bus 1
Multiplex bus
000
WRITE
Burst transfer
4.9.6.1
DMA
CPU bus 1
Multiplex bus
000
READ
Burst transfer
4.9.6.2
*1) Because the address signal is not used, the timing will be the same for the separate bus and multiplex bus.
*2) The reading and writing timing are carried out using control signal. If the control signal is configured of a
combination of multiple signals, the ratings from the falling edge will be valid starting from when the active
delay signal changes.
The ratings from the rising edge will be valid starting from the change in signals that become inactive more
quickly.
rev.1.00
2006.3.14
page 106 of 127
M66596FP/WG
4.9.1 CPU access timing(when a separate bus is set)
4.9.1.1 CPU access write timing (when a separate bus is set)
33
30
thw(A)
tsuw(A)
Address determination
A6-A1
CS_N
Note 1-4
47
tw(cycle) Note 1-1
41
trec(CTRL), 40 trecr(CTRL)
39 tw(CTRL)
WR1_N,
WR0_N
Note 1-2
43
44
tsu(D)
th(D)
Data determination
D15-D0
4.9.1.2 CPU access read timing (when a separate bus is set)
1
ta(A)
34
31 tsur(A)
thr(A)
Address determination
CS_N
Note 1-4
47 tw(cycle)Note 1-1
42
twr(CTRL)
RD_N
Note 1-3
5
40
Note 1-1
trec(CTRL), trecr(CTRL)
4
3
ta(CTRL-D)
ten(CTRL-D)
41
tv(A) 2
tv(CTRL-D)
tdis(CTRL-D)
6
Data determination
D15-D0
Note 1-1: tw (cycle) and trec (CTRL) are necessary when accessing the FIFO.
Note 1-2: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N.
Note 1-3: The control signal when reading data is a combination of CS_N and RD_N.
Note 1-4: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly,
CS_N should not be timed to fall at the same timing that WR0_N and WR1_N are rising. In the instances noted
above, an interval of at least 10 ns must be left open.
rev.1.00
2006.3.14
page 107 of 127
M66596FP/WG
4.9.2 CPU access timing (when a multiplex bus is set)
4.9.2.1 CPU access write timing (when a multiplex bus is set)
47 tw (cycle) Note 2-1
32
35
tsu (A - ALE)
AD6-AD1 /
D15-D0
44
tsu (D)
th (A - ALE)
Address
determination
36
43
th (D)
Address
determinatio
Data determination
38
tw (ALE)
trec (ALE)
ALE
CS_N
Note 2-4
37
39
tw (CTRL)
tdwr (ALE - CTRL)
WR1_N,
WR0_N
Note 2-2
4.9.2.2 CPU access read timing (when a multiplex bus is set)
47
32
tsu (A - ALE)
th (A - ALE)
tw (cycle) Note 2-1
tdis (CTRL - D)
35
tv (CTRL - D)
AD6-AD1 /
D15-D0
Address
determination
36
tw (ALE)
Data
determination
6
4
Address
determination
ten (CTRL - D) 5
ta (CTRL - D)
3
ALE
trec (ALE) 38
CS_N
Note 2-4
37
tdwr (ALE - CTRL)
twr (CTRL)
42
RD_N
Note 2-3
Note 2-1: tw (cycle) and trec (CTRL) are necessary when accessing the FIFO.
Note 2-2: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N.
Note 2-3: The control signal when reading data is a combination of CS_N and RD_N.
Note 2-4: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted
above, an interval of at least 10 ns must be left open.
rev.1.00
2006.3.14
page 108 of 127
M66596FP/WG
4.9.3 DMA access timing(when a cycle steal transfer and separate bus are set)
4.9.3.1 DMA cycle steal transfer write timing (when a CPU bus address is not used: DFORM=010)
17
20
tdis (CTRL - Dreq)
DREQi_N
(i=0,1)
DACKi_N
(i=0,1)
twh (Dreq)
Note 3-1
19
ten (CTRL - Dreq)
Note 3-8
tw (CTRL)
39
WR1_N,
WR0_N
Note 3-2
44
43
tsu (D)
th (D)
Data determination
D15-D0
tsu (Dend)
DENDi_N
(i=0,1)
45
th (Dend) 46
DENDi determination
4.9.3.2 DMA cycle steal transfer read timing(when a CPU bus address is not used: DFORM=010)
17
20
tdis (CTRL - Dreq)
twh (Dreq)
DREQi_N
(i=0,1) Note 3-1
19 ten (CTRL - Dreq)
DACKi_N
(i=0,1)
Note 3-8
42
twr (CTRL)
RD_N
Note 3-3
ta (CTRL - D)
3
5
tv (CTRL - D)
Data determination
ta (CTRL - DendV)
11
DENDi_N
(i=0,1)
Note 3-9
rev.1.00
2006.3.14
6
tdis (CTRL - D)
ten (CTRL - D)
D15-D0
4
tv (CTRL - DendV)
DENDi_N determination
page 109 of 127
12
M66596FP/WG
4.9.3.3 DMA cycle steal transfer write timing for strobe use (split bus : DFORM=110, OBUS=1/0)
17
20
tdis (CTRL - Dreq)
twh (Dreq)
DREQ0_N
Note 3-1
19
ten (CTRL - Dreq)
DACK0_N
tw (CTRL) 39
STRB0_N
Note 3-4
43
tsu (D)
th (D)
44
Data determination
SD7-SD0
tsu (Dend)
DEND0_N
45
th (Dend) 46
DEND0_N determination
4.9.3.4 DMA cycle steal transfer read timing for strobe use(split bus : DFORM=110, OBUS=1)
17
twh (Dreq)
tdis (CTRL - Dreq)
20
DREQ0_N
Note 3-1
19 ten (CTRL - Dreq)
DACK0_N
twr (CTRL)
42
STRB0_N
Note 3-4
ta (CTRL - D) 3
5
ten (CTRL - D)
Data_N determination
SD7-SD0
ta (CTRL - Dend) 13
15
ten (CTRL - Dend)
DEND0_N
rev.1.00
2006.3.14
tv (CTRL - D) 4
6
tdis (CTRL - D)
DEND0_N determination
page 110 of 127
14
16
tv (CTRL - Dend)
tdis (CTRL - Dend)
M66596FP/WG
4.9.3.5 DMA cycle steal transfer read timing (split bus : DFORM=110,OBUS=0)
DMA transfer begins
17
twh (Dreq)
tdis (CTRL - Dreq)
20
DREQ0_N
19 ten (CTRL - Dreq)
Note 3-1
DACK0_N
42
twr (CTRL)
STRB0_N
Note 3-4
23
td (DREQ - DV)
ta (CTRL - DV)
9
tv (CTRL - DV)
Data determination
SD7-SD0
11
24 td (DREQ - DendV) ta (CTRL - DendV)
2006.3.14
tv (CTRL - DendV) 12
DEND0_N determination
DEND0_N
rev.1.00
10
page 111 of 127
M66596FP/WG
4.9.3.6 DMA cycle steal transfer write timing (CPU separate bus setting: DFORM=000)
18
DREQi_N
(i=0,1)
Note 3-1
twh (Dreq) 20
tdis (CTRLH - Dreq)
ten (CTRL - Dreq) 19
50
tsud (A)
51
thd (A)
Address determination
A6-A1
CS_N
Note 3-7
tw (CTRL) 39
WR0_N,
WR1_N
Note 3-5
tsu (D) 43
th (D)
44
Data determination
D15-D0
tsu (DEND)
45
th (DEND) 46
DENDi_N determination
DENDi _N
(i=0,1)
4.9.3.7 DMA cycle steal transfer read timing (CPU separate bus setting: DFORM=000)
17
tdis (CTRL - Dreq)
twh (Dreq)
DREQi_N
(i=0,1)
Note 3-1
31
ta (A)
1
tsur (A)
20
19 ten (CTRL - Dreq)
thr (A) 34
Address determination
A6-A1
CS_N
Note 3-7
twr (CTRL)
42
RD_N
5
ta (CTRL - D)
3
4
tv (CTRL - D)
ten (CTRL - D)
tdis (CTRL - D)
ta (CTRL - DendV) 11
DENDi _N
(i=0,1)
Note 3-9
2006.3.14
6
Data determination
D15-D0
rev.1.00
2
tv (A)
Note 3-6
tv (CTRL - DendV)
DENDi_N determination
page 112 of 127
12
M66596FP/WG
4.9.3.8 DMA cycle steal transfer write timing when strobe is not used (split bus : DFORM=100, OBUS=1/0)
tdis (CTRL - Dreq)
17
twh (Dreq)
DREQi_N
(i=0, 1) Note
3-1
19
20
ten (CTRL - Dreq)
tw (CTRL) 39
DACKi_N
(i=0,1)
43
tsu (D)
th (D)
44
Data determination
SD7-SD0
45
DENDi_N
(i=0,1)
tsu (Dend)
th (Dend) 46
DENDi determination
4.9.3.9 DMA cycle steal transfer read timing when strobe is not used (split bus : DFORM=100, OBUS=1)
17 tdis (CTRL - Dreq)
DREQi_N
(i=0, 1)
twh (Dreq) 20
19 ten (CTRL - Dreq)
Note 3-1
twr (CTRL)
42
DACKi_N
(i=0,1)
ta (CTRL - D)
5
3
tv (CTRL - D)
Data determination
SD7-SD0
15
ta (CTRL - Dend) 13
tv (CTRL - Dend)
ten (CTRL - Dend)
DENDi_N
(i=0, 1)
2006.3.14
6
tdis (CTRL - D)
ten (CTRL - D)
rev.1.00
4
16
tdis (CTRL - Dend)
DENDi_N determination
page 113 of 127
14
M66596FP/WG
4.9.3.10 DMA cycle steal transfer read timing when strobe is not used(split bus : DFORM=100, OBUS=0)
DMA transfer begins
17
twh (Dreq)
tdis (CTRL - Dreq)
20
DREQi_N
(i=0, 1)
19 ten (CTRL - Dreq)
Note 3-1
twr (CTRL)
42
DACKi_N
(i=0, 1)
23
td (DREQ - DV)
ta (CTRL - DV)
9
tv (CTRL - DV)
Data determination
SD7-SD0
11
24 td (DREQ - DendV) ta (CTRL - DendV)
DENDi_N
(i=0, 1)
Note 3-9
rev.1.00
2006.3.14
10
tv (CTRL - DendV) 12
DENDi_N determination
page 114 of 127
M66596FP/WG
4.9.3.11 DMA cycle steal transfer write timing(CPU bus address not used: DFORM=011)
17
20
tdis (CTRL - Dreq)
twh (Dreq)
DREQi_N
(i=0,1)
Note 3-1
19
tw (CTRL)
ten (CTRL - Dreq)
39
DACKi_N
(i=0,1)
Note 3-8
44
43
tsu (D)
th (D)
Data determination
D15-D0
tsu (Dend)
DENDi_N
(i=0,1)
45
th (Dend) 46
DENDi determination
4.9.3.12 DMA cycle steal transfer read timing(CPU bus address not used: DFORM=011)
17
20
tdis (CTRL - Dreq)
twh (Dreq)
DREQi_N
(i=0,1) Note 3-1
19 ten (CTRL - Dreq)
twr (CTRL) 42
DACKi_N
(i=0,1)
Note 3-8
ta (CTRL - D)
3
5
tv (CTRL - D)
Data determination
ta (CTRL - DendV)
11
DENDi_N
(i=0,1)
rev.1.00
2006.3.14
6
tdis (CTRL - D)
ten (CTRL - D)
D15-D0
4
tv (CTRL - DendV)
DENDi_N determination
page 115 of 127
12
M66596FP/WG
Note 3-1: The inactive condition for DREQi_N (i=0, 1) is the control signal. If there is a next DMA transfer, the delay
ratings for twh (Dreq) and ten (CTRL-Dreq) will be valid for the time until DREQi_N becomes active is twh
(Dreq).
Note 3-2: The control signal when writing data is a combination of DACKi_N, WR1_N, and WR0_N.
Note 3-3: The control signal when reading data is a combination of DACKi_N and RD_N.
Note 3-4: The control signal when writing data is a combination of DACK0 and DSTRB0_N.
Note 3-5: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.
Note 3-6: The control signal when reading data is a combination of CS_N and RD_N.
Note 3-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances
noted above, an interval of at least 10 ns must be left open.
Note 3-8: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising (or falling).
Similarly, DACK should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are
rising. In the instances noted above, an interval of at least 10 ns must be left open.
Note 3-9: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined
time is "(24)td(DREQ-DendV)".
rev.1.00
2006.3.14
page 116 of 127
M66596FP/WG
4.9.4 DMA access timing(cycle steal transfer, when a multiplex bus is set)
4.9.4.1 DMA cycle steal transfer write timing (CPU multiplex bus setting: DFORM=000)
tdis (CTRLH - Dreq)
18
twh (Dreq) 20
DREQi_N
(i=0,1)
ten (CTRL - Dreq) 19
tsu (A - ALE) th (A - ALE)
32
AD6-AD1 /
D15-D0
Address
determination
tw (ALE)
35
tsu (D)
43
th (D) 44
Address
determination
Data determination
36
38
trec (ALE)
ALE
CS_N
Note 4-3
tw (CTRL) 39
37 tdwr (ALE - CTRL)
WR1_N,
WR0_N
Note 4-1
tsu (DEND)
45
DENDi_N
(i=0,1)
th (DEND) 46
DENDi_N determination
4.9.4.2 DMA cycle steal transfer read timing (CPU multiplex bus setting: DFORM=000)
17 tdis (CTRL - Dreq)
DREQi_N
(i=0,1)
twh (Dreq) 20
19 ten (CTRL - Dreq)
32
tsu (A - ALE) th (A - ALE)
tdis (CTRL - D) 6
35
tv (CTRL - D)
A6-A1 /
D15-A0
Address
determination
36
Data determination
tw (ALE)
4
Address
determination
ten (CTRL - D) 5
ta (CTRL - D) 3
ALE
trec (ALE) 38
CS_N
Note 4-3
37 tdwr (ALE - CTRL)
twr (CTRL) 42
RD_N
Note 4-2
12
ta (CTRL - DendV) 11
DENDi _N
(i=0,1)
tv (CTRL - DendV)
DENDi_N determination
Note 4-4
Note 4-1: The control signal when writing data is a combination of CS_N, WR0_N, and WR1_N.
Note 4-2: The control signal when reading data is a combination of CS_N and RD_N.
Note 4-3: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are rising. In the
instances noted above, an interval of at least 10 ns must be left open.
Note 4-4: When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)".
rev.1.00
2006.3.14
page 117 of 127
M66596FP/WG
4.9.5 DMA access timing (when burst transfer and separate bus are set)
4.9.5.1 DMA burst transfer write timing (CPU bus address not used: DFORM=010)
17 tdis (CTRL - Dreq)
18
tdis (CTRLH - Dreq)
DREQi_N
(i=0,1)
DACKi_N
(i=0,1)
Note 5-8
tw (cycle)
47
48
tw (CTRL_B) trec (CTRL_B) 49
WR1_N,
WR0_N
Note 5-1
43 tsu (D) th (D) 44
D0
D15-D0
D1
D2
Dn
45 tsu (Dend) th (Dend) 46
DENDi_N
(i=0,1)
4.9.5.2 DMA burst transfer read timing (CPU bus address not used: DFORM=010)
17
tdis (CTRL - Dreq)
DREQi_N
(i=0,1)
DACKi_N
(i=0,1)
Note 5-8
48
RD_N
Note
5-2
D15-D0
tw (cycle) 47
tw (CTRL_B) trec (CTRL_B) 49
3
ta (CTRL - D)
tv (CTRL - D) 4
D0
D1
Dn-1
12
11
DENDi _N
(i=0,1)
Note 5-6
rev.1.00
2006.3.14
Dn
page 118 of 127
ta (CTRL - DendV)
tv (CTRL - DendV)
M66596FP/WG
4.9.5.3 DMA burst transfer write timing for strobe use(split bus : DFORM=110, OBUS=1/0)
17 tdis (CTRL - Dreq)
18 tdis (CTRLH - Dreq)
DREQ0_N
DACK0_N
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
DSTRB0_N
Note 5-3
43 tsu (D) th (D) 44
D0
SD7-SD0
D1
D2
Dn
45
46
tsu (Dend) th (Dend)
DEND0_N
4.9.5.4 DMA burst transfer read timing for strobe use(split bus : DFORM=110, OBUS=1)
17
tdis (CTRL - Dreq)
DREQ0_N
DACK0_N
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
STRB0_N
Note 5-3
3
ta (CTRL - D)
SD7-SD0
tv (CTRL - D) 4
D0
D1
Dn-1
13
ta (CTRL - Dend)
DEND0_N
rev.1.00
2006.3.14
page 119 of 127
Dn
tv (CTRL - Dend)
14
M66596FP/WG
4.9.5.5 DMA burst transfer read timing for strobe use (split bus : DFORM=110, OBUS=0)
17
tdis (CTRL - Dreq)
DREQ0_N
DACK0_N
tw (cycle) 47
48
tw (CTRL_B) trec (CTRL_B) 49
STRB0_N
Note 5-3
23
9
td (DREQ - DV)
SD7-SD0
Note 5-6
ta (CTRL - DV) tv (CTRL - DV)
D0
24 td (DREQ - DendV)
DEND0_N
Note 5-6
rev.1.00
2006.3.14
page 120 of 127
D1
10
Dn-1
11
Dn
12
ta (CTRL - DendV)
tv (CTRL - DendV)
M66596FP/WG
4.9.5.6 DMA burst transfer write timing (separate bus setting: DFORM=000)
tdis (CTRL - Dreq)
17
18
tdis (CTRLH - Dreq)
DREQi _N
(i=0,1)
50
thd (A) 51
tsud (A)
Address
determination
A6-1
Address
determination
Address
determination
Address
determination
CS_N
Note 5-7
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
WR0_N,
WR1_N
Note 5-4
43 tsu (D) th (D) 44
D0
D15-D0
D1
D2
Dn
46
45 tsu (DEND) th (DEND)
DENDi _N
(i=0,1)
4.9.5.7 DMA burst transfer read timing(separate bus setting: DFORM=000)
tdis (CTRL - Dreq) 17
DREQi_N
(i=0,1)
31 tsur (A)
thr (A) 34
Address
determination
A6-A1
Address
determination
Address
determination
Address
determination
CS_N
Note 5-7
tw (cycle) 47
48
tw (CTRL_B)
RD_N
Note 5-5
3
D15-D0
ta (A) 1
ta (CTRL-D)
trec (CTRL_B)
tv (A) 2
tv (CTRL-D) 4
D0
DENDi_N
(i=0,1)
Note 5-6
rev.1.00
2006.3.14
49
page 121 of 127
D1
Dn-1
Dn
11
12
ta (CTRL - DendV)
tv (CTRL - DendV)
M66596FP/WG
4.9.5.8 DMA burst transfer write timing when no strobe is used (split bus: DFORM=100, OBUS=1/0)
17 tdis (CTRL - Dreq)
18
tdis (CTRLH - Dreq)
DREQi_N
(i=0, 1)
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
DACKi_N
(i=0, 1)
43 tsu (D) th (D) 44
D0
SD7-SD0
D1
D2
Dn
46
45 tsu (Dend) th (Dend)
DENDi_N
(i=0, 1)
4.9.5.9 DMA burst transfer read timing when no strobe is used (split bus: DFORM=100, OBUS=1)
17
tdis (CTRL - Dreq)
DREQi_N
(i=0, 1)
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
DACKi_N
(i=0, 1)
3
tv (CTRL - D)
ta (CTRL - D)
SD7-SD0
D0
4
D1
Dn-1
13
DENDi_N
(i=0, 1)
rev.1.00
2006.3.14
page 122 of 127
Dn
14
ta (CTRL - Dend)
tv (CTRL - DendV)
M66596FP/WG
4.9.5.10 DMA burst transfer read timing when no strobe is used (split bus: DFORM=100, OBUS=0)
17
tdis (CTRL - Dreq)
DREQi_N
(i=0, 1)
tw (cycle) 47
48
tw (CTRL_B) trec (CTRL_B) 49
DACKi_N
(i=0, 1)
23
9
td (DREQ - DV)
SD7-SD0
Note 5-6
D0
24 td (DREQ - DendV)
DENDi_N
(i=0, 1)
Note 5-6
rev.1.00
2006.3.14
tv (CTRL - DV) 10
ta (CTRL - DV)
page 123 of 127
D1
Dn-1
11 ta (CTRL - DendV)
Dn
12
tv (CTRL - DendV)
M66596FP/WG
4.9.5.11 DMA Burst transfer write timing (CPU bus address not used: DFORM=011)
17 tdis (CTRL - Dreq)
18
tdis (CTRLH - Dreq)
DREQi_N
(i=0,1)
tw (cycle)
48
47
tw (CTRL_B) trec (CTRL_B) 49
DACKi_N
(i=0,1)
43 tsu (D) th (D) 44
D0
D15-D0
D1
D2
Dn
45 tsu (Dend) th (Dend) 46
DENDi_N
(i=0,1)
4.9.5.12 DMA burst transfer read timing (CPU bus address not used: DFORM=011)
17
tdis (CTRL - Dreq)
DREQi_N
(i=0,1)
48
tw (cycle) 47
tw (CTRL_B) trec (CTRL_B) 49
DACKi_N
(i=0,1)
3
D15-D0
ta (CTRL - D)
tv (CTRL - D) 4
D0
D1
Dn-1
11
ta (CTRL - DendV)
Dn
12
tv (CTRL - DendV)
DENDi _N
(i=0,1)
Note 5-6
Note 5-1: The control signal when writing data is a combination of DACKi_N(i=0, 1), WR0_N and WR1_N.
Note 5-2: The control signal when reading data is a combination of DACKi_N and RD_N.
Note 5-3: The control signal when writing data is a combination of DACK0 and DSTRB0_N.
Note 5-4: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.
Note 5-5: The control signal when reading data is a combination of CS_N and RD_N.
Note 5-6: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined
time is "(24)td(DREQ-DendV)".
Note 5-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted
above, an interval must be needed at least 10ns.
Note 5-8:. RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising. Similarly,
DACKi_N should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the
instances noted above, an interval must be needed at least 10ns.
rev.1.00
2006.3.14
page 124 of 127
M66596FP/WG
4.9.6 DMA access timing(burst transfer, when a multiplex bus is set)
4.9.6.1 DMA burst transfer write timing (CPU multiplex bus setting: DFORM=000)
17
tdis (CTRL - Dreq)
18
tdis (CTRLH - Dreq)
DREQi_N
(i=0, 1)
tsu (A - ALE)
AD6-AD1 /
D15-D0
thw (A - ALE)
Address
D0
Address
tw (cycle)
tw (ALE)
ALE
43 tsu (D) th (D) 44
35
32
D1
Address
Dn
47
36
CS_N
Note 6-3
tdwr (ALE_CTRL) 37
48
trec (CTRL_B) 49
tw (CTRL_B)
WR0_N,
WR1_N
Note 6-1
46
45 tsu (DEND) th (DEND)
DENDi_N
(i=0, 1)
4.9.6.2 DMA burst transfer read timing(CPU multiplex bus setting: DFORM=000)
17
tdis (CTRL - Dreq)
DREQi_N
(i=0, 1)
tsu (A - ALE) th (A - ALE) 35
AD6-AD1 /
D15-D0
D0
Address
tw (ALE)
ALE
3 ta (CTRL-D)
tv (CTRL-D) 4
32
Address
D1
Address
tw (cycle) 47
36
CS_N
Note 6-3
tdwr (ALE_CTRL) 37
trec (CTRL_B) 49
tw (CTRL_B)
48
RD_N
Note 6-2
11
DENDi_N
(i=0, 1)
Note 6-4
rev.1.00
2006.3.14
page 125 of 127
ta (CTRL - DendV)
tv (CTRL - DendV) 12
Dn
M66596FP/WG
Note 6-1: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.
Note 6-2: The control signal when reading data is a combination of CS_N and RD_N.
Note 6-3: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall at the same timing that RD_N or WR0_N and WR1_N are rising. In the instances
noted above, an interval of at least 10 ns must be left open.
Note 6-4: When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)".
rev.1.00
2006.3.14
page 126 of 127
M66596FP/WG
4.10 Interrupt timing
22
twh (INT)
INT_N
21
td (CTRL - INT)
CS_N,
WR0_N, WR1_N
Note 7-1
Note 7-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active (“L”) overlap period.
The ratings from the rising edge are valid starting from the earliest change in the inactive signal.
4.11 Reset timing
52
tw (RST)
RST_N
53
tst (RST)
CS_N,
WR0_N, WR1_N
Note 8-1
Note 8-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active (“L”) overlap period.
The ratings from the rising edge are valid starting from the earliest change in the inactive signal.
rev.1.00
2006.3.14
page 127 of 127
REVISION HISTORY
Rev.
Date
0.79
0.79A
2004.07.7
2004.07.21
2004.10.5
M66596 Data Sheet
Description
Summary
Page
6
52
52-53
53
53
4
(1.3)
Change *3), *5), *6) of Table 1.1
Change INDEX of Table 3.1
Change INDEX of Table 3.2
Change note *2) --> *1) of Table 3.2
Delete note *3) of Table 3.2
Added:
Figure 1.2
5
(1.4)
Modified:
“Table 1.1 describes the controller pins.”
9
(1.6)
Modified:
“The controller is configured with an analog front end unit (AFE),”
12
(2.1)
Corrected:
Addr 0x6C “Pipe period control register”
First edition issued
13-14 Added:
(2.2) Addr 0x32 “BRDYM”, “PCSE”
Addr 0x70 – 0x78 “INBUFM”
15-45 Added and corrected : Refernce to chaptor 2 and 3 in noteof table.
(2.3-2.14) Corrected: Note *1)
15
(2.3)
Added: “or clock stop state”
Corrected: Note *1)
19
Modified: “Each bit of the DVSTCTR register”
(2.4.1) Added: “According to the USB specification, USB idle state…”
20
(2.5)
0.80
Modified: Note *1)
22
Modified: “Table 2.7 and Table 2.8 show the byte Endian operation…”
(2.5.2)
23
Corrected: Note 5, 6, 7, 8
25(2.6) Corrected: Note *7)
28
(2.7)
Added: PCSE and BRDYM bits
Added: Note *3), *4)
40
Corrected: PID bit
(2.13) Modified: Note *5)
42-45 Corrected: Note *4), *5), *6), *7)
(2.14) Corrected: Default value of bit6 of PIPEMAXP
Corrected and added: Note *12), *13), *14), *15)
104 Moved: Chaptor3 to Chaptor4
(4)
105,106 Corrected:
(4.3,4.4) Average supply current at HS operation; 60mA to 40mA.
51
(3)
2006.3.14
1.00
Added: Chaptor 3 Description of Operation
7
(1.7)
Added: 1.7
17
(2.2)
Corrected: Addr 0x68, 0x6A
2006.3.14
18
(2.3)
Corrected: Bit symbol of bit 5.
Corrected: Description of FSRPC.
20
Added: Description of Line status monitor
(2.3.3)
20
Added: note of Table2.5.
(2.3.4)
21
(2.4)
Corrected: Note *3)
22
(2.4)
Corrected: Description of 2.4.1
Added: Description of 2.4.2
27
(2.6)
Added: Note *6)
28
(2.6)
Corrected: Note *9)
41
Corrected: Note *9), *10)
(2.13)
46
Corrected: Bit alignment of address 0x68.
(2.14)
48
Corrected: Note *15), *18)
(2.14)
49
Corrected: BIGENB bit of Table 3.2.
(3.1.2)
54
Corrected: Description of Auto clock supply function.
(3.1.7.6)
1.00
55
Added: 3.1.7.7
(3.1.7.7)
59
Corrected: Description of (2).
(3.1.8.6)
60
(3.2)
Corrected: Description of SOFR and SIGN of Table 3.7.
63
Added: 3.2.2
(3.2.2)
64
Corrected: Table 3.9
(3.2.3)
65
Corrected: Description of “If a Zero-length ...” , “The conditions on ...”
(3.2.3)
66
Added: “*However ...”
(3.2.4.1)
66
Added: “When a token is ...”
(3.2.4.1)
71
Added: “This interruption is ...”
(3.2.9)
(3.2.10)
(3.2.11)
71
Corrected: Description of 3.2.12.
(3.2.12)
73
Added: “In the Host mode do not set ...”
(3.3.3)
74
Corrected: Description of 3.3.4.
(3.3.4)
2006.3.14
75
Added: “In control transfer of ...”
(3.3.6)
87
Deleted: “If the short packet...”
(3.6.2)
1.00
87
Added: “The 1st data packet ...”
(3.6.3)
102 Added: Description of (3)
(4.5.2)
113 Corrected: Chapter name “... when strobe is not used”
(4.9.3.8)
(4.9.3.9)
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