USB Compliance Checklist Peripheral Silicon (excluding hubs) July 19, 1999 USB Device Product Information Date Vendor Name Vendor Street Address Vendor City, State, Zip Vendor Phone Number Vendor Contact, Title Product Name Product Model Number Product Revision Level July 19, 1999 Motorola MPC823 Z3 1 7/19/99 Introduction This is a checklist to help in design reviews of ASICs and Components for Peripherals to check their compliance with Universal Serial Bus Specification, Revision 1.0. This checklist is also used to qualify a USB product for the System Integrator List by creating a paper trail of testing for USB compliance. USB Protocol Checklist The reference setup for this checklist is a USB link with one USB on each side of it. This checklist specifies behavior expected from these USB agents to satisfy chapter 8 of the USB protocol. One of these two agents is the controlling agent (host or hub) and the other is the controlled agent (device or hub). Except for a few noted items, both types of agents need to adhere to the same requirements. The hub is a special entity because its upstream ports act like a device and its downstream ports act like a host, and it is covered in a separate checklist. For the purposes of this checklist, the terms host and hub downstream port are equivalent as are the terms device and hub upstream/root port. Hub specific requirements are listed in the hub chapter. This checklist is organized in two broad sections. The first section lists expected or normal behavior from an USB agent when it drives the bus or receives from the bus . So tests in this section need to be done in two parts - ensure that the agent drives the correct signals and ensure that the agent accepts correct signaling (correctness by design and correctness by test). The second section lists expected behavior of an USB agent when it sees an error or abnormal condition on the bus (test of design robustness). Any deviation from this checklist should be noted and explained in the explanations area. These lists are organized starting with the smallest signal entity on the bus and ending at the transfer level. Some definitions of terms used in the checklist. Note that some terms are overloaded (e.g. data) and definition should be derived from context. Bit order is from left to right unless specified otherwise. Sense: The relationship between D+ and D- voltages for J state on a USB link e.g. on a fullspeed link, D+ > D- ; on a low-speed link D+ < D-. NZB: NrZ bit; smallest data structure referenced in spec; represented as 1, 0 and S (single-ended 0) e.g. 1 NIB: NrzI bit; smallest data structure referenced in spec; represented as J, K and 0 (single-ended 0) e.g. J Field: the next higher form of data structure; can be represented as NIBs or NZBs e.g. sync field is KJKJKJKK or 00000001 Packet: is the most referenced data structure; is built out of fields e.g. Token packet Phase: of a transaction is made up of 0 or 1 packet e.g. token phase 2 7/19/99 Transaction: is the basic unit for unidirectional data transfer and is a set of packets; for unidirectional endpoints (bulk, interrupt, iso) this is the final level of communication with protocol implications e.g. OUT transaction Stage: is a set of one or more unidirectional transactions e.g. data stage Transfer: is a unit of bi-directional data transfer and is built out of stages. It is used by bi-directional endpoints only. e.g. control transfer Turnaround time: time between an agent seeing the EOP for the previous packet and starting to drive the bus for a new packet i.e. J period after 0 of the EOP. This time also applies to the period between packets when the host is driving both packets. Time-out period: amount of time that an agent awaiting a response waits before invalidating the transaction Target: could be a pipe in the host or endpoint in a device The addendum lists test scenarios which can be used to develop tests for the items in the checklist as well as some useful Perl programs. 3 7/19/99 Design-and-Test section: Bitstream A bitstream is a set of bits from J,K, 0 (nrzi) or 0,1,S(nrz) Name BSD 1 BSD 2 BSD 3 BSD 4 BSD 5 BSD 6 BSD 7 BSD 8 BSD 9 BSD 10 BSD 11 BSD 12 BSD 13 BSD 14 BSD 15 BSD 16 Test description Is >=2.5 us of NIB 0 anywhere in a bitstream recognized on the root port of a device as a USB RESET? Is >=2.5 us of NIB 0 anywhere in a bitstream recognized by the host or the downstream port of a hub as a disconnect event? Is >=2.5 us of NIB J recognized by the host or a downstream port of a hub as a connect event? Is >=20 ms of NIB K followed by an EOP recognized as an end of resume event by a target? Does any transition from the J state on the root port of a suspended device wakeup the device? Is the possibility of a NIB 1 <1 bit time during bus transitions accounted for? Is the sense of signaling on a link either full-speed or low-speed but not both? Does the sense of signaling on a link correspond to speed of link? Is the bitstream on the bus nrzi encoded? Does the bitstream on the bus implement bit stuffing prior to transmission? Does the CRC bitstream on the bus implement bit stuffing? Is bit stuffing implemented even if a stuffed bit is required after the last bit of the packet? Is bit stuffing done after the CRC computation on the transmitted bit stream? Is nrzi encoding done after the bit stuffing on the transmitted bit stream? Is nrzi->nrz decoding done before bit unstuffing? Is bit unstuffing done before the bitstream is parsed? Spec sec Status 7.1.4.3 yes _4 no___ 7.1.4.1 yes _4 no___ 7.1.4.1 yes _4 no___ 11.5.1 yes _4_ no___ 7.1.4.5 yes _4_ no___ 7.1.13 11.2.5 yes _4 no___ yes _4 no___ 7.1.4 7.1.5 7.1.6 8.3.5 8.3.5 yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ 8.3.5 7.1.6 7.1.6 7.1.6 yes _4 yes _4 yes _4 yes _4 no___ no___ no___ no___ Spec sec 8.2 8.3.1 8.3.1 8.3.5.1 Status yes _4 yes _4 yes _4 yes _4 no___ no___ no___ no___ 8.3.5.1 yes _4 no___ 8.3.5.2 yes _4 no___ Field A field can be sync PID address endpoint frame number token CRC data data CRC EOP Name FLD 1 FLD 2 FLD 3 FLD 4 FLD 5 FLD 6 - 8 bit field with NZB value 00000001 - listed in Table 8-1 of spec - 7 bit field - 4 bit field - 11 bit field - 5 bit field - 0 to 1023 byte field - 16 bit field - 3 bit field with NIB value 00J Test description Is the sync field as measured on the bus wires correct i.e. NIB KJKJKJKK? Is the packet type in the PID one of those listed in Table 8-1 Is the PID check the one’s complement of the packet type field Is the token CRC generated with the polynomial NZB 00101 on addressendpoint/frame number fields Does the CRC computation on a token/SOF bitstream leave a residual of NZB 01100 at the EOP Is the data CRC generated with the polynomial NZB1000000000000101 on the data field 4 7/19/99 FLD 7 FLD 8 FLD 9 FLD 10 FLD 11 FLD 12 FLD 13 FLD 14 FLD 15 FLD 16 FLD 17 FLD 18 FLD19 Does the CRC computation on a data packet bitstream leave a residual of NZB 1000000000001101 at the EOP Is the 7-bit address field sent out LSB first on the bus Is the 4-bit endpoint field sent out LSB first on the bus Is the 11-bit frame number field sent out LSB first on the bus Is each data byte in the data field sent out LSB first Is the CRC shift register contents inverted to form the CRC field Is the CRC field sent out MSB first Is the EOP correctly constituted i.e. NIB 00J Does a full-speed receiver (on a non-hub device) recognize 82ns to 2.5 us of NIB 0 followed by a J transition as a valid EOP Does a low-speed receiver (on a non-hub device) recognize 670 ns to 2.5 us of NIB 0 followed by a J transition as a valid EOP Does a low speed device recognize low-speed keepalive strobes Does a low speed device support one control endpoint and at most two other endpoint numbers Are the endpoints on a low speed device either control or interrupt type 8.3.5.2 yes _4 no___ 8.3.2.1 8.3.2.2 8.3.3 8.3.4 8.3.5 8.3.5 7.1.11.2 7.1.12 yes _4 yes _4 yes _4 yes _4 yes _4 yes _4 yes _4 yes _4 7.1.12 yes _4 no___ 11.2.5.1 8.3.2.2 yes _4 no___ yes _4 no___ 8.3.2.2 yes _4_ no___ no___ no___ no___ no___ no___ no___ no___ no___ Packet A packet is made up of fields which are formatted as described in sec. 8.4 of spec and can be one of the following: PRE - sync PID SOF - sync PID timestamp token CRC EOP Token - sync PID endpt token CRC EOP data - sync PID data.......... data dataCRC EOP handshake - sync PID EOP Name PKD 1 PKD 2 PKD 3 PKD 4 PKD 5 PKD 6 PKD 7 PKD 8 PKD 9 PKD 10 PKD 11 Test description Is the PRE packet 16 bits long Is the PRE packet constituted as sync followed by PID Is the Token packet 32 bits + EOP Is the token constituted as sync followed by PID followed by address followed by endpoint followed by token CRC followed by EOP Is the SOF packet 32 bits + EOP Is the SOF constituted as sync followed by PID followed by frame number followed by token CRC followed by EOP Is the handshake packet 16 bits + EOP Is the handshake constituted as sync followed by PID followed by EOP Is the data packet an integral number of bytes ( 4 to 1027) + EOP Is the data packet constituted as sync followed by PID followed by 0 to 1023 bytes of data followed by data CRC followed by EOP Is the data payload of a low speed packet limited to 8 bytes Spec sec 8.6.5 8.6.5 8.4.1 8.4.1 Status yes _4 yes _4 yes _4 yes _4 8.4.2 8.4.2 yes _4 no___ yes _4 no___ 8.4.4 8.4.4 8.4.3 8.4.3 yes _4 yes _4 yes _4 yes _4 8.6.5 yes _4 no___ Transaction Transactions are sets of packets used for unidirectional data transfer and can be one of the following: (host phase in italics; device phase in regular font) SOF setup data ack out data ack/nak/stall out data0 in data ack in data0/nak/stall pre setup pre data ack pre out pre data ack/nak/stall pre in data pre ack pre in nak/stall 5 7/19/99 no___ no___ no___ no___ no___ no___ no___ no___ Name TRD 1 TRD 2 Test description Does the device implement default address of 0 on device reset Does the device implement a bi-directional control endpoint 0 for every address Does the generated packet fit the phase of the transaction as listed above Is the turnaround time of a packet-sourcing agent greater than 2 bit times Is the turnaround time of a packet-sourcing agent less than 6.5 (7.5 with integrated cable) bit times Is the time-out period at an agent awaiting response greater than 16 bit times Is the time-out period at an agent awaiting response less than 18 bit times Is an unsuccessful (NAK or time-out in non-token phase) transaction retried Does the retried transaction use the same data PID as the original transaction Do interrupt endpoints used in rate feedback mode toggle the sequence bit without regard to presence or type of handshake Do handshakes conform to order of precedence detailed in tables of Sec. 8.4.5 Are low speed transactions limited to those needed to support interrupt and control endpoints Does an ISO endpoint synthesize frame markers to replace SOFs which may be lost due to bus error Does an ISO pipe handle holes/bubbles in pipe which may arise during suspend-resume operation TRD 3 TRD 4 TRD 5 TRD 6 TRD 7 TRD 8 TRD 9 TRD 10 TRD 11 TRD 12 TRD 13 TRD 14 Spec sec 8.3.2.1 8.3.2.2 Status yes _4 no___ yes _4 no___ 8.5,8.6.5 7.1.15 7.1.15 yes _4 no___ yes _4 no___ yes _4 no___ 7.1.16 yes _4 no___ 7.1.16 8.6.2-4 8.6.2-4 yes _4 no___ yes _4 no___ yes _4 no___ 8.5.3 yes _4 no___ see note 0 yes _4 no___ see note 1 yes _4 no___ 8.4.5 8.6.5 5.10.6 yes _4 no___ see note 0 yes _4 no___ Transfer Transfers are data structures used by bi-directional (control endpoints). The transfer is made up of stages which are sets of unidirectional transactions. They can be one of: setup0 out1 out0 out1 ... out0/1 in1 setup0 in1 in0 in1 ... in0/1 out1 setup0 in1 Transactions in italics constitute the data stage ; there may or may not be a data stage between the setup stage and status stage. Suffix of 0 or 1 indicates the data PID used in the transaction Name TFD 1 TFD 2 TFD 3 TFD 4 TFD 5 TFD 6 Test description Does the setup stage use a data0 PID Does the status stage use a data1 PID Does the data stage always start with a data1 PID Are all the transactions of the data stage in the same direction Is there a change of direction when entering the status change Is the data packet used in the status stage 0 bytes in length 6 Spec sec 8.5.2 8.5.2 8.5.2 8.5.2 8.5.2 8.5.2 Status yes _4 yes _4 yes _4 yes _4 yes _4 yes _4 7/19/99 no___ no___ no___ no___ no___ no___ Test for robustness Section: Bitstream A compliant bitstream is a set of bits from J,K,0 (nrzi) or 0,1,X(nrz) Name BST 1 BST 2 BST 3 BST 4 BST 5 BST 6 BST 7 BST 8 BST 9 BST 10 Test description Is a single ended NIB 1 of >= 1 bit time ignored by the target Does an agent ignore a truncated (up to 50%) first bit of the sync field without impacting the rest of the bitstream Is the state of the differential receiver ignored during single ended signal state Does the target reject bitstreams of length <1 bit time without impacting future transactions Does the target adjust to the difference in frequency and phase between incoming clock and its internal clock Is a packet with a bit-stuff error rejected by the target Is a bitstream (which is not part of a packet) with bit stuff error ignored by the target Does the target reject packets with bit stuff error at the last bit of the packet Is bit stuffing implemented even if stuffed bit is after the last bit of the packet Can the device handle more than one USB RESET with no intervening packets correctly Status yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ Field A compliant field can be one of: sync PID address endpoint frame number token CRC data data CRC EOP Name FLT 1 FLT 2 FLT 3 FLT 4 FLT 5 FLT 6 FLT 7 - 8 bit field with NZB value 00000001 - listed in Table 8-1 of spec - 7 bit field - 4 bit field - 11 bit field - 5 bit field - 0 to 1023 byte field - 16 bit field - 3 bit field with NIB value 00J Test description Is the sync field recognized as valid even if up to two initial bits of it are corrupted (Actually, only the last 3 bits (JKK) need to be decoded). Is a packet with packet type not listed in Table 8-1 ignored by the target Is a packet with corrupt PID (PID check error) ignored by the target Is a token with bad CRC ignored by the target Is a CRC error on a data packet recognized by the target Does a full speed receiver reject a NIB 0 of duration less than 40 ns as part of an EOP Does a low speed receiver reject a NIB 0 of duration less than 330 ns as part of an EOP N/A Status yes _4 no___ yes _4 yes _4 yes _4 yes _4 yes _4 no___ no___ no___ no___ no___ yes _4 no___ Packet A compliant packet is made up of fields which are formatted as described in sec. 8.4 of spec and can be one of the following: 7 7/19/99 PRE SOF Token data handshake Name PKT 1 PKT 2 PKT 3 PKT 4 PKT 5 PKT 6 PKT 7 PKT 8 PKT 9 - sync PID sync PID timestamp tokenCRC EOP sync PID addr endpt tokenCRC EOP sync PID data.......... data data CRC EOP sync PID EOP Test description Is a token whose address field doesn’t match any address in the device ignored by the device Is a token whose endpoint field doesn’t match any endpoint in the address ignored by the device Is a token which doesn’t match direction of endpoint ignored by the device Is a SETUP token to a unidirectional endpoint ignored by the device Is every endpoint capable of handling 0 length data packet in its assigned direction(s) Does an ISO endpoint use 0 length data packet if fresh frame data is not available Is a packet whose length doesn’t match standard length for packet type rejected by target Does the measurement of packet length take into account the possibility of jitter in the EOP Is a bitstream not constituted according to packet rules described in last section rejected by the target N/A Status yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes __ no_4 see note 2 yes _4 no___ yes _4 no___ yes _4 no___ Transaction A compliant transaction can be one of the following: (host phase in italics; device phase in regular) SOF setup data ack out data ack/nak/stall out data0 in data ack in data0/nak/stall pre setup pre data ack pre out pre data ack/nak/stall pre in data pre ack pre in nak/stall Name TRT 1 TRT 2 TRT 3 TRT 4 TRT 5 TRT 6 TRT 7 TRT 8 Test description Is a packet which doesn’t fit the current phase of a transaction rejected by the target Does the receipt of a token always start a new transaction (and end a pending transaction) Does a target ignore data packet with same PID as previous data packet to the endpoint but successfully complete (ack) the transaction Does a time-out or error in any phase cause the transaction to be terminated Is a transaction always started with a token Is the data toggle implemented independently for each unidirectional endpoint Does the source of ISO data ignore handshake without impacting subsequent transactions Can the target handle consecutive packets in the same direction with >=2 bit times of interpacket gap 8 N/A Status yes _4 no___ yes _4 no___ yes _4 no___ see note 3 yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ yes _4 no___ 7/19/99 Transfer Transfers are data structures used by bi-directional (control endpoints). The transfer is made up of stages which are sets of unidirectional transactions. A compliant transfer can be one of: setup0 out1 out0 out1 ... out0/1 in1 setup0 in1 in0 in1 ... in0/1 out1 setup0 in1 Transactions in italics constitute the data stage ; there may or may not be a data stage between the setup stage and status stage. Suffix of 0 or 1 indicates the data PID used in the transaction Name TFT 1 TFT 2 Test description Does a target receiving an unexpected data PID ignore the data but still successfully complete(ack) the transaction Does the receipt of a non-zero length data packet in the status stage cause the transfer to be terminated with an error indication 9 N/A Status yes _4 no___ yes _4 no___ see note 0 7/19/99 USB Signals and Timing Checklist General Rules: Name EL1 EL2 EL3 EL4 EL5 EL6 EL7 EL8 EL9 EL10 EL11 EL12 EL13 EL14 Test description NA Single-ended receivers recognize voltage below 0.8 V as a logic low? Single-ended receivers recognize voltage above 2.0 V as a logic high? Differential receivers recognize differential voltages of 200 mV between 0.8 and 2.5 volts? Do active data line outputs drive to 2.8 volts with a 15 KΩ load to ground? Do active data line outputs drive to 0.3 volts with a 1.5 KΩ load to 3.6 volts? Capacitance on each data line is a maximum of 20 pF (without cable)? Does the device accept a truncated bit time (down to half of a bit time) as the first bit of the SYNC field? Does the device recognize a single-ended zero of 2.5 µs or greater on its root port as a device reset? Does the device recognize any non-idle state on its root port as a resume signal? Do all downstream ports sink 200 µA ±5% at 3.0V when not driving the bus (15 KΩ resistor to ground present)? Are open downstream ports pulled to ground? Does the device recognize a single-ended zero of 2.5 µs or greater on any of its downstream ports as a disconnect? Does the device recognize a non single-ended zero of 2.5 µs or greater on any of its downstream ports as a connect? Is the pullup at the root port connected to a supply which is controlled logically as an AND of Vbus and device VCC? 10 Status yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ n/a__ yes__ no__ n/a__ yes__ no__ n/a__ yes__ no__ n/a__ yes__ no__ n/a__ 7/19/99 Driver Port Characteristics - Full Speed Ports: This section is N/A__4 4 _. Applicable to any port which can operate at 12 Mb/s, up or downstream. This includes the host, full speed devices and all hub ports, including the root port. EL15 EL16 EL17 EL18 EL19 EL20 EL21 EL22 EL 23 EL 24 EL25 EL26 Is the differential source resistance between 28Ω and 43 Ω? Is the pull-down source resistance between 28Ω and 43 Ω? Are data line rise times are greater than 4.0 ns and less than 20 ns? Are data line fall times are greater than 4.0 ns and less than 20 ns? Are the rise and fall times matched to within 10%? Do the data lines cross over each other between 1.3 and 2.0 volts? Is the bus idle state D+ between 3.0 and 3.6V and D- at ground? Is there a pull-up resistor on the D+ data line of the device’s root port? Does the combination of the device’s pullup resistor and the 15KΩ pulldown resistor upstream yield a voltage which is at least 2.0V when the bus is idle? Does the combination of the device’s pullup resistor and the 15KΩ pulldown resistor upstream yield a voltage which does not exceed 3.6V when the bus is idle? When Vbus is disconnected from the device, does the D+ source no current? When Vbus is present on the device, is the magnitude of the leakage current (device not driving) from the D- data line less than 10 µA for input voltages between 0.0 and 3.3 volts? Driver Port Characteristics - Low Speed Ports: yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ This section is N/A__4 4 __. Applicable to any port which can operate at 1.5 Mb/s, up or downstream. This includes the host, low speed devices and all downstream hub ports. EL 27 EL 28 EL 29 EL 30 EL 31 EL 32 EL 33 EL 34 EL 35 Data line rise times are greater than 75 ns and less than 300 ns? Data line fall times are greater than 75 ns and less than 300 ns? Are the rise and fall times matched to within 20%? Do the data lines cross over each other between 1.3 and 2.0 volts? At bus idle is D- between 3.0 and 3.6V, and is D+ at ground? Does the combination of the device’s pullup resistor and the 15KΩ pulldown resistor upstream yield a voltage which is at least 2.0V when the bus is idle? Does the combination of the device’s pullup resistor and the 15KΩ pulldown resistor upstream yield a voltage which does not exceed 3.6V when the bus is idle? When Vbus is disconnected from the device, does the D- source no current? When Vbus is present on the device, is the magnitude of the leakage current (device not driving) from the D+ data line less than 10 µA for input voltages between 0.0 and 3.3 volts? 11 yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ 7/19/99 Data Source Timings - Full Speed Ports: This section is N/A_4 4 ___. Applicable to a device operating at 12 Mb/s, up or downstream which acts as the source of data. This includes the host, full speed devices and the root hub port when the hub or embedded function is the addressed device. EL 36 EL 37 EL 38 EL 39 EL 40 EL 41 EL 42 EL 43 EL 44 EL 45 Is the transmission data rate between 11.97 and 12.03 Mb/s? Does the high speed device operate correctly with frame lengths between 0.9995ms and 1.0005 ms? Is the differential driver jitter less than ±3.5 ns? Is the differential driver jitter for paired transitions3 less than ±4.0 ns? Is the EOP width between 160 ns and 175 ns at the transmitter? Is the timing skew due to the transition to the EOP on the last differential bit(s) between -2.0 ns and 5.0 ns at the transmitter? Is the receiver data jitter tolerance at least ± 18.5 ns? Is the receiver jitter tolerance for paired transitions3 at least ± 9.0 ns? Does the device accept a single-ended zero of 1 FS bit time as an EOP? Does the device reject as an EOP a single-ended zero of 40 ns or less? Data Source Timings - Low Speed Ports: yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ yes__ no__ This section is N/A_4 4 ___. Applicable to a device operating at 1.5 Mb/s, up or downstream. This includes the host and low speed devices. EL 46 EL 47 EL 48 EL 49 EL 50 EL 51 EL 52 EL 53 EL 54 Is the transmission data rate between 1.4775 and 1.5225 Mb/s? Is the differential driver jitter less than ±95 ns? (n/a for host devices) Is the differential driver jitter for paired transitions3 less than ±150 ns? (n/a for host devices) Is the EOP width between 1.25 µs and 1.5 µs at the transmitter? Is the timing skew due to the transition to the EOP on the last differential bit(s) between -40 ns and 100 ns at the transmitter? Is the receiver data jitter tolerance at least ± 75 ns? (n/a for host devices) Is the receiver jitter tolerance for paired transitions3 at least ± 45 ns? ( n/a for host devices) Does the device accept a single-ended zero of 1 LS bit time as an EOP? Does the device reject as an EOP a single-ended zero of 330 ns or less? yes__ no__ yes__ no__ n/a__ yes__ no__ n/a__ yes__ no__ yes__ no__ yes__ no__ n/a__ yes__ no__ n/a__ yes__ no__ yes__ no__ Suspend And Resume SU 1 SU 2 SU 3 SU 4 SU 5 SU 6 SU 7 Does a USB peripheral enter the suspend state after 3.0 ms of continuous J on its bus If a peripheral is bus powered does its average suspend current remain below 500 µa If a peripheral is bus powered does its peak suspend current remain below 100 ma If a peripheral is low powered does it recognize LS keep alive signaling and remain awake? Does a peripheral start its wake-up if the bus state changes from the J->K or J>SE0 states Is a peripheral fully awake within 10 ms of having received a resume event from upstream? Does a peripheral recognize a K->EOP->J transition as end of resume signaling? 12 yes_4 no__ see note 4 yes__ no__ na_4_ yes__ no__ na_4_ yes_4 no__ na__ yes_4 no__ yes_4 no__ yes_4 no__ 7/19/99 All USB devices must be capable of going into resume upon seeing a continuous idle on the bus for 3.0 ms or more. Similarly, all USB devices must be capable of receiving resume and waking up. USB peripherals may implement remote wake-up as an option. Remote Wake-up SU 8 SU 9 Is the peripheral capable of supporting remote wake-up Does the peripheral drive K signaling upstream for at least 10ms, but not more than 15 ms to initiate a remote wake-up event Does a remote wake-up device wait at least 5.0 ms from when the bus entered the idle state before initiating remote resume signaling? yes_4 no__ na__ yes_4 no__ na__ yes_4 no__ yes_4 no__ yes_4 no__ RST 4 Does a peripheral reject SE0 pulses of less than 2.5 µsec as not being reset? Does a peripheral recognize all SE0 pulses greater than 5.5µs as resets Does a suspended peripheral wake up and recognize reset signaling within 10ms from the start of reset? Does a peripheral respond to a reset by transitioning to the default state? RST 5 RST 6 RST 7 Does a peripheral draw no more than 100 ma during reset? Does a peripheral draw less than 100 ma from upstream after reset is completed? At the end of reset are the peripheral’s D+ and D- floating? SU 10 yes_4 no__ na__ Reset RST 1 RST 2 RST 3 13 yes_4 no__ see note 0 yes_4 no__ yes_4 no__ yes_4 no__ 7/19/99 Notes: 1. All of the items in this checklist have been taken from Chapter 7 of the USB Specification, Rev. 1.0, in particular, Section 7.3. These specifications are explained in Section 7.1. 2. All voltages are referenced from the USB ground of the device being tested. 3. See USB Specification Rev. 1.0, Chapter 7, Section 7.1.11.1 for explanation of paired transitions. Explanations: note 0 This function is implemented by s/w. note 1 In the case of OUT token, the USB channel will respond with NACK if the FIFO is full. It is always assumed that a BD is available to the be used by the CPM to store the data when it is read from the FIFO. note 2 The token will be ignored if a fresh packet is not available. note 3 The packet will be transferred to the s/w. The s/w should ignore it based on the repeated PID. note 4 The 3.0 ms timer is handled by the s/w. The h/w generates an indication when to start the timer and when to stop it. ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ 14 7/19/99 ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ This section should be used to explain any “no” or “n/a” answers or clarify any answers on checklist items above. Please key explanation to item number. 15 7/19/99 Explanations: ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ ___________________________________________________________ This section should be used to explain any “no” or “n/a” answers or clarify any answers on checklist items above. Please key explanation to item number. 16 7/19/99