RENESAS M66290AFP

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Ver.1.0 Oct. 27, 2000
DESCRIPTION
· Data transf er condition selectable f or each
Endpoints (EP1 to EP5)
· Data transf er t y pe
(Bulk, Isochronous and Interrupt)
· Transf er direction (IN/OUT)
· Buf f er size of FIFO (maximum 1024 By tes)
· Double (Toggle) buf f er conf iguration
· Continuous transf er mode
(Buf f ering up to 1 KBy teX2)
· Max packet size
· Supports 4 input clock f requencies
· Input clock : 6/12/24/48 MHz
· Built-in PLL which has an oscillation buf f er
and outputs at 48 MHz
· Supports both 8-bit and 16-bit DMA transf ers
· 16-bit CPU bus interf ace
· 3.3V single power source
· Built-in JTAG
The M66290A is a general purpose USB (Univ ersal Serial
Bus) dev ice controller compatible with the USB
specif ication v ersion 1.1 and corresponds to f ull speed
transf er. Built-in transceiv er circuits meet all transf er ty pe
which is def ined in USB.
M66290A has FIFO of 3k By tes f or data transf er and can
set 6 endpoints (maximum).
Each endpoint can be set programmable of its transf er
condition, so can correspond to each dev ice class transf er
sy stem of USB.
FEATURES
·
·
·
·
USB specif ication 1.1 compliant
Built-in USB transceiv er circuit
Supports Full Speed (12 Mbps) transmission
Supports all f our USB transf er t y pe :
· Control transf er
· Bulk transf er
· Isochronous transf er
· Interrupt transf er
· Built-in FIFO (3 KBy tes) f or Endpoint
· Up to 6 endpoint (EP0 to EP5) selectable
APPLICATION
· Printer , Scanner , DSC , DVC
· PC camera , Multimedia speaker , Terminal adapter etc.
· Support all PC peripheral using Full Speed USB
PIN CONFIGURATION
(TOP VIEW)
DATA BUS
TEST2 INPUT
INTERRUPT
READ STROBE
WRITE STROBE
CHIP SELECT
RESET
DMA REQUEST
DMA ACKNOWLEDGE
D12
D13
D14
D15
TEST2
INT
RD
WR
CS
RST
Dreq
Dack
37
24
38
23
39
22
40
41
42
43
44
45
21
M66290AGP
OR
M66290AFP
20
19
18
17
16
46
15
47
14
48
13
Outline
M66290AGP:48P6Q-A(LQFP)
M66290AFP:48P6X-A(TQFP)
c MITSUBISHI ELECTRIC CORPORATION
1
D1
D0
A6
A5
A4
A3
A2
A1
V CC
GND
Xin
Xout
DATA BUS
ADDRESS BUS
OSCILLAT OR INPUT
OSCILLAT OR OUTPUT
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
V CC
BLOCK DIAGRAM
1 16 35
Xin
14
Xout
13
Clock
Control
(Oscillator/
PLL)
17
to
A6 to 1
22
Vbus
5
T rON
6
4
D-
3
TRST
TCK
T MS
TDI
TDO
TEST1
TEST2
to
D15 to 0
40
CPU
Register
Serial
Interface
Engine
D+
23
Device
Control
Unit
USB
Peripheral
Circuit
45
CS
44
WR
43
RD
68
42
INT
47
Dreq
68
48
Dack
46
RST
USB
Transceiver
Endpoint
Buffer
(3KByte FIFO)
8
9
10
11
12
7
41
2 15 36
GND
BLOCK DESCRIPTIONS
Endpoint Buf f er
This is a FIFO buf f er f or transmit and receiv e
between endpoints.
Except f or EP0 f or control transf er, f iv e endpoints
(EP1 to EP5) can be set.
The M66290A contains USB transceiv er, oscillation
circuit, PLL, serial interf ace engine, endpoint buf f er,
dev ice control unit, and CPU register.
USB Transceiv er
USB Transceiv er is consisted of dif f erential driv er
and dif f erential receiv er.
And is compatible with USB specif ication v ersion 1.1
and corresponds to Full Speed Transf er mode.
CPU Register
This is an interf ace block with CPU.
Serial Interf ace Engine (SIE)
SIE handles protocol lay er as f ollows.
Oscillator/PLL
This block oscillates the internal operation clock
source of 48MHz.
External clock of 6/12/24/48MHz can be input.
Extract a USB 12MHz clock
Serial-Parallel data conv ersion
SYNC detection
NRZI encode and decode
Bit stuf f ing and destuf f ing
CRC generator and checker
USB peripheral circuit
Detect the connection and the shutdown of USB
by the Vbus input.
Connect the Vbus of U SB bus to or the 5V power
supply to Vbus input.
Connect the TrON output to D+ pull-up resistor of
1.5kohm. ON/OFF of the pull-up resistor is controlled
by the register.
Dev ice Control Unit (DCU)
DCU controls the dev ice state sequence, control
transf er sequence, and so on.
2
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
PIN DESCRIPTIONS
Item
Pin name Input/
D15 to D0
Function
Input/ DATA BUS
Output Data bus to access the register from the system
Number of
16
A6 to A1
Input
ADDRESS BUS
Address bus to access the register from the system
6
CS
Input
CHIP SELECT
"L" level enables to communicate with M66290A
1
WR
Input
WRITE STROBE
Input data is written into the register by the positive edge
1
RD
Input
READ STROBE
Register data can be read when "L" level
1
INT
Output
INTERRUPT
"L" level requests interrupt to system
1
Dreq
Output
DMA REQUEST
DMA transfer request to endpoint FIFO
1
Dack
Input
DMA ACKNOWLEDGE
FIFO access by DMA transfer is available in "L" level
1
CPU
interface
DMA
interface
D+
Input/ USB DATA(+)
Output D+ of USB. Connect the external resistor serially.
1
D-
Input/ USB DATA(-)
Output D- of USB. Connect the external resistor serially.
1
USB
interface Vbus
TrON
Input
Vbus INPUT (Built-in pull down resistor)
Connect to the Vbus of USB bus or to the 5V power supply.
Connection or shutdown of the Vbus can be detected.
TrON OUTPUT
Output Connect to the D+ pull-up resistor of 1.5kohm.
ON/OFF control of the pull-up resistor is available.
1
1
TRST
Input
TEST RESET INPUT (Built-in pull up resistor)
Reset input of JTAG. Even if the JTAG is not used, JTAG circuit must be
initialized. Input "L" level to initialize like the RST input.
1
TMS
Input
TEST MODE INPUT (Built-in pull up resistor)
Mode set input to JTAG. If JTAG is not used, keep "H" level or open.
1
JTAG
interface TCK
Input
TEST CLOCK INPUT (Built-in pull down resistor)
Clock input to JTAG. If JTAG is not used, keep "L" level or open.
1
TDI
Input
TEST DATA INPUT (Built-in pull up resistor)
Data input to JTAG. If JTAG is not used, keep "H" level or open.
1
TDO
Output
TEST DATA OUTPUT
Data output from JTAG. If the JTAG is not used, keep open.
1
RST
Input
RESET
"L" level initializes the register or the counter of M66290A.
1
Xin
Xout
OSCILLATO Generate an internal clock.
R INPUT
Input or output of internal clock oscillator. When use as a crystal oscillator, connect a
OSCILLATO crystal between Xin and Xout.
Output
R OUTPUT If an external clock is used, input it to Xin, and Xout must be opened.
Input
Others
1
1
TEST1
Input
TEST1 INPUT (Built-in pull down resistor)
Input for the test. Keep "L" level or open.
1
TEST2
Input
TEST2 INPUT (Built-in pull down resistor)
Input for the test. Keep "L" level or open.
1
VCC
-
Power supply pin
3
GND
-
Ground
3
3
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
USB DATA TRANSFER DESCRIPTIONS
M66290A is a USB dev ice controller correspond to all
the f our ty pes of transf er (control, bulk, isochronous,
and interrupt transf er), which is compatible to USB
specif ication 1.1.
M66290A acts USB f unctions as below automatically .
(1) Bit stuf f ing/destuf f ing
(2) CRC generate/check
(3) NRZI encode/decode
(4) Packet handling
(5) USB address check
(6) Bus error handling
Theref ore, when CPU transact the operations as
f ollows, USB transf er is realized.
(1) Response to the control transf er request
(2) Permission of store and transmission of the
transmit data into the endpoint buf f er.
(Or read of the receiv ed data f rom the endpoint
buf f er)
(3) Stall handling
(4) Suspend/resume handling
Data transmit
When the data of endpoint FIFO, which corresponds to
transmit request by IN token packet, is ready , M66290A
transmit the corresponded data packet to USB bus.
If the ACK packet come f rom the host f or the transmitted
data packet, a transaction completed and the endpoint
FIFO becomes empty and urge CPU to write the next
transmit data by buf f er ready interrupt.
If the transmit data, which correspond to transmit request
by IN token packet, is not exist in the endpoint FIFO,
M66290A transmit NAK packet to host when receiv ed
IN token packet f rom host and occurs interrupt and
request CPU to write transmit data.
When M66290A receiv ed IN token packet again f rom host,
M66290A transmits the data which is written.
If error is not occurred in that transf er, host transmit ACK
packet and if M66290A receiv ed it normally , a transaction
completed.
If U SB protocol error is occurred in the data which is
transmitted v ia USB bus, host does not transmit ACK
packet, so M66290A watch and wait until receiv e IN token
packet, with keeping the data to be transmitted.
Below are the descriptions about the data transf er.
Data receiv e
In data receiv e, there are dif f erences of its f unction
between setup transaction and out transaction.
In setup transaction, when receiv ed dev ice request
f rom host, 8By te request is alway s stored into f our
resistors.
When request data is receiv ed correctly ,sends back
ACK packet to host and at the same time, occurs
interrupt to CPU and urge CPU to read request.
In out transaction, af ter M66290A receiv ed OUT
token packet, host transmits data packet.
If packet of m aximum packet size or short packet
is stored into the endpoint FIFO of M66290A, and
moreov er, error is not occurred in that transf er,
M66290A transmits ACK packet to host and inf orms
CPU that the data was receiv ed by occurring buf f er
ready interrupt.
If U SB protocol error is occurred in the host data
which receiv ed v ia USB bus, or if the endpoint FIFO
is f ull, M66290A does not transmit ACK packet to
host. Host knows that the error occurred because the
ACK packet does not come, and take a step such as
data resend.
4
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
CONTROL REGISTER TABLE
Below is the table of registers of M66290A.
Bit width of all register is 16bits.
In reset item, "H/W" shows the reset status
by external RST input, "S/W" shows reset
status by USBE register, and "USB"
shows the reset status by receiv ing USB reset.
" - " shows that the prev ious status is kept.
Write into reserv ed address is inhibited.
Address
Name
R/W
H/W
S/W
USB
00h
USB Operation Enable Register
R/W
0000h
-
-
02h
Remote Wake-up Register
R/W
0000h
0000h
-
04h
Sequence Bit Clear Register
R/W
0000h
0000h
-
06h
Reserved
08h
USB_Address Register
R
0000h
0000h
0000h
0Ah
IsochronousStatus Register
R/W (note 2)
0000h
0000h
-
0Ch to 0Eh
Reserved
10h
Interrupt Enable Register0
R/W
0000h
0000h
-
12h
Interrupt Enable Register1
R/W
0000h
0000h
-
14h
Interrupt Enable Register2
R/W
0000h
0000h
-
16h
Interrupt Enable Register3
R/W
0000h
0000h
-
18h
Interrupt Status Register0
R/W (note 2)
0000h
0000h
Note 2
1Ah
Interrupt Status Register1
R
0000h
0000h
-
1Ch
Interrupt Status Register2
R/W
0000h
0000h
-
1Eh
Interrupt Status Register3
R/W
0000h
0000h
-
20h
Request Register
R
0000h
-
-
22h
Value Register
R
0000h
-
-
24h
Index Register
R
0000h
-
-
26h
Length Register
R
0000h
-
-
28h
Control Transfer Control Register
R/W
0000h
-
-
2Ah
EP0 Packet Size Register
R/W
0008h
-
-
2Ch
Auto-response Control Register
R/W
0000h
-
-
2Eh
Reserved
30h
EP0_FIFO Selection Register
R/W
0000h
-
-
32h
EP0_FIFO Control Register
R/W (note 2)
0800h
-
-
34h
EP0_FIFO Data Register
R/W
xxxx
-
-
36h
EP0 Continuous transmit Data Length
R/W
0000h
-
-
38h to 3Eh
Reserved
40h
CPU_FIFO Selection Register
R/W
0000h
-
-
42h
CPU_FIFO Control Register
R/W (note 2)
0800h
-
-
44h
CPU_FIFO Data Register
R/W
xxxx
-
-
46h
Reserved
48h
DMA_FIFO Selection Register
R/W
0000h
-
-
4Ah
DMA_FIFO Control Register
R/W (note 2)
0800h
-
-
4Ch
DMA_FIFO Data Register
R/W
xxxx
-
-
4Eh to 5Eh
Reserved
60h
EP1 Configuration Register0
R/W
0000h
-
-
62h
EP1 Configuration Register1
R/W
0040h
-
-
64h
EP2 Configuration Register0
R/W
0000h
-
-
66h
EP2 Configuration Register1
R/W
0040h
-
-
68h
EP3 Configuration Register0
R/W
0000h
-
-
6Ah
EP3 Configuration Register1
R/W
0040h
-
-
6Ch
EP4 Configuration Register0
R/W
0000h
-
-
6Eh
EP4 Configuration Register1
R/W
0040h
-
-
70h
EP5 Configuration Register0
R/W
0000h
-
-
note 1 : Detail description is mentioned later.
note 2 : Some are read only.
5
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Functional and register descriptions
And when use this f unction, dev ice state shif ts to Address
state af ter outputs remote wakeup signal, so it is needed
to set up again the dev ice state to Conf igured state.
Change of set up of dev ice state can be done in S/W
control mode.
Remote wakeup signal is a signal to set USB bus to idle
state af ter output K-state of 10ms length.
If this remote wakeup f unction is set up immediately af ter
detected suspend, USB bus idle state is kept f or 2ms and
then shif ts to K state output. (Because USB bus idle state
must be kept f or 5ms minimum until transmit of remote
wakeup signal, on the other hand af ter detect suspend,
USB idle state is continued f or 3ms)
We explain about Function and register constitution of
M66290A div iding into f our items as f ollows.
(1) Sy stem control
(2) Interrupts
(3) Control transf er/enumeration
(4) Endpoints and FIFO control
(1) System control
CLOCK
Clock of 48MHz is needed f or internal operations
of M66290A.
Built in PLL enables to input external clock of 6/12/
24/48MHz. Selection of it is realized by the XTAL
of "USB Operation Enable Register".
When use external clock of 48MHz, PLL is not
needed, so set to PLL operation disable.
Built in oscillation circuit enables to supply clock
by self oscillation.
To set the "USB Operation Enable Register", it can
be set the dev ice to standby state. Oscillation is
halted (clock input halted) by XCKE, PLL operation
is halted by PLLC, and clock supply to USB block
is halted by SCKE.
To prev ent unstable behav ior by unstable clock,
clock supply to USB block must be obey ed the
process, that is, enables clock input by XCKE, wait
until oscillation stabilized, start PLL by PLLC, wait
until oscillation stabilized (less than 1ms), and start
clock supply to USB block by SCKE.
RESET
S/W reset by the register set (USBE), dif f erent f rom
the hardware reset, keeps the v alue of register of
USB operation enable register, FIFO relational
register, control transf er relational register,endpoint
setting register, and so on.
And in USB reset (when more than 2.5us of SE0 state
is continued on D+, D- terminal), the v alue of register
is kept except f or "Interrupt Status Register 0" and
"USB_Address Register"
As to details of reset state, see each item of register.
Sequence toggle bit clear f unction
In each endpoint of EP0 to EP5, data PID can be reset
independently and also can appoint PID of DATA0.
By this f unction, management of sequence toggle bit
in transf er af ter reset PID, is done by H/W automatically .
Error inf ormation in isochronous transf er
In isochronous transf er there is not retry f unction of
transmit/receiv e, because the handshake f rom receiv er
to transmitter is not returned not to disturb the time
equiv alent data transf er.
M66290A has enough inf ormation f unction which enables
f irmware to manage incorrect transf er in case of transf er
error occurred in isochronous transf er.
Inf ormation which M66290A can inf orm is, ov er run
error, under run error, receiv ed data error (CRC error,
bit stuf f ing error), and f rame number.
Sof tware control mode
In sof tware control mode, it is av ailable to set up (write)
f rom CPU as f ollows, USB_Address register (USB_Addr),
dev ice state register (DVSQ), control transf er stage
register (CTSQ).
Normally , use this mode with OFF.
(1) In case of crystal oscillation
C1
Xin
XTAL
Rf M66290A
D+ pull-up resistor control f unction
To set the register, external TrON output is controlled
and can control the ON/OFF of pull-up resistor
(1.5kohm) on USB D+ line.
Xout
C2
Rd
Place the parts as near the terminal as possible
Remote wakeup f unction
(2) In case of external clock input
When dev ice is in suspended state, outputs remote
wakeup signal and can cancel suspended state to receiv e
resume f rom USB.
Remote wakeup f unction is only ef f ectiv e in Suspended
state in which dev ice state shif ts f rom Conf igured state,
so don't use to other dev ice state.
6
clock input
Xin
M66290A
open
Xout
Figure 1. Xin and Xout connections
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(1-1) USB Operation Enable Register (Address : 00h)
D15
D14
XCKE
PLLC
XTAL[1:0]
Bit
Bit
Name
Name
15
XCKE
Oscillator enable
14
PLLC
PLL control
10
9, 8
D12
D11
D10
SCKE USBPC
D9
D8
D7
D6
D5
D4
D3
D2
Tr_on[1:0]
D1
D0
SCTR
USBE
Reset
Function
W/R
H/W S/W USB
0 : Oscillator disable (clock input disable)
1 : Oscillator enable (clock input enable)
W/R
0
-
-
0 : PLL disable
1 : PLL enable
When use external clock of 48MHz, set to PLL disable.
W/R
0
-
-
Crystal select
00 : 1/1 division (external 48MHz input)
10 : 1/2 division (external 24MHz input)
01 : 1/4 division (external 12MHz input)
11 : 1/8 division (external 6MHz input)
W/R
00
-
-
SCKE
Internal clock
enable
0 : Internal clock (sck) disable
1 : Internal clock (sck) enable
W/R
0
-
-
USBPC
USB transceiver
power control
0 : USB transceiver disable
1 : USB transceiver enable
In suspend state, resume signal can be received even if USB
transceiver disabled.
W/R
0
-
-
X0 : TrON port ="Hi-Z"
01 : TrON port ="L"
11 : TrON port ="H"
This fields selects TrON output state, and it is effective when
external Vbus input is "H" level (5V). If external Vbus input is "L",
these bits can be set but TrON output does not operate.
W/R
00
-
-
13, 12 XTAL[1:0]
11
D13
Tr_on
[1:0]
Tr_on output
control
7 to 2 Reserved
Write/Read "0"
1
SCTR
Software control
mode
0 : Normal Operation
1 : Software Control Mode Operation
W/R
0
-
-
0
USBE
USB module
enable
0 : USB module disable (S/W Reset)
1 : USB module enable
W/R
0
-
-
(1-2) Remote Wake-up Register (Address : 02h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WKUP
Bit
Bit
Name
15 to 1 Reserved
0
WKUP
Function
Name
W/R
Reset
H/W S/W USB
Write/Read "0"
Remote wake-up
When CPU write "1" to WKUP for remote wake-up, M66290A outputs
K-State for 10ms, and return to Bus Idle-State.
(Remote wake-up signal)
This bit returns to "0" automatically after suspend is canceled.
If "1" is written into this bit after detected suspend, bus idle state is kept
for 2ms and after then shifts to K state output.
7
W/R
0
0
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(1-3) Sequence Bit Clear Register (Address : 04h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SQCLR[5:0]
Bit
Bit
Name
Name
15 to 6 Reserved
5 to 0
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
When write "1" into the bit which is correspond to the number
of endpoint, sequence toggle bit of that endpoint is cleared
and appoint the DATA0 by the data PID of next transmission.
Write "1" into the bit after set the response PID of the endpoint, which
SQCLR Sequence toggle bit clears sequence toggle bit, to NAK("00") .
Transfers After the transfer appointed, sequence toggle bit is controlled
[5:0]
clear
by H/W.
In USB reset, Sequence toggle bit of each endpoint is not cleared.
If "0" is written into this bit, flag is not changed.
Read data of this bit is always "0".
W/R
00h
00h
-
(1-4)USB Address Register (Address : 08h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
USB_Addr[6:0]
Bit
Bit
Name
Name
USB_
Addr
[6:0]
W/R
Reset
H/W S/W USB
Write/Read "0"
15 to 7 Reserved
6 to 0
Function
USB_Address
register
USB address which is assigned by host is stored.
After stored the address, transaction is done only to the token packet
which is transmitted to this address.
(If S/W control mode is set, write operation is available)
8
R
00h
00h 00h
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(1-5) Isochronous Status Register (Address : 0Ah)
D15
D14
D13
D12
OVRN CRCE
Bit
15
Bit
Name
OVRN
D11
D10
D9
D8
D7
FMOD
D6
D5
D4
D3
D2
D1
D0
FRNM[10:0]
Reset
Name
Function
W/R
H/W S/W USB
Over run error
In isochronous transfers (OUT/IN), when over-run or under-run is
occurred to the endpoint buffer, this flag is set at the timing of the
receive end of the OUT/IN token packet.
Over run is occurred when delayed to read the received data from
the endpoint buffer, and means that could not received. Over run is
occurred when the direction of transmission is OUT.
Also the received data has CRC or bit stuffing error, this flag is set.
Under run is occurred when delayed to write the transmit data into the
endpoint buffer, and means that could not transmitted. Under-run is
occurred when the direction of transmission is IN.
W/R
0
0
-
W/R
0
0
-
W/R
0
0
-
When a state above is occurred, endpoint buffer notready interrupt is
occurred.
When "0" is written, status flag is cleared.
When "1" is written, flag is not changed.
In isochronous transfers(OUT), if the received data has CRC or
bit stuffing error, this flag is set at the timing of the end of transaction.
14
CRCE
Receive data error
When a state above is occurred, endpoint buffer notready interrupt is
occurred.
When "0" is written, status flag is cleared.
When "1" is written, flag is not changed.
13 to 12 Reserved
Write/Read "0"
Select the renewal timing of the flame number to be stored
to FRNM[10:0].
11
FMOD
Frame number
mode
10 to 0
FRNM
[10:0]
Frame number
0 : Renew the flame number when SOF is received .
1 : In isochronous transfer, renew the flame number at the
timing of the end of transaction.
Stores the flame number.
The timing to renew the stored flame number is selectable by set
FMOD.
9
R
000h 000h
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2) Interrupts
Resume detect interrupt (RESM)
There are eight f actors of interrupt to CPU.
When interrupt occurred, the f actor can be known to
ref er to "Interrupt Status Register 0" and "Interrupt
Status Register 1".
These interrupts can be set of its enable/disable
independently to set "Interrupt Enable Register 0"
and "Interrupt Enable Register 1".
If disable is set, interrupt is not occurred but interrupt
status f lag is set.
Each f actor of interrupt is shown in the table below,
and also describes below the interrupt conditions and
how to deal with the interrupt.
If dev ice state is in suspended state and resume interrupt
enable f lag is set, interrupt occurs when USB bus state
is changed ("J" to "K" or "SE0").
This interrupt can be occurred ev en if the internal
clock(sck) is halted. To clear the status f lag, set the
internal clock(sck) in operation and then write "0". If the
internal clock(sck) is halted, status f lag can not be
cleared.
SOF detect interrupt (SOFR)
Interrupt occurs when detect SOF.
Device state transition interrupt (DVST)
Vbus (connect/shut down) interrupt (VBUS)
M66290A manages the dev ice state by H/W.
It manages Powered, Def ault, Address, Conf igured, and
Suspended state. Dev ice state can be known to ref er to
"Interrupt Status Register 0".
As to dev ice state shif t, see the item of "Dev ice state
shif t" in "(3) Control transf er/emulation" in the latter part.
Dev ice state transition interrupt occurs when dev ice state
shif ted. The number of f actors is f our, that is, USB bus
reset detect, suspend detect, execution of "Set Address",
and execution of "Set Conf iguration".
USB reset is detected when SE0 state ov er 2.5us is
continued on D+, D- terminal.
Suspend is detected when idle state ov er 3ms is
continued on D+, D- terminal.
Interrupt occurs when Vbus input state is changed
(both "L" to "H" and "H" to "L").
To know Vbus input state, conf irm the Vbus bit of
interrupt status register 0. Conf irmation of Vbus bit
must be done af ter enabled internal clock operation.
This interrupt can be occurred ev en if the internal
clock(sck) is halted. To clear the status f lag, enables
the internal clock(sck) in operation and then write "0".
If the internal clock(sck) is halted, status f lag can not
be cleared.
This interrupt is usef ul to detect connect/shut-down of
USB f or prepareration/close of USB transf ers.
Summary of interrupts
Status bit
Name
Abstract of interrupt f actor
Relational status bit
VBUS
Vbus interrupt
(connec/shut-down detect)
Change of the Vbus input
(both "L" to "H" and "H" to "L")
RESM
Resume detect interrupt
Resume signal receiv ed in suspended
SOFR
SOF detect interrupt
Receiv ed SOF
DVST
dev ice state transition
interrupt
Shif t of dev ice state
DVSQ[2:0]
CTRT
Control transf er
stage transition interrupt
Stage shif t of control transf er
CTSQ[2:0]
BEMP
Endpoint buf f er
empty /size-ov er interrupt
In each endpoint, when data transmit of all buf f er
is ended and buf f er is empty , or in OUT transf er,
receiv ed packet which exceeds max packet size.
INTN
Endpoint buf f er not ready
interrupt
When buf f er is in not ready state (SIE cannot read
and write) to IN/OUT token of each endpoint.
INTR
Endpoint buf f er ready
interrupt
When buf f er of each endpoint became ready
(read enable/write enable)
10
Vbus
EPB_EMP_OVR[5:0]
EPB_NRDY [5:0]
EPB_RDY [5:0]
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Each of "Set Address" and "Set Conf iguration" execution
detects the dev ice state shif t by analy zing the dev ice
request in control transf er.
Each of these f our f actors can be set of its interrupt to
enable or disable by setting the corresponded bit of
interrupt enable register 0.
For example by using this interrupt, when USB bus reset
is detected, a step to USB bus is av ailable and when
suspend is detected, a step to shif t dev ice to low power
consumption.
Endpoint buffer not ready interrupt (INTN)
When the buf f er is in not ready state to IN/OUT token
of each endpoint, interrupt occurs at the timing of token
packet receiv e end.
By ref er to EPB_NRDY[5:0] of interrupt status register 1,
it can be known which endpoint occurred the interrupt.
If endpoint is set to isochronous transf er, when ov er-run/
under-run error is occurred, interrupt occurs at the timing
of token packet receiv e end.
And if it is set to isochronous (OUT), if receiv ed data
has
error such as CRC error, interrupt occurs at the timing of
transaction end.
The v ariety of error in isochronous transf er is known to
ref er "Isochronous Status Register".
Control transfer stage transition interrupt (CTRT)
M66290A manages the sequence of control transf er
by H/W.
Each stage of c ontrol transf er, such as setup stage,
data stage, and status stage can be known to ref er to
the "Interrupt Status Register 0".
Control transf er stage transition interrupt is occurred
when the control transf er stage is shif ted.
There are f iv e f actors, that is, setup stage end,
control write transf er stage shif t, control read transf er
stage shif t, control transf er end, and control transf er
sequence error.
Except f or setup stage, Each of these f our f actors can
be set of its interrupt to enable or disable by setting the
corresponded bit of interrupt enable register 0.
As to control transf er sequence error which can be
recognized by H/W, ref er to "Control transf er stage
shif t" in the item of "(3) Control transf er/enumeration"
in the latter part.
Endpoint buffer ready interrupt (INTR)
Interrupt occurs when the buf f er of each endpoint
became ready (read/write is av ailable).
It can be known which endpoint occurred the interrupt
to ref er EPB_RDY [5:0] of interrupt status register 1.
According to the endpoint and its access mode, the
f actor of interrupt is dif f erent as f ollows.
1. In case of EP0
Interrupt occurs when receiv e (OUT) buf f er of endpoint
0 became ready .
If it is set to control write continuous receiv e mode,
when continuous receiv e of 255 by tes ended or when
receiv ed short packet, interrupt occurs.
Interrupt is not occurred ev en if the transmit buf f er
became ready .
Endpoint buffer empty/size-over interrupt (BEMP)
Interrupt f actor is dif f erent by transf er direction of
endpoint.
2. In case of EP1 to EP5, when CPU access
Interrupt occurs when the buf f er of each endpoint
became ready .
1. In case of transf er direction is IN
In each endpoint, interrupt occurs when transmission
ended of all data which is stored in the buf f er.
By this interrupt, when endpoint is set to double buf f er,
end of data transmission of all data of the buf f er can
be known.
And also can know the end of data transmission of
control read transf er in endpoint 0 (EP0).
3. In case of EP1 to EP5, when DMA access
If the transf er direction is set to OUT, interrupt occurs
when receiv ed short data packet and then ended DMA
transf er.
Interrupt is not occurred if the transf er direction is set
to IN.
2. In case of transf er direction is OUT
In each endpoint, interrupt occurs in data packet
receiv e when receiv ed packet which exceeds the
maximum packet size.
By ref er to EPB_EMP_OVR[5:0] of interrupt status
register, it can be known which endpoint occurred the
interrupt.
11
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Figure 2. shows the examples of interrupt output timing
(1) Endpoint buf f er ready interrupt (ex.OUT transaction)
OUT token packet
USB
SYNC PID
Data packet
Addr Endp CRC EOP
SYNC PID
DATA
Hand shake packet (ACK)
CRC EOP
SYNC PID
EOP
Buf f er becomes ready (read enable)
and interrupt occurs
INT output
(2) Endpoint buf f er not ready interrupt (ex.OUT transaction)
OUT token packet
USB
SYNC PID
Data packet
Addr Endp CRC EOP
SYNC PID
DATA
Hand shake packet (NAK)
CRC EOP
SYNC PID
Buf f er is in not ready (receiv e disable)
and interrupt occurs
INT output
(3) Endpoint buf f er not ready interrupt (ex.IN transaction)
IN token packet
USB
SYNC PID
Hand shake packet (NAK)
Addr Endp CRC EOP
INT output
SYNC PID
EOP
Buf f er is in not ready (transmit disable)
and interrupt occurs
Figure 2. Examples of interrupt output timing
12
EOP
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-1) Interrupt Enable Register 0 (Address : 10h)
D15
D14
D13
D12
VBSE RSME SOFE
DVSE
D11
D10
D9
D8
D7
CTRE BEMPE INTNE INTRE URST
D6
D5
SADR SCFG
D4
SUSP
D3
D2
WDST RDST
D1
D0
CMPL SERR
Reset
Bit
Bit
Name
Name
15
VBSE
Vbus interrupt
enable
0 : Disable
1 : Enable
W/R
0
0
-
14
RSME
Resume interrupt
enable
0 : Disable
1 : Enable
W/R
0
0
-
13
SOFE
SOF interrupt
enable
0 : Disable
1 : Enable
W/R
0
0
-
12
DVSE
Device state
interrupt enable
0 : Disable
1 : Enable
W/R
0
0
-
11
CTRE
Control transfer
interrupt enable
0 : Disable
1 : Enable
W/R
0
0
-
10
BEMPE
Endpoint5-0 buffer
empty/size error
interrupt enable
0 : Disable
1 : Enable
W/R
0
0
-
9
INTNE
Endpoint5-0 buffer
not ready
interrupt enable
0 : Disable
1 : Enable
W/R
0
0
-
8
INTRE
Endpoint5-0 buffer
ready
interrupt enable
0 : Disable
1 : Enable
W/R
0
0
-
7
URST
USB reset detect
If this bit is "1", then the DVST flag is set when detected USB reset.
W/R
0
0
-
6
SADR
Set Address
execute
If this bit is "1", then the DVST flag is set after executed SetAddress.
W/R
0
0
-
5
SCFG
Set Configration
execute
If this bit is "1", then the DVST flag is set after executed SetConfigration.
W/R
0
0
-
4
SUSP
Suspend
detect
If this bit is "1", then the DVST flag is set when detected suspend.
W/R
0
0
-
3
WDST
Control write
transfer status
stage
If this bit is "1", then the CTRT flag is set when shifted to status stage
in control write transfer.
W/R
0
0
-
2
RDST
Control read
transfer status
stage
If this bit is "1", then the CTRT flag is set when shifted to status stage
in control read transfer.
W/R
0
0
-
1
CMPL
Control transfer
complete
If this bit is "1", then the CTRT flag is set when control transfer
completed (when the status stage completed normally).
W/R
0
0
-
0
SERR
Control transfer
sequence error
If this bit is "1" then the CTRT flag is set when error
occurred in the sequence of control transfer.
W/R
0
0
-
Function
13
W/R
H/W S/W USB
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-2) Interrupt Enable Register 1(Address : 12h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_RE[5:0]
Bit
Bit
Name
Name
Function
15 to 6 Reserved
5 to 0
EPB_RE
[5:0]
W/R
Reset
H/W S/W USB
Write/Read "0"
Endpoint5-0 buffer
ready
interrupt enable
0 : Disable
1 : Enable
The number of endpoint is correspond to each bit one by one.
W/R
00h
00h
-
(2-3) Interrupt Enable Register 2 (Address : 14h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_NRE[5:0]
Bit
Bit
Name
Name
Function
15 to 6 Reserved
5 to 0
EPB_NRE
[5:0]
W/R
Reset
H/W S/W USB
Write/Read "0"
Endpoint5-0 buffer
not ready
interrupt enable
0 : Disable
1 : Enable
The number of endpoint is correspond to each bit one by one.
W/R
00h
00h
-
(2-4) Interrupt Enable Register 3 (Address : 16h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_EMPE[5:0]
Bit
Bit
Name
Name
15 to 6 Reserved
5 to 0
EPB_
EMPE
[5:0]
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
Endpoint5-0 buffer
empty/size error
interrupt enable
0 : Disable
1 : Enable
The number of endpoint is correspond to each bit one by one.
14
W/R
00h
00h
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-5) Interrupt Status Register 0 (Address : 18h)
D15
D14
VBUS RESM
Bit
15
14
13
12
11
10
Bit
Name
D13
D12
D11
D10
D9
D8
D7
SOFR
DVST
CTRT
BEMP
INTN
INTR
Vbus
Name
D6
D5
D4
DVSQ[2:0]
D3
D2
VALID
Function
D1
D0
CTSQ[2:0]
W/R
Reset
H/W S/W USB
Vbus interrupt
This bit changes to "1" when Vbus input changed both "0" to "1" and
"1" to "0".
As to the Vbus input state, confirm to see the bit of Vbus input port.
This bit is set even if the internal clock (sck) is in halt state.
If "0" is written after enabled internal clock as operation, status flag is
cleared. But if internal clock is in halt state, flag is not cleared.
If "1" is written, flag is not changed.
W/R
0
0
-
RESM
Resume detect
interrupt
This bit changes to "1" when USB bus state changed("J" to "K" or "SE0")
under the condition that resume interrupt enable flag is set.
This bit is set even if the internal clock (sck) is in halt state.
If "0" is written after enabled internal clock as operation, status flag is
cleared. But if internal clock is in halt state, flag is not cleared.
If "1" is written, flag is not changed.
W/R
0
0
-
SOFR
SOF detect
interrupt
This bit changes to "1" when detected SOF.
If "0" is written, status flag is cleared.
If "1" is written, flag is not changed.
W/R
0
0
-
This bit changes to "1" when device state shifted.
There are four factors, that is, USB reset detect, suspend detect,
"Set Address" execution, and "Set Configuration" execution.
Device state
These four factors can be masked by the corresponded bit of
transition interrupt
"Interrupt Enable Register0" .
If "0" is written, status flag is cleared.
If "1" is written, flag is not changed.
W/R
0
0
1
W/R
0
0
-
R
0
0
-
VBUS
DVST
CTRT
BEMP
Control transfer
stage transition
interrupt
This bit changes to "1" when the stage of control transfer is shifted.
There are five factors, that is, setup stage end, control write transfer
status stage shift, control read transfer status stage shift, control transfer
end, and control transfer sequence error.
Four factors, except for setup stage end, can be masked by the
corresponded bit of the "Interrupt Enable Register0".
If "0" is written, status flag is cleared.
If "1" is written, flag is not changed.
The factor is different by the direction of the transfer of each endpoint.
In each endpoint, this bit changes to "1" when the transmission of all
stored data is completed (direction:IN) and when received the packet
Endpoint5-0 buffer which is exceeded to maximum packet size (direction:OUT).
The endpoint which occurs the interrupt can be checked to see the
empty/size error
interrupt
EPB_EMP_OVR[5:0].
This flag is cleared to clear the status flag of EPB_EMP_OVR[5:0].
15
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
9
Bit
Name
INTN
Name
Function
This bit changes to "1" at the timing of token packet receive end when
buffer respond NAK, of its not ready state, to IN/OUT token of each
Endpoint5-0 buffer endpoint.
not ready
The endpoint which occurred the interrupt is checked to see
interrupt enable
EPB_NRDY[5:0].
This flag is cleared to clear the status flag of EPB_NRDY[5:0].
W/R
Reset
H/W S/W USB
R
0
0
-
R
0
0
-
R
Ext.
Ext. Ext.
R
000
000 001
W/R
0
0
-
R
000
000
-
This bit changes to "1" when the buffer of each endpoint
became ready (read/write enable).
8
7
INTR
Vbus
Endpoint5-0 buffer
ready
interrupt enable
Vbus input port
The endpoint which occurred the interrupt is checked to see
EPB_RDY[5:0].
This flag is cleared to clear the status flag of
EPB_RDY[5:0].
Input data from external Vbus is stored.
0: Vbus input port is "L"
1: Vbus input port is "H"
External Vbus input data is latched by the positive edge of internal clock.
Refer to this bit after enabled internal clock operation.
000: Powered State
001: Default State
010: Address State
011: Configured State
1xx: Suspended State
6-4
3
2-0
DVSQ
[2:0]
Device state
VALID
Setup packet
detect
CTSQ
[2:0]
Control transfer
Stage
Device state can be known.
As to the device state shift, refer to Fig.5 in the later part.
When detect USB reset, this becomes 001: Default state automatically.
When detect suspend, this becomes 1xx: Suspended state automatically.
Whatever the automatic response mode is, this becomes 010: Address
state after executed Set_Address request, and becomes 011: Configured
state after executed Set_Configuration request.
(Write operation is available when S/W control mode is set)
This bit changes to "1" when received setup packet.
This flag does not the factor of interrupt.
When "0" is written, status flag is cleared .
When "1" is written, flag is not changed .
000 : Idle or Setup stage
001 : Control read transfer data stage
010 : Control read transfer status stage
011 : Control write transfer data stage
100 : Control write transfer status stage
101 : Control write no data transfer status stage
110 : Control transfer sequence error
111 : Not assigned
Can be seen the stage of control transfer.
As to the stage shift of control transfer, refer to Fig.5 in the later part.
(Write operation is available when S/W control mode is set)
16
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-6) Interrupt Status Register 1 (Address : 1Ah)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_RDY[5:0]
Bit
Bit
Name
Name
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
15 to 6 Reserved
When buffer becomes ready (read/write enabled) to each endpoint,
the bit which corresponds to the number of endpoint changes to "1".
The factor of the interrupt is different by the transfer condition of each
endpoint.
1. As to EP0
This bit changes to "1" when receive buffer(OUT) became ready
(read enabled) in control write transfer.
If it is set to control write continuous receive mode or completed
receiving of the data of 255Bytes or received short data packet,
this bit changes to "1".
This bit is not changed even if the transmission buffer(IN) became
ready (write enabled) in control read transfer.
The ready state of the transmission buffer(IN) can be known by the
buffer empty interrupt.
5 to 0
EPB_RDY
[5:0]
Endpoint5-0 buffer
ready
interrupt
2. As to EP1 to EP5, when CPU access
This bit changes to "1" when each buffer of each endpoint became
ready(read/write enabled).
This bit also changes to "1" when set the direction of the transfer to IN
in initialization.
R
3. As to EP1 to EP5, when DAM access
If the direction of the transfer is set to OUT, this bit changes to "1"
when received short data packet and then completed DMA transfer
of received data.
In this case, clear is only available to write the BCLR command.
This bit is not changed if the direction of transfer is set to IN.
Clearance of this flag is different by the transfer direction of endpoint.
1. If the transfer direction is OUT
After set the number of the object endpoint to the "FIFO Selection
Register", write BCLR command or read all data of the buffer, then
flag is cleared.
(When DMA access, clearance is only available to write BCLR
command)
2. If the direction is IN
After set the number of the object endpoint to the "FIFO Selection
Register", write IVAL command or write data into the buffer of maximum
packet size (buffer size, if in continuous transmission mode ), then
flag is cleared.
17
00h 00h
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-7) Interrupt Status Register 2 (Address : 1Ch)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_NRDY[5:0]
Bit
Bit
Name
Name
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
15 to 6 Reserved
To IN/OUT token of each endpoint, if the set of response PID is not
NAK("00") and if buffer is in not ready state (receive/transmit disabled),
the bit which corresponds to the number of endpoint changes to "1".
(If the endpoint is control transfer or bulk transfer or interrupt transfer,
NAK response is executed)
5 to 0
EPB_
NRDY
[5:0]
Endpoint5-0 buffer
not ready
interrupt
If the endpoint is set to isochronous transfer, M66290A does not execute
NAK response, but when over-run or under-run of endpoint buffer
occurred, this bit changes to "1" at the timing of token packet receive end.
If it is set to isochronous (OUT), and if received data has error such as
CRC, this bit changes to "1" at the timing of transaction end.
When "0" is written, status flag is cleared.
When "1" is written, flag is not changed.
18
W/R
00h 00h
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-8) Interrupt Status Register 3 (Address : 1Eh)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPB_EMP_OVR[5:0]
Bit
Bit
Name
Name
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
15 to 6 Reserved
When factors below are occurred to each endpoint, the bit which
corresponds to the number of endpoint, changes to "1".
5 to 0
EPB_
EMP_
OVR
[5:0]
Endpoint5-0 buffer
empty/size error
interrupt
1. If the transfer direction is IN
In each endpoint, when transmission completed of all data which stored
in buffer, c
By this interrupt, if endpoint is set to double buffer, it can be known that
transmission of all data of buffer is completed.
And also by this interrupt, it can be known that transmission of EP0 is
completed.
2. If the direction is OUT
In each endpoint, when received data which exceeds the maximum
packet size in data packet receive, the bit which corresponds to the
number of endpoint changes to "1".
When "0" is written, status flag is cleared.
When "1" is written, status flag is not cleared.
19
W/R
00h 00h
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3) Control transfer / Enumeration
If it is control read transf er, data stage is IN transaction
and CPU prepares f or data transmit (write into endpoint
FIFO) at the timing of interrupt in setup stage.
M66290A is equipped with control transf er continuous
transmit and receiv e f unction. Af ter ended data stage,
it proceeds to status stage.
In control transf er, there are setup stage, data stage,
and status stage.
M66290A manages stage and inf orm CPU the stage
shif t by interrupt. CPU do stage transact of control
transf er according to the interrupt f actor.
Setup stage
Status stage
In setup stage, 8By tes request (setup data) of setup
transaction data packet which transf erred f rom host
is stored into f our registers automatically (Request,
Value, Index, and Length register).
Except f or dev ice state shif t request (Set Address and
Set Conf iguration) which can cope with by the automatic
response control f unction, analy sis (decode) and
execution of contents of request must be done by CPU.
By executing the request, it proceeds to data stage or
to status stage.
Status stage executes receiv e/transmit of N ull data
(data length 0), in both control write and control read
transf er. Receiv e/transmit of N ull data is possible to
set control transf er complete enable bit (CCPL) af ter
ended setup stage.
Control transf er complete enable bit is reset when
receiv ed setup packet.
Control transf er executes data transf er using EP0.
To both control read and control write, buf f er size of
EP0 can be set by a unit of 64By tes by "Control
Transf er Control Register".
Access to EP0_FIFO data register must be done by
CPU access. DMA transf er can not be set.
Data stage
Data stage executes IN transaction or OUT transaction
according to the contents of request. If it is control
write transf er, data stage is OUT transaction and CPU
prepares f or data receiv e at the timing of interrupt in
setup stage and reads the receiv ed data f rom endpoint
FIFO when data receiv e ended.
Figure 3. shows the abstract of enumeration
operations.
M66290A
USB bus connect
Dev ice f irmware
Clock ON
Initializing
Tr ON
Vbus interrupt
Dev ice state
Idle
(Powered)
Full speed
dev ice recognition
USB reset
Def ault
state
USB reset receiv e
DVST interrupt
USB request
(Control transf er)
Get xx command
CTRT interrupt
USB request
Set Address
CTRT/DVST interrupt
(Automatic response av ailable)
Set response data
USB request
Get xx command
CTRT interrupt
USB request
Set Conf iguration
CTRT/DVST interrupt
(Automatic response av ailable)
USB request
Address
state
Set response data
Set xx command
CTRT interrupt
Conf igured
state
Read receiv ed data
Figure 3. Abstract of enumeration operations
20
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Auto-response control function
which extend plural of transaction.
If continuous transf er mode is set, it can transf er the
transmit which data length is set to "EP0 Continuous
Transmit Data Length Register", without
occurring interrupt.
Control read buf f er can be set up to 256By tes at a unit
of 64By tes. Control write buf f er can receiv e continuously
up to 255By tes, so secure the area of 256By tes.
M66290A has auto-response f unction to dev ice
state transition request (Set Address and Set
Conf iguration)in control transf er.
By the set of "Auto-response Control Register",
auto-response mode to Set Address and to
Set Conf iguration can be set indiv idually .
If the auto-response mode is set, dev ice state
transition request can be ended without occurring
interrupt.
Abstract of control transfer operations
Continuous transfer function
Figure 4. shows examples of abstraction of control
transf er operations.
M66290A has continuous transf er f unction to
transmit/receiv e continuously of requested data
Transf er direction of packet :
Host to M66290A
M66290A to Host
(1) Continuous receive mode (control write transfer)
Setup
stage
Data
stage
INT1:
CTRT interrupt (setup stage completion)
Read EP0 request and conf irm the contents of request.
Data packet
ACK
OUT token
Data packet
NAK
OUT token
Data packet
NAK
By receiv ing SETUP token packet, response PID of
EP0 is set to NAK automatically .
OUT token
Data packet
ACK
By the set of response PID to BUF (buf f er control),
data receiv e starts.
OUT token
Data packet
ACK
OUT token
Data packet
ACK
IN token
Status
stage
INT1
Setup token
INT2
INT2:
CTRT interrupt (control write transf er status stage shif t)
Conf irm the number of by te of receiv ed data and read
the receiv ed data.
NAK
IN token
NAK
IN token
Null data packet
By the set of CCPL, transmit the Null data.
Interrupt, which is occurred by control write transf er
status stage shif t and by control transf er completion is
dif f erent by interrupt enable setting.
ACK
(2) Continuous transmit mode (control read transfer)
Setup
stage
Data
stage
Status
stage
Setup token
Data packet
IN token
NAK
IN token
NAK
IN token
NAK
ACK
INT1
INT1:
CTRT interrupt (setup stage completion)
Read EP0 request and conf irm the contents of request.
By receiv ing SETUP token packet, response PID of
EP0 is set to NAK automatically .
IN token
Data packet
ACK
IN token
Data packet
ACK
IN token
Data packet
ACK
OUT token
Null data packet
ACK
Executes transmit data write which is requested,
set transmit data length, set response PID to BUF
(buf f er control), and data transmit is started.
By the set of CCPL, ACK handshake is executed
when receiv ed Null data.
Interrupt which is occurred by control read transf er
status stage shif t and by control transf er completion is
dif f erent by interrupt enable setting.
Figure 4. Examples of abstract of control transf er operations
21
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Device state transition
other state and to Set_Address request which Dev iceAddess
is not equal to 01h to 7Fh, auto-response is not executed.
M66290A manages dev ice state by H/W.
To Set_Conf iguration request, auto-response is executed
It manages Powered, Def ault, Address, Conf igured,
to Set_Conf iguration request (Conf igurationValue is not equal
and Suspended state of U SB dev ice state.
to 0) which dev ice state is in Address state and to
To Set_Address and Set_Conf iguration request in
Set_Conf iguration request (Conf igurationValue=0) which dev ice
auto-response mode, transf er can be completed
state is in Conf igured state.
without occurring interrupt to CPU.
To Set_Address request, auto-response is executed to To other state and to Set_Conf iguration request which is
dif f erent of its Conf igurationValue f rom the v alue abov e,
Set_Address request (Dev iceAddess=01h
to 7Fh) which dev ice state is in Def ault state, and to auto-response is not executed.
Suspend detection (DVST)
Powered
state
Suspended
state
(DVSQ="000")
(DVSQ="100")
Resume detection (RESM)
USB reset detection (DVST)
USB reset detection (DVST)
Suspend detection (DVST)
Def ault
state
Suspended
state
(DVSQ="001")
(DVSQ="101")
Resume detection (RESM)
Set Address execution (DVST)
(Dev iceAddress=01h to 7Fh)
*Can be set to auto-response
Suspend detection (DVST)
Def ault
state
Suspended
state
(DVSQ="010")
(DVSQ="110")
Resume detection (RESM)
Set Conf iguration execution (DVST)
(Conf iguration Value is not equal to 0)
*Can be set to auto-response
Set Conf iguration execution (DVST)
(Conf iguration Value is not equal to 0)
*Can be set to auto-response
Suspend detection (DVST)
Def ault
state
Suspended
state
(DVSQ="011")
(DVSQ="111")
Resume detection (RESM)
Figure 5. Device state shift
22
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Control transfer stage transition
3. OUT token packet receiv e in control read data stage.
M66290A manages control transf er sequence by H/W.
There are setup stage, data stage, and status stage in
control transf er stage, as shown in f igure 6. And when
stage shif ts, CTRT interrupt occurs.
There are f iv e f actors in CTRT interrupt, that is, setup
stage end, control write transf er status stage shif t,
control read transf er status stage shif t, control transf er
end, and control transf er sequence error. And there are
sev en errors as f ollows in control transf er sequence
error which can be detected by H/W.
If H/W detected control transf er sequence error,
response PID is set to STALL("1x") automatically .
(OUT token packet receiv e which did not do data transf er
once to IN token packet in data stage).
4. IN token packet receiv e in control read status stage.
5. Data packet receiv e except f or Null data in control
read status stage.
6. OUT token packet receiv e in control write no data
status stage.
7. Data receiv e which exceeds maximum packet size.
In control write data stage, it can not be recognized as
sequence error when receiv ed data packet which exceeds
request wLength v alue.
1. IN token packet receiv e in control write data stage
(In token packet receiv e which did not do ACK
handshake once to OUT token packet in data stage)
2. OUT token packet receiv e in control write status stage
Control
transf er
sequence
error
Receiv e
setup packet
Receiv e short packet
or Receiv e IN token
ACK transmit
(Setup stage complete)
Setup
stage
Error detected
Control
write
data
stage
(Control write transfer
status stage transition)
ACK receiv e
Control
write
status
stage
Transmit short packet
or Receiv e OUT token
ACK transmit
(Setup stage complete)
Control
read
data
stage
(Control read transfer
status stage transition)
(Control transfer
complete)
ACK receiv e
Control
read
status
stage
(Control transfer
complete)
ACK receiv e
ACK transmit
Control
write
no data
status
stage
(Setup stage complete)
Figure 6. Stage shift of control transfer
23
(Control transfer
complete)
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3-1) Request Register (Address : 20h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
bRequest[7:0]
Bit
Bit
Name
Name
15 to 8
bRequest
[7:0]
Request register
bmRequest
Type
[7:0]
RequestType
register
7 to 0
D4
D3
D2
D1
D0
bmRequestType[7:0]
Function
W/R
Reset
H/W S/W USB
This fields provides bRequest of the last setup packet received.
R
00h
00h
-
This fields provides bmRequest of the last setup packet received.
R
00h
00h
-
(3-2) Value Register (Address : 22h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
wValue[15:0]
Bit
Bit
Name
Name
15 to 0
wValue
[15:0]
Value register
Function
W/R
This fields provides wValue of the last setup packet received.
R
Reset
H/W S/W USB
0000h
-
-
(3-3) Index Register (Address : 24h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
wIndex[15:0]
Bit
Bit
Name
Name
15 to 0
wIndex
[15:0]
Index register
Function
W/R
This fields provides wIndex of the last setup packet received.
R
Reset
H/W S/W USB
0000h
-
-
(3-4) Length Register (Address : 26h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
wLength
Bit
Bit
Name
Name
15 to 0
wLength
[15:0]
Length register
Function
This fields provides wLength of the last setup packet received.
24
W/R
R
Reset
H/W S/W USB
0000h
-
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3-5) Control Transfer Control Register (Address : 28h)
D15
D14
D13
D12
CTRR
D11
D10
D9
D8
Ctr_Rd_Buf_Nmb[5:0]
Bit
Bit
Name
15
CTRR
14
Reserved
D7
D6
D5
D4
CTRW
Name
D3
D2
D1
D0
Ctr_Wr_Buf_Nmb[5:0]
Function
W/R
Control read
Control read transfer continuous transmit mode is set
transfer continuous
when "1" is written in this bit.
transmit mode
Reset
H/W S/W USB
W/R
0
-
-
W/R
00h
-
-
W/R
0
-
-
W/R
00h
-
-
Write/Read "0"
Appoint the start number of the buffer which is used in control read
transfer by a unit of 64bytes.
Ctr_Rd_
Control read buffer
13 to 8 Buf_Nmb
start number
[5:0]
7
CTRW
6
Reserved
5 to 0
The buffer is available from #00h to #2Fh.
When control read continuous transmit mode is set, it can
transmit continuously up to 255Bytes, so keep the area of the
buffer of 256Bytes (4 blocks).
Control write
When "1" is written, control write transfer continuous receive mode
transfer continuous
is set.
receive mode
Write/Read "0"
Appoint the start number of the buffer which is used in control write
transfer by a unit of 64bytes.
Ctr_Wr_
Control write buffer The buffer is available from #00h to #2Fh.
Buf_Nmb
When control write continuous receive mode is set, it can receive
start number
[5:0]
continuously up to 255bytes, so keep the area of buffer of 256bytes
(4 blocks).
(3-6) EP0 Packet Size Register (Address : 2Ah)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EP0_MXPS[6:0]
Bit
Bit
Name
Name
15 to 7 Reserved
6 to 0
EP0_MXPS
[6:0]
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
Max Packet size
Set the maximum value of data (byte) which transmit or receive in a
packet transfer.
Set the value of wMaxPacketSize in request.
This bit must be set after set the response PID to NAK("00").
25
W/R
08h
-
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3-7) Auto-response Control Register (Address : 2Ch)
D15
Bit
D14
D13
Bit
Name
D12
D11
0
ASCN
ASTD
D9
D8
D7
Name
D6
D5
D4
D3
Function
D2
W/R
D1
D0
ASCN
ATAD
Reset
H/W S/W USB
Write/Read "0"
15 to 2 Reserved
1
D10
Set_Configuration
Auto-response
mode
When "1" is written into this bit, auto-response mode of
Set_Configuration request is set.
To the Set_Configuration request in auto-response mode,
transfer can be completed without occurring interrupt to CPU.
(Set of CCPL is not needed)
Auto-response is done to the Set_Configuration request
(ConfigurationValue is not equal to 0) in Address device state
and to the Set_Configuration request (ConfigurationValue is equal to 0)
in Configured state.
To the other state and to the Set_Configuration request which
ConfigurationVale is different from the value above, auto-response
is not done.
W/R
0
-
-
Set_Address
Auto-response
mode
When "1" is written into this bit, automatic response mode of
Set_Address request is set.
To the Set_Address request in automatic response mode,
transfer can be completed without occurring the interrupt to
CPU. (Set of CCPL is not needed)
Automatic response is done to the Set_Address request (DeviceAddress
is equal to 01h to 7Fh) which device state is Default state.
To the other state and to the Set_Address request which DeviceAddress
is not equal to 01h to 7Fh, automatic response is not done.
W/R
0
-
-
(3-8) EP0_FIFO Selection Register (Address : 30h)
D15
D14
D13
D12
D11
RCNT
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Octl
Bit
Bit
Name
Name
15
RCNT
Read count mode
14 to 11 Reserved
10
Octl
9-1
Reserved
0
ISEL
ISEL
Function
If this bit is "1", every time when read EP0_FIFO register,the value of
ODLN register is counted down.
W/R
Reset
H/W S/W USB
W/R
0
-
-
W/R
0
-
-
W/R
0
-
-
Write/Read "0"
FIFO access
8 bit mode
If this bit is set to "1", data register of FIFO turns to 8-bit mode and
lower 8 bit[7:0] becomes enable when access the "FIFO Data Register"
of endpoint.
When transmit data of odd number byte, data must be written in 8-bit
mode.
When read in 8-bit mode, set to 8-bit mode before data receive.
Write/Read "0"
Buffer select
0 : Control write (OUT) buffer select
1 : Control read (IN) buffer select
26
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3-9) EP0_FIFO Control Register (Address : 32h)
D15
D14
D13
D12
D11
D10
EP0_PID[1:0]
IVAL
BCLR
E0req
CCPL
Bit
15 to 14
13
12
11
Bit
Name
EP0_PID
[1:0]
IVAL
BCLR
E0req
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ODLN[7:0]
Name
Function
W/R
Reset
H/W S/W USB
Response PID
Setting the response PID.
00 : NAK Whatever the buffer state is,do NAK handshake.
01 : BUF Response PID is selected by the state of buffer
and sequence toggle bit status.
(One of ACK, NAK, and DATA0/DATA1)
1x : STALL Do STALL handshake
1. When received Setup packet, turns to "00"(=NAK) automatically.
2. When received request (Set_Address, etc.) which is set to
automatic response, turns to "01"(=ACK) automatically after
completed the Setup transaction.
3. If sequence error occurred in control transfer,or received data
in control write transfer which exceed maximum packet size,
this turns to "1x"(=STALL) automatically.
W/R
00
-
-
In buffer status
If the control read buffer is selected, this becomes IN buffer
effective state flag.
When set to "1", it becomes to transmit data set state (SIE read enabled).
If data is written which exceeds to the maximum byte of maximum
packet size (MXPS), this bit is set to "1".
When short packet transmit, set this bit to "1" after wrote transmit data.
If the IVAL="1" and BCLR="1" is written at the same time,
IN buffer effective state flag is set.
(This is effective to transmit 0 length data)
If the control readout) buffer is selected, it becomes OUT buffer
effective state status.
Status "1" shows that there is data which can be read.
This bit shows the effective value when E0req bit is "0".
If "1" is written, it is not changed.
If "0" is written, flag is not changed.
W/R
0
-
-
Buffer clear
If "1" is written into this bit When the selected endpoint is set to IN, IN
buffer effective state flag and the data (byte) which is written are cleared.
If IVAL="1" and BCLR="1" is written at the same time, data is cleared
but IN buffer effective state flag is set.(This is effective to transmit 0
length data)
When "1" is written into this bit, if the selected endpoint is set to OUT,
OUT buffer effective state flag is cleared and read data is also cleared.
When "0" is written, this bit is not changed.
W/R
0
-
-
R
1
-
-
EP0_FIFO ready
If this bit is "0", access to EP0_FIFO data register is enabled.
And when this bit is "0", IVAL and ODLN bit shows the effective value.
EP0_FIFO data register, when read or write, needs cycle time of
200ns (min).
(Continuous access at 5MHz is available)
27
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
10
Bit
Name
CCPL
Name
Control transfer
complete enable
7 to 0
To write "1" into this register, status stage of control transfer can be
completed.
If this bit is "1" and response PID is BUF("01"), Null data is transmitted
in control write transfer, and do response ACK in control read transfer
when received NULL data.
If this bit is "0", do response NAK in status stage.
This flag is reset to "0" when received setup packet.
Reset
H/W S/W USB
W/R
0
-
-
R
00h
-
-
Write/Read "0"
9 to 8 Reserved
ODLN
[7:0]
W/R
Function
Control write
receive
data length
Received data length(byte) can be read from this register.
If RCNT mode is set, every time when read EP0_FIFO data register,
it is counted down by -1(8-bit mode) or by -2(16-bit mode).
This bit shows effective value when E0req bit is "0".
(3-10) EP0_FIFO Data Register (Address : 34h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EP0_FIFO[15:0]
Bit
15 to 0
Bit
Name
EP0_FIFO
[15:0]
Name
EP0_FIFO data
Function
W/R
When read, this becomes to receive data FIFO register.
If it is set to 8-bit mode, lower 8 bit[7:0] is valid.
When write, this becomes to transmit data FIFO register.
If it is set to 8-bit mode, lower 8 bit[7:0] is valid.
Both for read and write, cycle time of 200ns (min) is needed.
(Continuous access at 5MHz is available)
Read when IN buffer is selected or write when OUT buffer is
selected is inhibited.
W/R
Reset
H/W S/W USB
xxxx
-
-
(3-11) EP0 Continuous transmit Data Length (Address : 36h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDLN[7:0]
Bit
Bit
Name
14-8
Reserved
7 to 0
SDLN
[7:0]
Function
Name
W/R
Reset
H/W S/W USB
Write/Read "0"
Set the control read continuous transmit data length (byte).
It can be set up to FFh (255bytes).
Control read
In control read continuous transmit mode, write FIFO data (transmit data)
continuous transmit
after set this register.
data length
This is available in control read continuous transmit mode.
28
W/R
00h
-
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4) Endpoint and FIFO control
To use with double buf f er constitution, 1kBy tes x2
maximum of buf f ering is realized.
Continuous receiv e mode can receiv e data packet
continuously up to the buf f er size which is set, or until
receiv es short packet. If the data to be receiv ed is data
packet of m ax packet size, it can receiv e continuously
up to the buf f er size without occurring interrupt to CPU,
and if the data is data packet (max packet size) which is
less than buf f er size, interrupt to CPU is not occurred.
In bulk transf er, when set max packet size as 64By tes,
buf f er size as 1024By tes, and FIFO constitution as
double buf f er, when receiv ed data of m ax packet size
as 16 times (1024By tes), it became buf f er redried
enable) and urge to CPU by interrupt to read receiv ed
data. When receiv ed short packet, ends the continuous
receiv e and buf f er became redried enable).
Continuous transmit mode can transmit data packet
continuously up to buf f er size which is set. Short packet
transmit can be done to set IVAL f lag. And it is needed
to set IVAL f lag to transmit a multiple data of m aximum
packet size which is less than buf f er size.
By set Null data transmit addition mode, when write a
multiple data of max packet size into buf f er and
transmit, Null data can be transmitted automatically
af ter the last packet is transmitted .
Except f or EP0 f or control transf er, M66290A can set
f iv e endpoints as EP1 to EP5.
Each of these f iv e endpoints (EP1 to EP5) can be set to
bulk, interrupt, and isochronous transf er. And y et,
another constitution can conf igurated independently .
Below are the constitutions to be realized.
Built-in FIFO f or endpoint buf f er is 3kBy tes totally of its
memory c apacity . This FIFO of 3kBy tes can div ided
into each endpoint of EP0 to EP5 and to each endpoint,
can assign up to 1024By tes (max) by a unit of 64By tes.
Buf f er size of each endpoint must be set to ov er the
capacity which is set in maximum buf f er size.
In the buf f er size, which is set, by tes of m aximum
packet size is used f or v alid. (If set the buf f er size to
128By tes to the endpoint which maximum packet size
is set to 64By tes, 64By tes are v alid)
We show setting examples to each of these buf f er of
EP0 to EP5 below, and next explain about continuous
transmit and receiv e f unction, FIFO control, DMA
transf er, and double buf f er.
Continuous transfer function
Continuous transf er f unction is to transmit/receiv e data
which extend plural transaction without occurring interrupt
to CPU.
For EP1 to EP5, this f unction is ef f ectiv e when transf er
ty pe is bulk transf er.
In each endpoint, when continuous transf er mode is set,
it can transf er data up to the buf f er size which is set to
the endpoint without occurring interrupt to CPU.
Examples of endpoint FIFO setting
FIFO
number
Memory
address
Endpoint setting
00h to
03h
000h to
0FFh
EP0:Control write transfer
Buffer size:256Bytes
Control write continuous receive
mode(CTRW)
FIFO area:256Bytes(4 blocks)
04h to
07h
100h to
1FFh
EP0:Control read transfer
Buffer size:256Bytes
Control read continuous transmit
mode(CTRR)
FIFO area:256Bytes(4 blocks)
08h
200h to
23Fh
EP2:Interrupt transfer(IN)
Buffer size:64Bytes
FIFO area:64Bytes(1 block)
09h
240h to
27Fh
EP4:Interrupt transfer(OUT)
Buffer size:64Bytes
FIFO area:64Bytes(1 block)
0Ah to
0Bh
280h to
2FFh
EP3:Bulk transfer(IN)
Buffer size:64Bytes
Double buffer constitution(DBLB)
FIFO area:128Bytes(2 blocks)
0Ch to
0Fh
300h to
3FFh
Not used:256Bytes(4 blocks)
10h to
2Fh
400h to
BFFh
EP1:Bulk transfer(OUT)
Buffer size:1024Bytes
Double buffer constitution(DBLB)
Continuous receive mode(RWMD)
FIFO area:2kBytes(32 blocks)
Construction of endpoint (EP1 to EP5) FIFO
Register
Transfer type
EPi_TYP[1:0]
EP1 to EP5
Can be set to Bulk,
Interrupt, isochronous
transfer.
Transfer direction
EPi_DIR
Can be set to IN/OUT
Double buffer
(Toggle buffer)
EPi_DBLB
Can be set
EPi_RWMD
Can be set
(Effective in bulk transfer)
EPi_Buf_siz[3:0]
Can be set
(Up to 1024bytes by
a unit of 64bytes)
Response PID
EPi_PID[1:0]
Can be set to
NAK, STALL, and
BUF(buffer control).
DMA transfer
EPi_DMAE
Can be set
Receive data
read and abandon
mode
EPi_ACLR
Can be set
Max packet size
EPi_MXPS[9:0]
Can be set
( 0 to 1023bytes)
Continuous
transmit/receive
Buffer size
29
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
DMA transfer
FIFO control
Access to endpoint buf f er of EP0 to EP5 is done by
three FIFO data registers. One is only f or EP0 and
Others are common to EP1 to EP5. Common data
registers are div ided into two, because accessing
is dif f erent, that is f or CPU access and f or DMA
transf er. Which endpoint of EP1 to EP5 to be
accessed can be selected to set each FIFO
selection register.
Endpoint
Accessing
EP0
CPU access
EP1 to EP5
Register name
EP0_FIFO
data register
CPU_FIFO
CPU access data register
DMA transf er DMA_FIFO
data register
Each of three FIFO registers has f unctions as
f ollows. And these f unctions can be used to set
"Each FIFO Selection/Control Register".
Short packet transmission f unction
To endpoint of EP1 to EP5, 16bits width or 8bit width of
DMA
transf er is av ailable.
Each endpoint of EP1 to EP5 can be set to CPU access
mode or DMA access mode by set of "EPx Conf iguration
Register 1" mentioned later.
DMA transf er is realized to hand shake with external DMAC
and Dreq, Dack signal. Dreq is asserted when endpoint
buf f er, which is set to DMA transf er mode, became ready .
The means of Buf f er ready state is, if the endpoint
transf er
direction is set to Out (reciv e data f rom host) buf f er ready
means that in read enable state, if the endpoint transf er
direction is set to IN(transmit data to host) buf f er ready
means that in write enable state. Setting the transf er
direction can be done by "EPi Conf iguration Register 0" to
each endpoint.
When Dack comes f rom external DMAC af ter asserted
Dreq, Dreq is negated.
In DMA transf er, Dack is dealt equiv alently with CS signal
and DMA_FIFO address appointment.
Appoint read or write operation by RD or WR signal.
This DMA transf er can be used only f or single transf er,
which
transf ers one word (16bit or 8bit) by one time Dreq start.
(IVAL : IN buf f er status bit)
Transmit/receiv e buf f er clear f unction
(BCLR : Buf f er clear bit)
Null data (data length 0) transmit f unction
(IVAL & BCLR)
Data length (8/16 bit) set f unction
(Octl : Register 8bit mode bit)
Receiv ed data length count down f unction
In DMA transf er, as same as the CPU access, occurs
endpoint buf f er not ready interrupt and endpoint buf f er
empty interrupt according to endpoint buf f er state. But as
to endpoint buf f er ready interrupt, it is not same as the
CPU access as f ollows.
(RCNT : Read count mode bit)
*: There is none f or DMA transf er
Access to CPU_FIFO data register when interrupt
occurred, to know the endpoint which requested
access, access the "Interrupt Status Register 0/1"
and by checking the interrupt status f lag and know
the endpoint which requested access, and then set
endpoint to be accessed by "CPU_FIFO Selection
Register".
If there is no change of endpoint setting, it is not
needed to set again the CPU access endpoint
appointment bit.
Data transfer procedure
Data which is set to endpoint FIFO, is sent to USB
bus by LSB f irst. When store the receiv ed data
f rom USB bus to endpoint FIFO, it is as the same
as abov e.
1
Time scale
In DMA transf er, endpoint buf f er ready interrupt is not
occurred if the transf er direction is IN.
If the transf er direction is OUT, interrupt is occurred when
receiv ed short data packet and ended data transf er of all
data which receiv ed in DMA transf er.
Occurring of endpoint buf f er ready interrupt and to ref er
DMA_DTLN, it can be known that short data packet was
receiv ed.
DMA_DTLN shows the number of by te of short data
packet,
or in the continuous receiv e mode it shows the number of
by te
of receiv ed data bef ore short data packet receiv e.
16
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14D15
(Data send procedure to USB bus)
30
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Double buffer operations
The endpoint FIFO of EP1 to EP5 can be
set to double buffer constitution.
So a double of transfer data of its buffer size, which
is set, can be stored.
(1) Receiv ing
Below are the receiv e status examples
of the endpoint which is set to double buf f er.
Endpoint buffer status
CPU bus side
Buf f er2
USB side
IN
"Data1" receiv e start
Buf f er1
data1
receiving data
"Data1" receiv e end
"Data2" receiv e start
Buf f er2
When data receiv e ended, the buf f er
is set to Ready state (read enable)
and occurs INTR interrupt
Continuous receiv ing is av ailable
bef ore data read.
Buf f er1
data1
data receive
available
IN
data receive completed
data read available
Buf f er2
data2
Buf f er1
data1
receiving data
IN
"Data1" read start
Bef ore "Data1" read end
"Data2" receiv e end
"Data1" read end
In OUT token receiv e to this
endpoint, M66290A occurs
INTN interrupt and do NAK
handshake.
Buf f er2
data2
Buf f er1
receiving data
reading data
Buf f er2
data2
Buf f er1
data1
data1
data receive completed
data receive impossible
It becomes receiv e enable
af ter read of data1 ended.
And occurs INTR interrupt
because the buf f er is ready .
Buf f er1
data receive enable
M66290A Occurs INTR interrupt
because the buf f er is ready .
Buf f er1
data3
Figure 7. Double buf f er activ ities-1
31
reading data
data read available
data read available
Buf f er2
data2
receiving data
data
OUT
Buf f er2
data2
data receive available
IN
"Data3" receiv e start
OUT
Buf f er2
data2
Buf f er1
Af ter "Data1" read end
"Data2" receiv e end
data read available
data read available
: Data exists in buf f er
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2) Transmitting
Below are the transmit status examples
of the endpoint which is set to double buf f er.
Endpoint buffer status
CPU bus side
Buf f er2
USB side
In token receiv e
Can not transmit because the
transmit buf f er is in NotReady .
Request CPU to prepare transmit
data by INTN interrupt
Buf f er1
data transmit impossible
Buf f er1
Buf f er2
data1
"Data1" write start
data transmit impossible
"Data1" write end
"Data1" transmit start
"Data2" write start
End of data write of m aximum packet
size or to set(short packet transmit)
IVAL f lag, it becomes transmit data
set status, and transmit becomes enable.
And occurs INTR interrupt because
the buf f er is in Ready (write enable).
Before "Data1" transmit end
"Data2" write end
"Data1" transmit end
Af ter "Data1" transmit end
"Data2" write end
Buf f er2
data1
writing data
Buf f er2
data1
data write available
Buf f er1
data2
transmitting data
writing data
Buf f er2
End of data write of maximum packet
OUT
size or to set (short packet transmit)
data1
IVAL flag, it becomes transmit data
transmitting data
set status, and transmit becomes enable.
Buf f er1
data2
When data transmit ended,
it occurs INTR interrupt
because the buf f er is in
Ready .
When data transmit ended, it occurs
INTR interrupt because the buf f er
is in Ready .
Buf f er1
data2
data transmit avalable
Buf f er1
data2
data transmit avalable
32
data write completed
data writeimpossible
data write avalable
data write avalable
Buf f er2
data3
data2
Figure 8. Double buf f er activ ities-2
IN
Buf f er2
data transmit avalable
data
IN
Buf f er2
Buf f er1
"Data3" write start
IN
Buf f er1
data transmit available
OUT
Data write is av ailable during
data transmitting.
data write available
writing data
: Data exists in buf f er
IN
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4-1) CPU_FIFO Selection Register (Address : 40h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
RCNT
D2
D1
D0
CPU_EP[3:0]
Bit
Bit
Name
Name
15
RCNT
Read count mode
Function
W/R
If this bit is "1", every time when read CPU_FIFO register,
CPU_DTLN register value is counted down.
W/R
Reset
H/W S/W USB
0
-
-
-
-
Write/Read "0"
14 to 4 Reserved
Appoint the CPU access endpoint.
"0001"=EP1,"0010"=EP2,"0011"=EP3,
"0100"=EP4,"0101"=EP5
EP0 can not be appointed.
3 to 0
CPU_EP
[3:0]
CPU access
endpoint
Don't change the setting in writing (IN) or in reading (OUT).
Change of the setting of the endpoint of direction IN must be
done after confirmed that IVAL="0" and Creq="0", or IVAL="1"
and Creq="1".
Change of the setting of the endpoint of direction OUT must
be done after confirmed that IVAL="1" and Creq="0", or
IVAL="0" and Creq="1".
W/R 0000
(4-2) CPU_FIFO Control Register (Address : 42h)
D15
Bit
D14
Bit
Name
D13
D12
D11
IVAL
BCLR
Creq
Name
15, 14 Reserved
13
IVAL
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CPU_DTLN[10:0]
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
IN buffer status
If the selected endpoint is set to IN, this becomes IN buffer
effective state flag.
When set to "1", it becomes transmit data set state.
(SIE is available to read)
When the data (byte) which exceeds to the maximum packet size
(MXPS) is written, this bit is set to "1".
In short packet transmit, set this bit to "1" after wrote the transmit data.
If IVAL="1" and BCLR="1" is written at the same time, the
effective state flag is set.
(This is effective to transmit 0 length data)
If the selected endpoint is set to OUT, it becomes to
OUT buffer effective state status.
Status "1" shows that there is data which is available to read.
When Creq bit is "0", this bit shows effective value.
This bit is not changed when "1" is written.
Flag is not changed when "0" is written.
33
W/R
0
-
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit
Name
Name
Function
W/R
Reset
H/W S/W USB
If the selected endpoint is set to IN, when "1" is written into
this bit, the IN buffer effective state flag and the data (byte)
which is written are cleared.
If IVAL="1" and BCLR="1" is written at the same time, data
is cleared but the IN buffer effective state flag is set.
(This is effective to transmit 0 length data)
12
BCLR
Buffer clear
If the selected endpoint is set to OUT, when "1" is written into
this bit, the OUT buffer effective state flag and the read data (byte)
are cleared.
W/R
0
-
-
R
1
-
-
R
000h
-
-
If it is set to double buffer, the state of write/read enable buffer
for CPU is cleared.
To set the EPi_ACLR, USB bus buffer is cleared.
This bit is not changed when "0" is written.
If this bit is "0", access to CPU_FIFO data register is available.
11
10 to 0
Creq
CPU_DTL
N[10:0]
CPU_FIFO ready
CPU_FIFO
receive data
length
And if this bit is "0", the bit of IVAL and CPU_DTLN bit shows the
effective value.
When read or write to CPU_FIFO register, 200ns (min) of cycle
time is needed. (Continuous access at 5MHz is available)
If the access end point is changed, 200ns (min) of recovery
time is needed.
When read this register, receive data length (byte) appears.
When RCNT mode is set, every time when read CPU_FIFO
register, it is counted down by -1 (8-bit mode) or by -2 (16-bit mode).
If RCNT mode is not set, this register turns to 000h after all of
received data is read.
This bit shows effective value when Creq bit is "0".
34
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4-3) CPU_FIFO Data Register (Address : 44h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CPU_FIFO[15:0]
Bit
Name
Bit
15 to 0
Name
Function
CPU_FIFO
CPU_FIFO data
[15:0]
W/R
If the selected endpoint is set to OUT, this becomes to
receive data FIFO register.
If the selected endpoint is set to IN, this becomes to
transmit data FIFO register.
If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid.
When read or write, 200ns (min) of cycle time is needed.
(Continuous access at 5MHz is available)
Read operation when direction IN is appointed or write operation
when direction OUT is appointed, write operation is inhibited.
W/R
Reset
H/W S/W USB
xxxx
-
-
(4-4) DMA_FIFO Selection Register (Address : 48h)
D15
D14
D13
D12
D11
D10
MODE
Bit
15
Bit
Name
D7
D6
D5
D4
D3
MODE
DMAEN
DMA_EP
[3:0]
D2
D1
D0
DMA_EP[3:0]
Reset
Name
Function
W/R
DMA operation
mode
Set the operation mode of DMA transfer.
0 : High speed transfer mode
1 : One word transfer mode
In high speed transfer mode, when endpoint buffer is in read/write enable
in the state that DMA transfer enable, Dreq is asserted.
In one word transfer mode, when endpoint buffer is in read/write enable
in the state that DMA transfer enable and Dack="H", Dreq is asserted.
In both mode, Dreq detects Dack="L" and is negated.
W/R
0
-
-
W/R
0
-
-
-
-
H/W S/W USB
Write/Read "0"
DMA transfer
enable
7 to 4 Reserved
3 to 0
D8
DMAEN
14 to 9 Reserved
8
D9
If this bit is "1", endpoint buffer which is appointed by DMA_EP[3:0]
is enable to write or when read is enable, Dreq is asserted.
If "0" is written in DMA transferring, DMA transfer is forced to end.
Write/Read "0"
DMA transfer
endpoint
Appoint the endpoint for DMA transfer.
"0001"=EP1,"0010"=EP2,"0011"=EP3,
"0100"=EP4,"0101"=EP5
EP0 can not be appointed.
Don't change the setting during write (IN) or read (OUT).
Change of the setting of the endpoint of direction IN must
be done after confirmed that IVAL="0" and Dreq="0", or
IVAL="1" and Dreq="1".
Change of the setting of the endpoint of direction OUT must
be done after confirmed that IVAL="0" and Dreq="1".
35
W/R 0000
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4-5) DMA_FIFO Control Register (Address : 4Ah)
D15
Bit
D14
Bit
Name
D13
D12
D11
IVAL
BCLR
Dreq
Name
15, 14 Reserved
13
IVAL
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMA_DTLN[10:0]
Function
W/R
Reset
H/W S/W USB
Write/Read "0"
IN buffer status
If the selected endpoint is set to IN, this becomes IN buffer
effective state flag.
When set to "1", it becomes transmit data set state.
(SIE is available to read)
When the data (byte) which exceeds to the maximum packet size
(MXPS) is written, this bit is set to "1".
In short packet transmit, set this bit to "1" after wrote
the transmit data.
If IVAL="1" and BCLR="1" is written at the same time, the
IN buffer effective state flag is set to "1".
(This is effective to transmit 0 length data)
W/R
0
-
-
W/R
0
-
-
If the selected endpoint is set to OUT, it becomes to
OUT buffer effective state status.
Status "1" shows that there is data which is available to read.
When Creq bit is "0", the value of this bit is effective.
This bit is not changed when "1" is written.
Flag is not changed when "0" is written.
If "1" is written into this bit when the selected endpoint is
set to IN, IN buffer effective state flag and the data (byte)
which is written are cleared.
If the IVAL="1" and BCLR="1" is written at the same time,
the data is cleared but the IN buffer effective state flag
is set.(This is effective to transmit 0 length data)
12
BCLR
Buffer clear
If "1" is written into this bit when the selected endpoint is
set to OUT, OUT buffer effective state flag and the read data
(byte) are cleared.
If it is set to double buffer, the state of buffer which can
be read or write for CPU bus is cleared.
To set the EPi_ACLR, USB bus buffer is cleared.
This bit is not changed when "0" is written.
36
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Bit
Bit
Name
11
Dreq
10 to 0
DMA_DT
LN[10:0]
Name
Function
DMA_FIFO
ready
DMA_FIFO
receive data
length
W/R
Reset
H/W S/W USB
If this bit is "0", then access is available to DMA_FIFO register.
And if this bit is "0", then the bit of IVAL and DMA_DTLN is valid.
This bit is used as DMA request signal (Dreq).
R
1
-
-
When read this register, receive data length (byte) is appears.
This bit is valid when Dreq bit is "0".
R
000h
-
-
(4-6) DMA_FIFO Data Register (Address : 4Ch)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMA_FIFO[15:0]
Bit
15 to 0
Bit
Name
DMA_FI
FO[15:0]
Name
DMA_FIFO data
Function
If the selected endpoint is set to OUT, this becomes to receive data
FIFO register.
If the selected endpoint is set to IN, this becomes to transmit data
FIFO register.
If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] are valid.
Read operation when the endpoint appointed direction IN, or
write operation when the endpoint appointed direction OUT, is inhibited.
37
W/R
W/R
Reset
H/W S/W USB
xxxx
-
-
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4-7) EPi Configuration Register 0 ( i=1 to 5)
(Address : EP1=60h, EP2=64h, EP3=68h, EP4=6Ch, EP5=70h)
D15
D14
D13
D12
EPi_TYP[1:0]
DIR
ITMD
D11
D10
D9
EPi_Buf_siz[3:0]
D8
D7
D6
D5
D4
DBLB RWMD
D3
D2
D1
D0
EPi_Buf_Nmb[5:0]
The EPi configuration register 0 must be set in a state of response PID is NAK("00").
Bit
15 to 14
13
Bit
Name
EPi_TYP
[1:0]
EPi_DIR
Name
Transfer type
Transfer direction
12
EPi_ITMD
Interrupt toggle
mode
11 to 8
EPi_Buf_
siz[3:0]
Buffer size
7
6
5 to 0
EPi_DBLB Double buffer mode
EPi_
RWMD
Continuous
transfer mode
(only for Bulk
transfer)
EPi_Buf_
Buffer start number
Nmb[5:0]
Function
W/R
Reset
H/W S/W USB
To set the transfer type of endpoint.
00 : not Configured
01 : bulk transfer
10 : interrupt transfer
11 : isochronous transfer
W/R
00
-
-
To set the transfer direction of endpoint
0 : OUT (receive data from host)
1 : IN (transmit data to host)
When changed the state of transfer direction, clear (EPi_ACLR)
the endpoint buffer.
W/R
0
-
-
To set the sequence toggle bit mode of interrupt transfer.
0 : Alternation data toggle bit mode
(Only toggled when transfer completed with no problem)
1 : Continuous toggle bit mode
(Whatever the hand shake exists or the types are, it toggles
every time when data packet is transmitted )
This is effective when endpoint is set to interrupt(IN) transfer.
W/R
0
-
-
Set endpoint buffer size at a unit of 64Bytes.
"0000"=64Bytes, "0001"=128Bytes, ...., "1110"=960Bytes,
"1111"=1024Bytes
W/R 0000
-
-
Set the constitution of endpoint buffer.
0 : Single buffer mode
1 : Double buffer mode
In double buffer mode, double of the buffer size is taken as the endpoint
buffer.
W/R
0
-
-
If "1" is written into this bit, continuous transfer mode of endpoint is set.
When the direction of endpoint is set to OUT, then it is set to continuous
receive mode. And when the direction of endpoint is set to IN, then it is
set to continuous transmit mode.
Continuous receive mode can receive data packet up to the buffer size
which is set, or can receive continuously before receives short packet.
Continuous transmit mode can transmit data packet up to the buffer size
which is set, and transmission of short packet can be done by set the
IVAL flag.
In data packet (max packet size) receive which is less than buffer
size, interrupt to CPU does not occur.
Continuous transfer mode is effective only in bulk transfer.
W/R
0
-
-
Appoint the first number of the buffer of a unit of 64Bytes.
Buffer exists from #00h to #2Fh.
Buffer size(double of the buffer size in double buffer mode), which is
appointed from the first, is secured for endpoint buffer.
Set that plural of endpoint do not occupy the same buffer area.
W/R
00h
-
-
38
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4-8) EPi Configuration Register 1 ( i=1 to 5 )
(Address : EP1=62h, EP2=66h, EP3=6Ah, EP4=6Eh, EP5=72h)
D15
D14
EPi_PID[1:0]
D13
D12
DMAMD NULMD
D11
D10
ACLR
Octl
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EPi_MXPS[9:0]
The EPi configuration register 1 must be set in a state of response PID is NAK("00").
Bit
15, 14
13
12
11
Bit
Name
EPi_
PID
[1:0]
Name
Response PID
Function
Set response PID.
00 : NAK Whatever the buffer state is, do NAK handshake.
01 : BUF Response PID is selected according to the state of buffer
and sequence toggle bit. (In bulk/interrupt transfer, one of
ACK, NAK, DATA0, and DATA1)
1x : STALL Do STALL handshake.
If the transfer direction of selected endpoint is OUT, when received
data which exceeded maximum packet size (MXPS), it becomes
"1x" (=STALL) automatically.
EPi_
ACLR
Null data
addition
transmit mode
OUT buffer
automatic
clear mode
10
EPi_Octl
FIFO access
8 bit mode
9 to 0
EPi_
MXPS
[9:0]
Max Packet size
Reset
H/W S/W USB
W/R
00
-
-
W/R
0
-
-
W/R
0
-
-
When the selected endpoint is set to OUT and if this bit is set to "1",
OUT buffer effective flag and read data (number of byte) is cleared.
In this state(OUT buffer does not become effective state), SIE side
writes data from host into OUT buffer but CPU side does not read.
When set this bit to "1", whatever the transfer direction is, endpoint
buffer (all buffer of single/double buffer) are cleared.
When clear the endpoint buffer, set this bit to "1" and then set again to "0".
W/R
0
-
-
When this bit is set to "1", FIFO data register becomes 8-bit mode and
when accessed "FIFO Data Register" of endpoint, lower 8bit[7:0]
becomes effective.
When transmit odd number of byte, it is needed to write in 8-bit mode.
When read in 8-bit mode, set to 8-bit mode before data receive.
W/R
0
-
-
Set the maximum data size (Byte) to transmit/receive in one packet
transfer.
Set the value of wMaxPacketSize in request.
W/R 040h
-
-
Set the access mode to endpoint buffer.
EPi_
DMA transfer mode 0 : CPU access mode
DMAMD
1 : DMA transfer mode
EPi_
NULMD
W/R
To set this bit as "1", Null data addition transmit mode is set .
In the endpoint which is set to continuous transmit mode, when
write a multiple data of maximum packet size into buffer and transmit,
Null data is transmitted automatically after transmitted the last packet.
This setting is effective when continuous transmit mode is set.
39
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Unit
VCC
Supply voltage
-0.3 to +4.2
V
VI
Input voltage
-0.3 to VCC+0.3
V
VO
Output voltage
-0.3 to VCC+0.3
V
IO
Output current
±20
mA
Pd
Power dissipation
400
mW
T stg
Storage temperature
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS
Limits
Symbol
Unit
Parameter
Min.
Typ.
Max.
3.0
3.3
3.6
VCC
Supply voltage
GND
Supply voltage
VI
Input voltage
0
VCC
V
VI(Vbus)
Input voltage ( Only for Vbus Input )
0
5.25
V
VO
Output voltage
0
VCC
V
T opr
Operating temperature
0
+70
C
Normal input
500
ns
Schmidt trigger input
5
ms
tr, tf
V
0
+25
V
Input rise, fall time
40
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Condition
Unit
Min.
VIH
"H" input voltage
Typ.
Max.
VCC = 3.6V
2.52
3.6
V
VCC = 3.0V
0
0.9
V
1.4
2.4
V
0.5
1.65
V
Xin
VIL
"L" input voltage
VT+
Threshold voltage in positive direction
VCC = 3.3V
Note 1
VT-
Threshold voltage in negative direction
VOH
"H" output voltage
IOH = -50uA
Xout
VOL
"L" output voltage
VOH
"H" output voltage
"L" output voltage
VOH
"H" output voltage
IOH = -2mA
"L" output voltage
IIH
"H" input current
0.4
2.6
V
V
VCC = 3.0V
IOL = 2mA
IOH = -4mA
Note 3
VOL
V
IOL = 50uA
Note 2
VOL
2.6
VCC = 3.0V
0.4
2.6
V
V
VCC = 3.0V
IOL = 4mA
0.4
V
VI = VCC
10
uA
VI = GND
-10
uA
VO = VCC
10
uA
VO = GND
-10
uA
VCC = 3.6V
IIL
"L" input current
IOZH
"H" output current in off status
D15-0
,TDO
VCC = 3.6V
IOZL
"L" output current in off status
R dv
Pull down resistance
Note 4
100
kΩ
R dt
Pull down resistance
Note 5
50
kΩ
Ru
Pull up resistance
Note 6
50
kΩ
ICC(A)
Average supply current in operation
mode
ICC(S)
Supply current in static mode
f(Xin)=48MHz,VCC = 3.6V
USB transmit state
40
55
mA
Oscillator disable,PLL disable,
USB transceiver enable,
TrON=H/L output
VI=Vcc or GND fixed,Vcc = 3.6V
2
4
mA
Oscillator disable,PLL disable,
USB transceiver disable,
TrON=H/L output
VI=Vcc or GND fixed,Vcc = 3.6V
Suspend state
30
200
uA
Oscillator disable,PLL disable,
USB transceiver disable,
TrON=H/L output
VI=Vcc or GND fixed,Vcc = 3.6V
H/W reset state
10
100
uA
Notes 1: All input and bidirection pins except for Xin (except for USB buffer)
2: INT,Dreq,TDO output pins
3: D15-0 input /output pins
4: Vbus input pins
5: TEST1,TEST2,TCK input pins
6: TRST,TMS,TDI input pins
41
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
ELECTRICAL CHARACTERISTICS (USB)
(1) DC CHARACTERISTICS
Limits
Symbol
Parameter
Unit
Test condition
Min.
| (D+)-(D-) |
Ty p.
Max.
VDI
Differential Input Sensitivity
0.2
VCM
Differential Common Mode Range
0.8
2.5
V
VSE
Single Ended Receiver Threshold
0.8
2.0
V
VOL
"L" Output voltage
0.3
V
V
RL of 1.5KΩ to 3.6V
VCC = 3.0V
VOH
"H" Output voltage
IOZL
"L" output current in off status
RL of 15KΩ to GND
2.8
3.6
V
VO =0V
-10
10
mA
VO =3.6V
-10
10
mA
VO =0V
4
7
15
Ω
VO =3.3V
4
7
15
Ω
VCC = 3.6V
IOZH
"H" output current in off status
R o(Pch)
Output resistance
VCC = 3.3V
R o(Nch)
Output resistance
(2) AC CHARACTERISTICS
Limits
Symbol
Parameter
Test condition
Unit
Min.
Ty p.
Max.
tr
Rise transition time
10% to 90% of the data signal
C L=50pF
4
20
ns
tf
Fall transition time
10% to 90% of the data signal
C L=50pF
4
20
ns
TRFM
Rise/fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
C L=50pF
1.3
2.0
V
42
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
SWITCHING CHARACTERISTICS
Test condition
Limits
Symbol
Parameter
ta(A)
Address access time
30
ns
ta(CTRL)
Control access time
30
ns
tv(CTRL)
Data valid time after control
0
ten(CTRL)
Data output enable time after control
0
20
ns
tdis(CTRL)
Data output disable time after control
0
20
ns
td(Dack-
Dreq disable propagation time
60
ns
td(WR-INT )
INT disable propagation time
60
ns
twh(INT )
INT "H" pulse width
320
ns
twh(Dreq)
Dreq "H" pulse width
60
ns
td(CTRLDreq)
Dreq output enable time after control
60
ns
td(DackhDreq)
Dreq output enable time after Dack
20
ns
td(TCKTDOV)
TDO output enable time after TCK
30
ns
td(TCKTDOX)
TDO output disable time after TCK
30
ns
Min.
Typ.
Max.
Unit
ns
CL=50pF
TIMING REQUIREMENTS
Test condition
Limits
Symbol
Parameter
tsu(A)
Address setup time
30
ns
th(A)
Address hold time
0
ns
tw(CTRL)
Control pulse width
30
ns
trec(CTRL)
Control recovery time
30
ns
tsu(D)
Data setup time
20
ns
th(D)
Data hold time
0
ns
tw(cycle)
FIFO access cycle time
200
ns
tw(RST )
RESET pulse width
100
ns
tst(RST )
Control start time after RESET
100
ns
tc(TCK)
TCK cycle time
100
ns
tw(TCKH)
TCK "H" pulse width
40
ns
tw(TCKL)
TCK "L" pulse width
40
ns
tsu(TDI-TCK)
TDI,TMS setup time
20
ns
th(TDI-TCK)
TDI,TMS setup time
20
ns
tw(TRST)
TRST "L" pulse width
100
ns
td(CTRLDack)
TRST "L" pulse width
Min.
Typ.
Max.
83
43
Unit
ns
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Measurement circuit
1. Terminals except f or USB buf f er block
Vcc
Vcc
Input
RL=1kohm
SW1
D15-0, TDO
CL
SW2
P.G
DUT
RL=1kohm
50ohm
Other output
CL
Item
SW1
SW2
tdis(CTRL(LZ))
close
open
tdis(CTRL(HZ))
open
close
ta(CTRL(ZL))
close
open
ta(CTRL(ZH))
open
close
(1) Input pulse lev el
: 0 to 3.3V
Input pulse rise/f all time : tr=tf =3ns
Input timing v oltage
: 1.65V
Output timing v oltage
: Vcc/2
(tdis(LZ) is measured at 10% of output,
tdis(HZ) is measured at 90% of output)
(2) Capacitance CL includes stray capacitance
and probe capacitance.
2. USB buf f er block
Vcc
Vcc
RL=1.5kohm
D+
RL=27ohm
CL
RL=15kohm
(1) tr, tf is measured f rom 10% to 90% of output.
(2) Capacitance CL includes stray capacitance
and probe capacitance.
DUT
D-
GND
RL=27ohm
CL
RL=15kohm
44
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
TIMING DIAGRAM
(1) Write timing
tsu(A)
th(A)
Address is established
A6 to 1
tw(cycle)
trec(CTRL)
tw(CTRL)
CS ,WR
(note 2)
tsu(D)
th(D)
Data input is established
D15 to 0
(2) Read timing
ta(A)
th(A)
Address is established
A6 to 1
tw(cycle)
(note 1)
ta(CTRL)
trec(CTRL)
tw(CTRL)
CS ,RD
(note 3)
tv(CTRL)
ten(CTRL)
tdis(CTRL)
D15 to 0
Data output is established
note 1 : tw(cycle) is needed when access FIFO.
note 2 : Write is done in the overlap period when CS and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
Spec of pulse width is valid of the overlap period of active "L".
note 3 : Read is done in the overlap period of CS and RD is active "L"
Spec from the negative edge is valid from the latest signal.
Spec from the positive edge is valid form the fastest inactive signal.
Spec of pulse width is valid during active "L" overlap period.
45
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3) DMA Transfer Timing -1
In case of Full speed transfer mode (DMA operation mode register : MODE=0)
(3-1) Write timing -1
twh(Dreq)
Dreq (note 4)
td(CTRL-Dreq)
td(Dack-Dreq)
Dack
trec(CTRL)
tw(CTRL)
WR
(note 5)
tsu(D)
th(D)
Data input is established
D15 to 0
(3-2) Read timing -1
twh(Dreq)
Dreq (note 4)
td(CTRL-Dreq)
td(Dack-Dreq)
Dack
ta(CTRL)
trec(CTRL)
tw(CTRL)
RD (note 6)
tv(CTRL)
ten(CTRL)
tdis(CTRL)
D15 to 0
Data output is established
note 4 : Inactive condition of Dreq is Dack="L"
And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(CTRL-Dreq).
note 5 : Write is done in the overlap period when Dack and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
Spec of pulse width is valid of the overlap period of active "L".
note 6 : Read is done in the overlap period of Dack and RD is active "L"
Spec from the negative edge is valid from the latest signal.
Spec from the positive edge is valid form the fastest inactive signal.
Spec of pulse width is valid during active "L" overlap period.
46
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(3-3) Write timing -2
Dreq (note 4)
td(CTRL-Dreq)
td(CTRL-Dreq)
td(Dack-Dreq)
Dack
RD
tw(CTRL)
WR
tw(CTRL)
(note 5)
tsu(D)
tsu(D)
th(D)
th(D)
D15 to 0
(3-4) Read timing -2
Dreq (note 4)
td(CTRL-Dreq)
td(CTRL-Dreq)
td(Dack-Dreq)
Dack
tw(CTRL)
RD
tw(CTRL)
(note 6)
WR
ta(CTRL)
tv(CTRL)
ta(CTRL)
tv(CTRL)
D15 to 0
note 4 : Inactive condition of Dreq is Dack="L"
And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(CTRL-Dreq).
note 5 : Write is done in the overlap period when Dack and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
Spec of pulse width is valid of the overlap period of active "L".
note 6 : Read is done in the overlap period of Dack and RD is active "L"
Spec from the negative edge is valid from the latest signal.
Spec from the positive edge is valid form the fastest inactive signal.
Spec of pulse width is valid during active "L" overlap period.
47
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(4) DMA Transfer Timing -2
In case of one word transfer mode (DMA operation mode register : MODE=1)
(4-1) Write timing -1
twh(Dreq)
Dreq (note 7)
td(Dackh-Dreq)
td(Dack-Dreq)
Dack
td(CTRL-Dack)
trec(CTRL)
tw(CTRL)
WR
(note 5)
tsu(D)
th(D)
Data input is established
D15 to 0
(4-2) Read timing -1
twh(Dreq)
Dreq (note 7)
td(Dackh-Dreq)
td(Dack-Dreq)
Dack
td(CTRL-Dack)
ta(CTRL)
trec(CTRL)
tw(CTRL)
RD (note 6)
tv(CTRL)
ten(CTRL)
tdis(CTRL)
D15 to 0
Data output is established
note 7 : Inactive condition of Dreq is Dack="L"
And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(Dackh-Dreq).
note 5 : Write is done in the overlap period when Dack and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
Spec of pulse width is valid of the overlap period of active "L".
note 6 : Read is done in the overlap period of Dack and RD is active "L"
Spec from the negative edge is valid from the latest signal.
Spec from the positive edge is valid form the fastest inactive signal.
Spec of pulse width is valid during active "L" overlap period.
48
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(5) Interrupt timing
twh(INT)
INT
td(CTRL-INT)
CS ,WR
(note 8)
note 8 : Write is done in the overlap period when CS and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
(6) Reset timing
tw(RST)
RST,TRST
tst(RST)
CS ,WR
49
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(7) JTAG timing
tc(TCK)
tw(TCKL)
tw(TCKH)
TCK
tsu(TDI-TCK)
th(TCK-TDI)
TDI,TMS
td(TCK-TDOX)
td(TCK-TDOV)
TDO
tw(TRST)
TRST
50
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Abstraction of JTAG
M66290A has JTAG (Joint Test Action Group) interf ace
which meets IEEE 1149.1 test access port spec.
This JTAG interf ace can be used f or input/output path
(boundary scan path) f or boundary scan test.
Further inf ormation as to JTAG test access port, ref er
to "IEEE Std. 1149.1a-1993".
Test mode input (TMS)
Test mode select input to control status shif t of test
circuit. This is sampled by the positiv e edge of TCK.
Test reset input (TRST)
"L" activ e test reset input to initialize the test circuit
asy nchronously . To assure this reset f unction, keep
TMS input as "H" when this signal changes f rom "L"
to "H".
Pin descriptions
Pin description which relates to JTAG interf ace of
M66290A are as f ollows.
JTAG circuit constitution
Test clock input (TCK)
JTAG circuit of M66290A is constituted by the blocks
as f ollows.
Clock input into test circuit.
Test data input (TDI)
(1) Command register which keeps command code
which is f etched through the boundary scan path.
(2) Data register group which is accessed through the
boundary scan pass.
(3) Test access port (TAP) controller to control the
status shif t of JTAG block.
(4) Control logic f or input select, output select, and so.
Sy nchronous serial input to input test command
code and test data. Data is sampled by the
positiv e edge of TCK.
Test data output (TDO)
Sy nchronous serial output to output test command
code and test data. Output data changes by the
negativ e edge of TCK and is output only in the state
of Shif t-IR or Shif t-DR. In other state,keeps "Z".
M66290A
Data register group
TDI 11
Boundary scan
register (JTAGBSR)
By pass register
(JTAGBPR)
ID code register
(JTAGIDR)
Decoder
12 TDO
Command register
(3bits) (JTAGIR)
TMS 10
TCK
9
TAP controller
TRST 8
51
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
Abstract of JTAG operations
JTAG interf ace shif ts the internal state according to TMS
input, and do two kinds of operations as f ollows. Both are
basically
executed in turn of "Capture -> Shif t -> Update".
There are f our basic access to command register
and to data register. And the access is executed
based on the status shif t of TAP controller.
TAP controller is shif ted of its status by the TMS
input and make a control signal which is needed to
each state.
IR path sequence
Set the command code into command register and when
path sequence comes, select the data register which is
the object of the operation.
Capture operation
Result of the boundary scan test or the f ixed
data which is def ined to each register, is sampled.
For operation, load the input data into shif t register
stage.
DR path sequence
To selected data register, ref er or set the data.
Shif t operation
Through the boundary scan path, access f rom external
is done. M66290A set the data f rom external and at the
same time, output the data which is sampled by capture
operation.
For register operation, right shif t is executed among
shif t register stage of each bit.
Input select
Data input
To next cell
Shift register
stage
A
From previous
cell
B
Data output
Y
D
Q
T
A/B
D
Q
T
Shift-DR/IR
Parallel output
stage
Clock-DR/IR
Update operation
Update-DR/IR
In shif t operation, driv e the data which is set by external.
For register operation, transf er the v alue which is set to
shif t register stage, to parallel output stage.
1
Test reset
Figure. Basic construction of JTAG related register
Test-Logic-Reset
0
1
1
0
1
Run-Test-/Idle
Select-DR-Scan
Select-IR-Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
0
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
1
0
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Exit2-IR
0
Update-IR
1
0
note: 0,1 shows the status of TMS input signal
Figure. Status shif t of TAP controller
52
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
JTAG registers
Command registers
Data registers
Command register is constituted by 3 bits register
which keeps command code, and is set in the IR
path sequence. Data register, which is selected in
the f ollowing path sequence, is determined by the
command which is set into the command register.
Initial v alue in test reset is IDCODE command.
Until the command code is set f rom external,
IDCODE register is kept selecting as the data
register.
(1) Boundary scan register (JTAGBSR)
M66290A supports three commands (EXTEST,
SAMPLE/PRELOAD, and BYPASS) which are
established as essential by IEEE 1149.1 and the
dev ice recognize register access command
(IDCODE).
Below are the commands and the related code.
EXTEST (Command code : b'000)
Executes outside circuit connection test and on
board connection test. Reads the TDI input into the
"Boundary Scan Register" and outputs the contents
of "Boundary Scan Register" f rom TDO.
This is f or boundary scan test and is assigned to each
terminal of M66290A which is related to JTAG.
Boundary scan register is connected between TDI and
TDO terminal, and is selected when "EXTEST Command"
is ordered. This register captures the status of input
terminal or the output v alue f rom internal logic circuit in
the state of C apture-DR. In the state of Shif t-DR, input
the data f or boundary scan test parallely outputting the
sampled v alue. And set terminal f unction (IN/OUT of
bidirectional terminal or direction of 3-state output) and
output v alue.
As to the JTAG related terminal and the structure of
boundary scan, ref er to BSDL specially .
(2) BYPASS register (JTAGBPR)
BYPASS register is one bit register to by pass the boundary
scan path when M66290A is not the object in boundary scan
test. BYPASS register is connected between TDI and TDO
terminal, and is selected when "BTPASS command" is
ordered. In the state of C apture-DR, "0" is loaded.
IDCODE (Command code : b'001)
(4) IDCODE register (JTAGIDR)
Selects the "IDCODE Register" and outputs the
dev ice and company discrimination data f rom
TDO.
SAMPLE/PRELOAD (Command code : b'010)
Samples the circuit status in operation and outputs
it f rom TDO, and at the same time, inputs the data
f rom TDI which will be use in the next boundary
scan test and set into the "Boundary Scan Register"
prev iously .
IDCODE register is a register of 32bits to discriminate the
dev ice and the company , and keeps inf ormation as f ollows.
IDCODE register is connected between TDI and TDO
terminal,
and is selected when "IDCODE Command" is ordered.
IDCODE data is loaded in Capture-DR state and is output
f rom TDO in Shif t-DR state.
1. Version inf ormation (4bits) : b'0000
BYPASS (Command code : b'111)
2. Part number (16bits)
Selects the "BYPASS Register" and executes the
ref er and the set of the data.
3. Company ID (11bits)
Don't set the command code except f or abov e.
4. LSB (1bit)
53
: b'0001 1000 1001 0010
(Binary code of "6290")
: b'000 0001 1100
(JEDEC code of MITSUBISHI)
: b'1
(Fixed)