CPC5710

CPC5710N
Phone Line Monitor (PLM) IC
INTEGRATED CIRCUITS DIVISION
Features
Description
• Excellent common-mode rejection ratio (CMRR)
• Application circuits can meet isolation requirements
of worldwide telephony standards
• Small 8-pin SOIC
• Worldwide telephone network compatibility
• Full-wave ringing level detector comparator with
internal threshold, large hysteresis, and logic-level
output
• 3.3V or 5V operation
• High differential input impedance
• Very low common-mode input impedance
• Fixed gain
• Differential or single-ended linear output
• TTL logic level input
• CMOS logic level output (TTL compatible)
• Virtually non-detectable in voice monitoring
applications
The CPC5710N is a selectable dual function CMOS
special purpose integrated high-impedance input,
fixed-gain amplifier and an internally set voltage level
comparator for telephone line monitoring. The high
(>40dB) common-mode rejection ratio makes the
CPC5710N an excellent choice for signaling detection,
line condition monitoring, discrete voice recording and
CID buffering applications. In addition to voice
applications, the CPC5710N is ideal for data
applications such as embedded modem designs
utilized in broadband set-top boxes.
Ordering Information
Part Number
CPC5710N
CPC5710NTR
Applications
Description
PLM IC, Tubed, 100/Tube
PLM IC, Tape &Reel, 2000/Reel
e3
Pb
• The CPC5710N can be used for line monitoring or
detection of signaling states and loop conditions
such as:
• Display feature (caller ID) signal buffering
• Line-In-Use (LIU) detection
• Ringing signal with adjustable detection level
• Battery presence monitoring
• Tip to ring line voltage monitoring
• Line polarity
• Imperceptible voice recording
CPC5710N Block Diagram
VDD
3
VDD
50kΩ
1
LIN/CMP
VDD
+
VDD
2
CMPOUT
1.625 V
+
6
+ +
AV=6
- -
IN+
IN-
7
0V
5
2V
4
LINOUT+
LINOUT-
Switch shown
in Detector Mode
VSS
8
+
-
DS-CPC5710-R03
1.25 V
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GND
GND
1
CPC5710N
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Recommended Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 Detector Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3 LIN/CMP Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
4
4
4
4
4
2. Using CPC5710N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 LIN/CMP Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Amplifier Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Linear Amplifier Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Detector Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Ringing Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Setting Ringing Detection Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Power Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
5
5
5
6
3. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Line-In-Use (LIU) and Line Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ringing Detection Application . . . . . . . . . . . . .
3.2.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Regulatory Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
8
8
8
4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5.1 CPC5710N 8-Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5.2 CPC5710NTR Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
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R03
CPC5710N
INTEGRATED CIRCUITS DIVISION
1. Specifications
1.1 Package Pinout
1.2 Pin Description
Pin
1
VDD
2
CMPOUT
GND
8
IN -
7
3
LIN/CMP
IN +
6
4
LINOUT+
LINOUT-
5
Name
Description
1
VDD
Power supply
2
CMPOUT
Detector output
3
LIN/CMP
Comparator Enable - disables linear amplifier
outputs.
4
LINOUT-
Linear amplifier inverting output
5
LINOUT+
Linear amplifier non-inverting output
6
IN+
Non-inverting differential input
7
IN-
Inverting differential input
8
GND
Ground
1.3 Absolute Maximum Ratings
Parameter
Minimum Maximum
Unit
VDD
-0.3
6
V
Storage temperature
-40
+125
°C
300
mW
VDD + 0.3
V
Total package power
dissipation
Logic input voltage
-0.3
Absolute maximum ratings are stress ratings. Stresses in excess of these
ratings can cause permanent damage to the device. Functional operation
of the device at conditions beyond those indicated in the operational
sections of this data sheet is not implied.
1.4 Recommended Operating Environment
Parameter
Conditions
Temperature
Humidity
R03
Non-condensing
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Minimum
Typical
Maximum
Unit
-40
-
+85
°C
5
-
95
%
3
CPC5710N
INTEGRATED CIRCUITS DIVISION
1.5 Electrical Characteristics
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements. Typical values, the result of engineering
evaluations, are characteristic of the device and are
provided for informational purposes only. They are not
however, a part of the production testing requirements.
Unless otherwise indicated:
VDD = 5V, Temperature = 25°C
1.5.1 AC Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Unit
Input Impedance
ZIN
10
-
-
M
Input offset voltage
VIO
-
-
40
mV
Input offset current
IIO
ICM = 0, No common-mode signal applied.
-
-
35
nA
ICM = 12A (per lead) signal applied.
-
-
125
nA
0.9
1.0
1.1
V
Output DC bias level
Output Low Voltage
Gain
Common-mode
rejection ratio
Equivalent input noise
voltage
VOUT_DC At LINOUT+ or LINOUT-, IO = 0.5mA
VOUT
IO = 0.5mA
-
-
50
mV
AV
0 to 20kHz
5.88
6
6.12
-
40
-
-
dB
-
-90
-
dBm/Hz
Minimum
Typical
Maximum
Unit
ICM = 0
675
750
850
mV
ICM = ±12A
488
750
1012
mV
300
375
450
mV
Minimum
Typical
Maximum
Unit
CMRR
Common-mode current  12A per lead,
0 to 120Hz
VN
1.5.2 Detector Threshold Characteristics
Parameter
Symbol
Conditions
Detection threshold
VIN_DET
Detector hysteresis
VIN_HYST ICM = 0
1.5.3 LIN/CMP Input Characteristics
Parameter
Symbol
Conditions
Input low voltage
VIL
-
-
0.8
V
Input high voltage
VIH
2.0
-
-
V
Input low leakage
current
Input high leakage
current
IIL
VIL = 0.4V
-
-
-120
A
IIH
VIH = 2.4V
-
-
-120
A
Minimum
Typical
Maximum
Unit
3.0
-
5.5
V
-
-
10
mA
1.5.4 Power Characteristics
Parameter
Symbol
Supply voltage
VDD
Supply current
IDD
4
Conditions
All inputs and outputs open
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R03
CPC5710N
INTEGRATED CIRCUITS DIVISION
2. Using CPC5710N
2.1 LIN/CMP Input
The LIN/CMP input selects the active output, either
the detector output CMPOUT or the linear outputs,
LINOUT- and LINOUT+. Set LIN/CMP low for linear
output and high for comparator output. Note that both
outputs cannot be used at once.
With LIN/CMP at logic low (LIN/CMP = 0), the
amplifier outputs are biased at a nominal 1VDC and
CMPOUT is held high. With LIN/CMP at logic high
(LIN/CMP = 1), LINOUT+ is 0V and LINOUT- is 2V.
Figure 1. LIN/CMP Timing for Caller-ID Signal
Reception
2s
500 ms
3s
475 ms
6R SNPD
GAIN CID  dB  = 20 log ----------------------------------------------------------------------------------------2
1
 4R SNP + R SNPD  + -------------------------2 fC SNP 
where  is the frequency of the signal.
Application Note AN-117 Customize Caller ID Gain and
Ringing Detect Voltage Threshold is a spreadsheet for
trying different component values in this type of circuit.
2.3 Detector Considerations
2.3.1 Ringing Signal Detection
2s
The CPC5710N detector is a full-wave configuration.
Ringing signals will assert the output on both positive
and negative parts of the ringing waveform. Hysteresis
is employed by the internal comparator circuit to
provide noise immunity. The set-up of the detector
causes CMPOUT output pulses to remain low for most
of the ringing signal positive and negative half-cycles.
CMPOUT returns high when the ringing signal is near
the zero-voltage crossing.
Caller ID data
LIN/CMP
Figure 2. CMPOUT Relative to Input
Signal levels not to scale
Ringing Signal
2.2 Amplifier Design
Considerations
CMPOUT
Amplifier inputs are biased at a nominal 1.25VDC, the
internal voltage reference. The internal common-mode
circuitry maintains the average of the inputs at
1.25VDC. For example, if one input reaches 1.3V, the
common-mode circuit drives the other input to 1.2V.
2.2.1 Linear Amplifier Gain
Display feature information (caller ID) and voice
signals are coupled through the linear amplifier. In
North America, CID data signals are typically sent
between the first and second ringing signal burst.
Referring to Figure 5., signal gain from tip and ring to
LINOUT+ and LINOUT- is determined by:
R03
2.3.2 Setting Ringing Detection Threshold
The ringing detection threshold depends on the
component values of the input network. The values for
these components shown in the application circuit are
recommended for typical operation. Referring to
Figure 5., the ringing detection threshold can be
changed according to the following formula:
750mV
V RINGPK =  -------------------
R RSNPD
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2
1
 4R SNP + R SNPD  + -------------------------------------2 f RING C SNP 
5
CPC5710N
INTEGRATED CIRCUITS DIVISION
With the application circuit in Figure 5., the series
capacitors serve to reduce the magnitude of the
high-amplitude, low-frequency ringing signals, while
making the ringing detection threshold of the
CPC5710N variable with the frequency of the ringing
signal. With the circuit as given, CMPOUT will change
states with a 15Hz ringing signal at approximately
48VPEAK. For a 68Hz ringing signal, CMPOUT will
change states with a ringing signal amplitude of
approximately 11.5VPEAK.
In applications where CPC5710N will be used only as
a ringing level detector, or if significant attenuation of
the amplified signal can be tolerated, the frequency
variability of the ringing detection threshold can be
reduced by increasing the value of the resistors and
capacitors in series with the input.
Application Note AN-117 Customize Caller ID Gain and
Ringing Detect Voltage Threshold is a spreadsheet for
trying different component values in this circuit for
LITELINK snoop circuit applications.
6
2.4 Power Quality
CPC5710N works best with a clean power supply. To
clean up power supply noise, IXYS Integrated Circuits
Division recommends using a pi network on the VDD
pin as shown in Figure 3., if needed.
Figure 3. Optional Power Supply pi Network
3.3 or 5 V
R100
10
FB100
600 Ω
200 mA
C101
10
A
C100
1
A
To VDD
Pin 1
Note: For lower-frequency noise, use a 220 H
inductor in series with R100.
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R03
CPC5710N
INTEGRATED CIRCUITS DIVISION
3. Applications
3.1 Line-In-Use (LIU) and Line Polarity Detector
This circuit performs two phone line interface
functions, LIU and line polarity detection. The LIU
output is logic high if the tip to ring voltage is less than
approximately 17V. This will occur whenever a parallel
device on the line such as a telephone or FAX is taken
off hook. This circuit can also be used to detect for the
presence or loss of battery.
The Polarity output indicates the polarity of the phone
line. Whenever tip is positive with respect to ring,
Polarity out will be a logic high.
Figure 4. LIU and Polarity Detection Application Circuit
+V
U1 CPC5710
VDD
50kΩ
3
VDD
+
LIN/CMP
CMPOUT
VDD
1
R13
20KΩ
+V
IN+
2
1.625 V
R3
R2
R4
6
R5
604KΩ
0V
IN+
+ +
AV=6
- -
IN-
7
RING
2V
LINOUT+
5
LINOUT-
4
R6
4.7MΩ
R8
20KΩ
+V
IN+
GND
+
-
1.25 V
GND
8
1/4 U2
LM339
OUT
INR10
21KΩ
VSS
R15
10KΩ
+V
IN+
R11
499KΩ
Switch shown
in Linear Mode
R1-4
8.06MΩ
1%
1206
R12
20KΩ
Polarity
+V
R17
4.7MΩ
+
R1
1/4 U2
LM339
OUT
IN-
TIP
R16
10KΩ
R14
4.7MΩ
+V
VDD
R9
499KΩ
IN-
1/4 U2
LM339
OUT
LIU
C1
1nF
R7
21KΩ
Unless noted otherwise:
All resistors 1%, 1/16 W.
All capacitors 16 V 10%.
R03
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7
CPC5710N
INTEGRATED CIRCUITS DIVISION
3.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal
Reception, and Ringing Detection Application
This application uses the logic input LIN/CMP to select
between ringing detection or buffering display feature
(caller-ID) and voice signals. Note the AC coupling of
the tip and ring signals.
period, configure LIN/CMP with a logic low to couple
the audio frequency signal to the output pins.
Please see “Detector Considerations” on page 5 for more
information on ringing detection.
With this circuit, setting LIN/CMP to a logic high
enables the ringing detector. After a valid ringing
Figure 5. Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ringing
Detection Application Circuit
U1 CPC5710
VDD
From
Control
Logic
LIN/CMP 3
3.3 or 5 V
VDD
50kΩ
1 VDD
+
VDD
2 CMPOUT
1.625 V
RINGING DET
+
TIP
R1
R3
R2 C1
R4 C2
RING
IN+
6
0V
+ +
AV=6
- -
R5
1.5MΩ
0603 7
IN-
5 LINOUT+
2V
4 LINOUT-
Display Feature Output
VOUT = VIN at 500 Hz
Switch shown
in Detector Mode
R1-4
C1,2
1.8 MΩ 220 pF
VSS
8 GND
+
-
1.25 V
GND
Unless noted otherwise:
All resistors are 1/8 W, 1%, 1206.
3.2.1 Frequency Response
The blocking capacitors used in this application circuit
affect the frequency response of the system. With the
components shown, response rolls off 3dB @ 166Hz.
Other values can be used for different response
characteristics.
3.3 Regulatory Issues
Component sizing and value recommendations shown
in the application circuits above will need to be
reviewed with regard to the regulatory and safety
requirements for each particular application.
8
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R03
CPC5710N
INTEGRATED CIRCUITS DIVISION
4. Manufacturing Information
4.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC5710N
MSL 1
4.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
4.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC5710N
260°C for 30 seconds
4.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
e3
Note: The CPC5710N branding (package imprinting) leaves off the last character of the part number, the letter “N,”
due to package space limitations.
R03
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9
CPC5710N
INTEGRATED CIRCUITS DIVISION
4.5 Mechanical Dimensions
4.5.1 CPC5710N 8-Pin SOIC Package
1.270 REF
(0.050)
Pin 8
PCB Land Pattern
0.60
(0.024)
0.762 ± 0.254
(0.030 ± 0.010)
3.937 ± 0.254
(0.155 ± 0.010)
5.994 ± 0.254
(0.236 ± 0.010)
5.40
(0.213)
Pin 1
1.55
(0.061)
0.406 ± 0.076
(0.016 ± 0.003)
4.928 ± 0.254
(0.194 ± 0.010)
0.559 ± 0.254
(0.022 ± 0.010)
1.346 ± 0.076
(0.053 ± 0.003)
1.27
(0.050)
Dimensions
mm
(inches)
0.051 MIN - 0.254 MAX
(0.002 MIN - 0.010 MAX)
4.5.2 CPC5710NTR Tape and Reel Specifications
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
W=12.00
(0.472)
B0=5.30
(0.209)
K0= 2.10
(0.083)
A0=6.50
(0.256)
P=8.00
(0.315)
User Direction of Feed
Embossed Carrier
Embossment
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC5710-R03
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/22/2012
10
www.ixysic.com
R03