CPC5620/CPC5621 LITELINK™ III Phone Line Interface IC (DAA) Features Description • Superior voice solution with high power option, low noise, no automatic gain control circuit, and excellent part-to-part gain accuracy • Data access arrangement (DAA) solution for modems at speeds up to V.92 • 3.3 or 5 V power supply operation • Caller ID signal reception function • Easy interface with modem ICs and voice CODECs • Worldwide dial-up telephone network compatibility • Supplied application circuit complies with the requirements of TIA/EIA/IS-968 (FCC part 68), UL1950, UL60950, EN60950, IEC60950, EN55022B, CISPR22B, EN55024, and TBR-21 • Complies with UL1577 • Line-side circuit powered from telephone line • Compared to other silicon DAA solutions, LITELINK: - Uses fewer passive components - Takes up less printed-circuit board space - Uses less telephone line power - Offers simplified operation - Is a single-chip solution LITELINK III is a single-package silicon phone line interface/DAA used in voice and data communication applications to make connections between host equipment and telephone networks. ar y LITELINK provides a high-voltage isolation barrier, AC and DC phone line termination, switchhook, 2-wire to 4-wire hybrid, ring detection, and on-hook signal detection. LITELINK can be used in both differential and single-ended signal applications. im in LITELINK uses on-chip optical components and a few inexpensive external components to form a complete voice or high-speed data phone line interface. LITELINK eliminates the need for the large isolation transformers or capacitors used in other interface configurations. It incorporates the required high-voltage isolation barrier in the surface-mount SOIC package. el Applications Computer telephony and gateways, such as VoIP PBXs Satellite and cable set-top boxes V.92 (and other standard) modems Fax machines Voicemail systems Embedded modems for POS terminals, automated banking, remote metering, vending machines, security, and surveillance Ordering Information Part Number Pr • • • • • • • The CPC5620 (half-wave ring detect) and CPC5621 (full-wave ring detect) PLIs build upon Clare’s LITELINK II line, with improved insertion loss control, improved noise performance, and lower minimum current draw from the phone line. CPC5620A CPC5620ATR CPC5621A CPC5621ATR Description 32-pin PLI with half-wave ring detect, tubed 32-pin PLI with half-wave ring detect, tape and reel 32-pin PLI with full-wave ring detect, tubed 32-pin PLI with full-wave ring detect, tape and reel Figure 1. CPC5620/CPC5621 Block Diagram TIP+ Isolation Barrier Transmit Isolation Amplifier Tx+ Tx- Transmit Diff. Amplifier Transconductance Stage 2-4 Wire Hybrid AC/DC Termination Hookswitch VI Slope Control AC Impedance Control Current Limit Control MODE OH Vref Gain Trim RING CID RING- Vref Gain Trim Receive Isolation Amplifier Rx+ Rx- Receive Diff. Amplifier CID/ RING MUX Snoop Amplifier DS-CPC5620/5621-R0.E CSNOOP RSNOOP CSNOOP RSNOOP www.clare.com 1 CPC5620/CPC5621 1 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 5 2 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Resistive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Reactive Termination Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9 im in ar y 3 Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 On-hook Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Ring Signal Reception via the Snoop Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Polarity Reversal Detection with CPC5621 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 On-hook Caller ID Signal Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Off-Hook Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Start-up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Non-Current Limited Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Current Limited Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Mode Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 13 el 4 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pr 5 LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Clare, Inc. Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Third Party Design Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Manufacturing Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 17 17 18 18 18 18 18 R0.E CPC5620/CPC5621 1. Electrical Specifications 1.1 Absolute Maximum Ratings Unit - VRMS 150 mA 1 W 0 +85 °C Storage temperature -40 +125 °C Soldering temperature - +220 °C Isolation Voltage 1500 Continuous Tip to Ring Current (RZDC = 5.2Ω) Operating temperature in Total Package Power Dissipation y Minimum Maximum ar Parameter Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. Parameter Minimum Typical Maximum Unit - 5.50 V Host side - 10 mA Host side 2.8 - 3.2 V - 7 8 mA DC Characteristics 3.0 Operating Current IDD - Operating Current IDDL Metallic DC Resistance Pr On-hook Characteristics el Operating Voltage VDD Operating Voltage VDDL im 1.2 Performance Conditions Line side, derived from tip and ring Line side, drawn from tip and ring while off-hook 10 - - MΩ Tip to ring, 100 Vdc applied Longitudinal DC Resistance 10 - - MΩ 150 Vdc applied from tip and ring to Earth ground Ring Signal Detect Level 5 - - VRMS 68 Hz ring signal applied to tip and ring Ring Signal Detect Level 28 - - VRMS 15 Hz ring signal applied across tip and ring Snoop Circuit Frequency Response 166 - >4000 Hz -3 dB corner frequency @ 166 Hz, in Clare application circuit - -40 - dB 120 VRMS 60 Hz common-mode signal across tip and ring Ringer Equivalence - 0.1B - REN Longitudinal Balance 60 - - dB Per FCC part 68.3 - 600 - Ω Tip to ring, using resistive termination application circuit 40 - - dB Per FCC part 68.3 - 26 - dB Into 600 Ω at 1800 Hz 30 - 4000 Hz -3 dB corner frequency 30 Hz - 36 - dB Into 600 Ω at 1800 Hz, with C18 in the resistive termination application circuit Snoop Circuit CMRR Off-Hook Characteristics AC Impedance Longitudinal Balance Return Loss Transmit and Receive Characteristics Frequency Response Trans-Hybrid Loss Rev. 0.E www.clare.com 3 CPC5620/CPC5621 Minimum Typical Maximum Unit -0.4 0 0.4 dB Average In-band Noise - -126 - dBm/Hz Harmonic Distortion - -80 - dB Transmit Level - 0 2.2 VP-P Single-tone sine wave. Or 0 dBm into 600 Ω. Receive Level - - 2.2 VP-P Single-tone sine wave. Or 0 dBm into 600 Ω. RX+/RX- Output Drive Current - - 0.5 mA Sink and source 60 90 120 kΩ Isolation Voltage 1500 - - VRMS Line side to host side Surge Rise Time 2000 - - V/µS No damage via tip and ring Transmit and Receive Insertion Loss TX+/TX- Input Impedance Conditions 30 Hz to 4 kHz, for resistive termination application circuit with MODE de-asserted and for reactive termination application circuit with MODE asserted. 4 kHz flat bandwidth -3 dBm, 600 Hz, 2nd harmonic y Parameter MODE, OH, and CID Control Logic Inputs ar Isolation Characteristics 0.8 - 2.0 V High Level Input Current -120 - 0 µA VIN≤VDD Low Level Input Current - - -120 µA VIN=GND Output High Voltage VDD -0.4 Output Low Voltage - im RING Output Logic Levels in Input Threshold Voltage - - V IOUT = -400 µA - 0.4 V IOUT = 1 mA Pr el Specifications subject to change without notice. All performance characteristics based on the use of Clare application circuits. Functional operation of the device at conditions beyond those specified here is not implied. All specifications at 25 °C 4 www.clare.com Rev. 0.E CPC5620/CPC5621 1.3 Pin Description VDD Host (CPE) side power supply 2 TXSM Transmit summing junction 3 TX- Negative differential transmit signal to DAA from host 4 TX+ Positive differential transmit signal to DAA from host 5 TX Transmit differential amplifier output 6 MODE When asserted low, changes gain of TX path (-7 dB) and RX path (+7 dB) to accommodate reactive termination networks 7 GND Host (CPE) side analog ground 8 OH Assert logic low for off-hook operation 9 RING Indicates ring signal, pulsed high to low Assert logic low while on hook to place CID information on RX pins. 11 RX- Negative differential analog signal received from the telephone line. Must be AC coupled with 0.1 µF. 12 RX+ Positive differential analog signal received from the telephone line. Must be AC coupled with 0.1 µF. 13 SNP+ Positive differential snoop input 14 SNP- Negative differential snoop input 15 RXF Receive photodiode amplifier output 16 RX Receive photodiode summing junction 17 VDDL Power supply for line side, regulated from tip and ring. 18 RXS Receive isolation amp summing junction 19 RPB Receive LED pre-bias current set REFL TXF ZTX ZNT TXSL BRNTS GAT NTF DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pr el im 10 CID VDD TXSM TXTX+ TX MODE GND OH RING CID RXRX+ SNP+ SNPRXF RX y 1 20 BR- Bridge rectifier return 21 ZDC Electronic inductor DCR/current limit 22 DCS2 DC feedback output 23 DCS1 V to I slope control 24 NTF Network amplifier feedback 25 GAT External MOSFET gate control 26 NTS Receive signal input 27 BR- Bridge rectifier return 28 TXSL Transmit photodiode summing junction 29 ZNT Receiver impedance set 30 ZTX Transmit transconductance gain set 31 TXF Transmit photodiode amplifier output 32 REFL 1.25 Vdc reference Rev. 0.E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function ar Name in Pin Figure 2. Pinout www.clare.com 5 CPC5620/CPC5621 2. Application Circuits circuit (see Section 2.2 on page 8) describes a TBR-21 implementation. This circuit can be adapted easily for other reactive termination needs. Worldwide applications of LITELINK are described more fully in Clare application note AN-147, Worldwide Application of LITELINK. LITELINK can be used with telephone networks worldwide. Some public telephone networks, notably in North America and Japan require resistive line temrination. Other telephone networks in Europe and elsewhere require reactive line termination. y The application circuits below address both line termination models. The reactive termination application Figure 3. Resistive Termination Application Circuit Schematic C1 1 C9 0.1 A U1 LITELINK A 2 C13 0.1 3 TX- C2 0.1 TX+ 4 5 6 7 OH 8 RING 9 VDD REFL TXSM TXF TX- ZTX TX+ ZNT TX TXSL MODE GAT OH RING RX+ C4 0.1 NTF DCS1 DCS2 12 RX+ 13 SNP+ 14 SNP15 RXF ZDC BR- RPB RXS 16 RX A 32 31 30 29 28 R75 (RNTX) 261K 1% 27 VDDL R2 (RRXF) 130K 1% C15 0.01 500V 24 R12 (RNTF) 499K 1% 22 R15 (RDCS2) 1.69M 1% 21 20 R16 (RZDC) 8.2 1% 19 R76 (RHNTF) 200K 1% 18 R22 (RDCS1A) 6.8 M 1% R21 (RDCS1B) 6.2 M 1% R14 (RGAT) 47 25 23 BR- Q1 CPC5602C R13 (RNTS) 1M 1% 26 Pr RX- BR- NTS GND 10 CID C14 0.1 11 RX- CID BR- R5 (RTXF) 60.4K 1% el 1 R1 (RTX) 80.6K 1% C10 0.01 500V im FB1 600 Ω 200 mA C16 10 in 3.3 or 5 V R23² 10 ar 2.1 Resistive Termination Application Circuit C12 (CDCS) 0.027 C21 (CGAT) 100 pF BR- R20 (RVDDL) 2 BR- + DB1 17 R4 (RPB) 68.1 1% BR- R18 (RZTX) 3.32K 1% R8 (RHTX) 221K 1% TIP - SP1¹ 1 BR- C18 15 pF³ BR2 R10 (RZNT) 301 1% BR- RING NOTE: Unless otherwise noted, all resistors are in Ohms, 5%. All capacitors are in microFarads. C7 (CSNP-) 220pF 2000V R3 (RSNPD) 1.5M 1% R6 (RSNP-2) 1.8M 1/10W 1% R44 (RSNP-1) 1.8M 1/10W 1% R7 (RSNP+2) C8 (CSNP+) 1.8M 1/10W 1% 220pF 2000V R45 (RSNP+1) 1.8M 1/10W 1% ¹This design was tested and found to comply with FCC Part 68 with this part. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare appli- 6 cation note AN-146, Guidelines for Effective LITELINK Designs for more information. ³Optional for enhanced trans-hybrid loss. www.clare.com Rev. 0.E CPC5620/CPC5621 2.1.1 Resistive Termination Application Circuit Part List Description C1 C2, C4, C9, C13, C14 1 µF, 16 V, ±10% 0.1 µF, 16 V, ±10% 2 C7, C81 220 pF, 2 kV, ±5% 2 C10, C151 0.01 µF, 500 V, ±10% 1 1 1 1 1 1 1 1 1 C12 C16 C18 (optional) C21 R1 R2 R3 R4 R5 0.027 µF, 16 V, ±10% 10 µF, 16 V, ±10% 15 pF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 kΩ, 1/16 W, ±1% 130 kΩ, 1/16 W, ±1% 1.5 MΩ, 1/16 W, ±1% 68.1 Ω, 1/16 W, ±1% 60.4 kΩ, 1/16 W, ±1% 4 R6, R7, R44, R451 R8 R10 R12 R13 R14 R15 R16 R18 R20 R21 R22 R23 R75 R76 FB1 DB1 SP1 Q1 U1 1.8 MΩ, 1/10 W, ±1% 1 im 221 kΩ, 1/16 W, ±1% 301 Ω, 1/16 W, ±1% 499 kΩ, 1/16 W, ±1% 1 MΩ, 1/16 W, ±1% 47 Ω, 1/16 W, ±5% 1.69 MΩ, 1/16 W, ±1% 8.2 Ω, 1/16 W, ±1% 3.32 kΩ, 1/16 W, ±1% 2 Ω, 1/16 W, ±5% 6.2 MΩ, 1/16 W, ±1% 6.8 MΩ, 1/16 W, ±1% 10 Ω, 1/16 W, ±5%, or 220 µH inductor 261 kΩ, 1/16 W, ±1% 200 kΩ, 1/16 W, ±1% 600 Ω, 200 mA ferrite bead SIZB60 bridge rectifier 350 V, 100 A, P3100SB Sidactor CPC5602 FET CPC5620 LITELINK Panasonic, Electro Films, FMI, Vishay, etc. el Pr 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Panasonic, AVX, Novacap, Murata, SMEC, etc. in 1 5 Suppliers y Reference Designator ar Quantity Murata BLM11A601S or similar Shindengen, Diodes, Inc. Teccor, ST Microelectronics, TI Clare Through-hole components offer significant cost savings over SMT. Rev. 0.E www.clare.com 7 CPC5620/CPC5621 2.2 Reactive Termination Application Circuit Figure 4. Reactive Termination Application Circuit Schematic 3.3 or 5 V R23² 10 C1 1 C9 0.1 A C13 0.1 3 TX- C2 0.1 TX+ 4 5 6 7 OH 8 RING 9 VDD REFL TXSM TXF TX- ZTX TX+ ZNT TX TXSL MODE BR- GND NTS OH GAT RING NTF 10 CID C14 0.1 11 RX- CID RXRX+ C4 0.1 DCS1 DCS2 12 RX+ 13 SNP+ ZDC 14 SNP15 RXF RPB RXS 16 RX VDDL R2 (RRXF) 130K 1% 31 30 29 28 27 25 R12 (RNTF) 221K 1% 23 R15 (RDCS2) 1.69M 1% 22 21 20 R16 (RZDC) 22.1 1% 19 18 17 R76 (RHNTF) 200K 1% C20 (CZNT) 0.68 R21 (RDCS1B) 6.2 M 1% C12 (CDCS) 0.027 C21 (CGAT) 100 pF R20 (RVDDL) 2 BR- R8 (RHTX) 200K 1% el R4 (RPB) 68.1 1% BR- R22 (RDCS1A) 6.8 M 1% R14 (RGAT) 47 26 24 BR- Q1 CPC5602C R13 (RNTS) 1M 1% R75 (RNTX) 110K 1% Pr A BR- 32 C15 0.01 500V ar 2 im 1 R1 (RTX) 80.6K 1% C10 0.01 500V BRR5 (RTXF) 60.4K 1% y U1 LITELINK A in FB1 600 Ω 200 mA C16 10 R10 (RZNT1) 59 1% R11 (RZNT2) 169 1% R18 (RZTX) 10K 1% BR- BR- + DB1 TIP - SP1¹ 1 BR2 RING NOTE: Unless otherwise noted, all resistors are in Ohms, 5%. All capacitors are in microFarads. BR- C7 (CSNP-) 220pF 2000V R3 (RSNPD) 1.5M 1% R6 (RSNP-2) 1.8M 1/10W 1% R44 (RSNP-1) 1.8M 1/10W 1% R7 (RSNP+2) C8 (CSNP+) 1.8M 1/10W 1% 220pF 2000V R45 (RSNP+1) 1.8M 1/10W 1% ¹This design was tested and found to comply with FCC Part 68 with this part. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. 8 www.clare.com Rev. 0.E CPC5620/CPC5621 2.2.1 Reactive Termination Application Circuit Part List Description C1 C2, C4, C9, C13, C14 1 µF, 16 V, ±10% 0.1 µF, 16 V, ±10% 2 C7, C81 220 pF, 2 kV, ±5% 2 C10, C151 0.01 µF, 500 V, ±10% 1 1 1 1 1 1 1 1 1 C12 C16 C20 C21 R1 R2 R3 R4 R5 0.027 µF, 16 V, ±10% 10 µF, 16 V, ±10% 0.68 µF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 kΩ, 1/16 W, ±1% 130 kΩ, 1/16 W, ±1% 1.5 MΩ, 1/16 W, ±1% 68.1 Ω, 1/16 W, ±1% 60.4 kΩ, 1/16 W, ±1% 4 R6, R7, R44, R451 R8 R10 R11 R12 R13 R14 R15 R16 R18 R20 R21 R22 R23 R75 R76 FB1 DB1 SP1 Q1 U1 1.8 MΩ, 1/10 W, ±1% 1Through-hole Rev. 0.E im 200 kΩ, 1/16 W, ±1% 59 Ω, 1/16 W, ±1% 169 Ω, 1/16 W, ±1% 221 kΩ, 1/16 W, ±1% 1 MΩ, 1/16 W, ±1% 47 Ω, 1/16 W, ±5% 1.69 MΩ, 1/16 W, ±1% 22.1 Ω, 1/16 W, ±1% 10 kΩ, 1/16 W, ±1% 2 Ω, 1/16 W, ±5% 6.2 MΩ, 1/16 W, ±1% 6.8 MΩ, 1/16 W, ±1% 10 Ω, 1/16 W, ±5%, or 220 µH inductor 110 kΩ, 1/16 W, ±1% 200 kΩ, 1/16 W, ±1% 600 Ω, 200 mA ferrite bead SIZB60 bridge rectifier 350 V, 100 A, P3100SB Sidactor CPC5602 FET CPC5620 LITELINK Panasonic, Electro Films, FMI, Vishay, etc. el Pr 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Panasonic, AVX, Novacap, Murata, SMEC, etc. in 1 5 Supplier y Reference Designator ar Quantity Murata BLM11A601S or similar Shindengen, Diodes, Inc. Teccor, ST Microelectronics, TI Clare components offer significant cost savings over SMT. www.clare.com 9 CPC5620/CPC5621 3. Using LITELINK As a full-featured telephone line interface, LITELINK performs the following functions: DC termination AC impedance control V/I slope control 2-wire to 4-wire conversion (hybrid) Current limiting Ring signal reception Caller ID signal reception Switch hook 3.2 On-hook Operation Pr This section of the data sheet describes LITELINK operation in standard configuration for usual operation. Clare offers additional application information online (see Section 5 on page 14). These include information on the following topics: • • • • • • In the on-hook state (OH and CID not asserted), an internal multiplexer turns on the snoop circuit. This circuit monitors the telephone line for two conditions; an incoming ring signal, and caller ID data bursts. Refer to the application schematic diagram (see Figure 3 on page 6). C7 (CSNP-) and C8 (CSNP+) provide a high-voltage isolation barrier between the telephone line and SNP- and SNP+ on the LITELINK while coupling AC signals to the snoop amplifier. The snoop circuit “snoops” the telephone line continuously while drawing no current. In the LITELINK, ringing signals are compared to a threshold. The comparator output forms the RING signal output from LITELINK. This signal must be qualified by the host system as a valid ringing signal. A low level on RING indicates that the LITELINK ring signal threshold has been exceeded. im High transmit power operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (911 feature) Battery reversal detection Line presence detection World-wide programmable operation el • • • • • • • • 3.2.1 Ring Signal Reception via the Snoop Circuit ar LITELINK can accommodate specific application features without sacrificing basic functionality and performance. Application features include, but are not limited to: y The LITELINK application circuit leakage current is less than 10 µA with 100 V across ring and tip, equivalent to greater than 10 MΩ on-hook resistance. in • • • • • • • • hook state, loop current flows through LITELINK and the system is answering or placing a call. Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection EMI considerations Other specific application materials are also referenced in this section as appropriate. 3.1 Switch Hook Control (On-hook and Off-hook States) LITELINK operates in one of two conditions, on-hook and off-hook. In the on-hook condition the telephone line is available for calls. In the off-hook condition the telephone line is engaged. Use the OH control input to place LITELINK in one of these two states. With OH high, LITELINK is on-hook and ready to make or receive a call. The snoop circuit is enabled. Assert OH low to place LITELINK in the off-hook state. In the off10 For the CPC5620 (with the half-wave ring detector), the frequency of the RING output follows the frequency of the ringing signal from the central office (CO), typically 20 Hz. The RING output of the CPC5621 (with the full-wave ring detector) is twice the ringing signal frequency. Hysteresis is employed in the LITELINK ring detector circuit to provide noise immunity. The setup of the ring detector comparator causes RING output pulses to remain low for most of the ringing signal half-cycle. The RING output returns high for the entire negative half-cycle of the ringing signal for the CPC5620. For the CPC5621, the RING output returns high for a short period near the zero-crossing of the ringing signal before returning low during the positive half-cycle. For both the CPC5620 and CPC5621, the RING output remains high between ringing signal bursts. The ring detection threshold depends on the values of R3 (RSNPD), R6 (RSNP-), R7 (RSNP+), C7 (CSNP-), and C8 (CSNP+). The values for these components shown in the typical application circuits are recommended for www.clare.com Rev. 0.E CPC5620/CPC5621 2 1 ( 2R 6 + R 3 ) + ------------------------------2 ( πf RING C 7 ) Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the ring detection threshold will also change the caller ID gain and the timing of the polarity reversal detection pulse, if used. 1. 2. 3. 4. Detect the first ringing signal outputs on RING. Assert CID low. Process the CID data from the RX outputs. De-assert CID (high or floating). Note: Taking LITELINK off-hook (via the OH pin) disconnects the snoop path from both the receive outputs and the RING output, regardless of the state of the CID pin. 6R 3 GAIN CID ( dB ) = 20 log ----------------------------------------------------------------2 1 ( 2R + R ) + -----------------6 3 im The full-wave ring detector in the CPC5621 makes it possible to detect tip and ring polarity reversal using the RING output. When the polarity of tip and ring reverses, a pulse on RING indicates the event. Your host system must be able to discriminate this single pulse of approximately 1 msec (using the recommended snoop circuit external components) from a valid ringing signal. ar CID gain from tip and ring to RX+ and RX- is determined by: 3.2.2 Polarity Reversal Detection with CPC5621 in 750mV V RINGPK = ----------------- R3 In North American applications, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: y typical operation. The ring detection threshold can be changed according to the following formula: 3.2.3 On-hook Caller ID Signal Reception Pr el On-hook caller ID (CID) signals are processed by LITELINK by coupling the CID data burst through the snoop circuit to the LITELINK RX outputs under control of the CID pin. In North America, CID data signals are typically sent between the first and second ringing signal. Figure 5. On-hook Caller ID Signal Timing in North America for CPC5620 (with Halfwave Ring Detect) 2s 500 ms 3s 475 ms ( πfC 7 ) 2 where ƒ is the frequency of the CID data signal. The recommended components in the application circuit yield a gain 0.27 dB at 200 Hz. Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the CID gain will also change the ring detection threshold and the timing of the polarity reversal detection pulse, if used. For single-ended snoop circuit output of 0 dBm, set the total resistance across the series resistors (R6/ R44 and R7/R45) to 1.4 MΩ. 2s 3.3 Off-Hook Operation 3.3.1 Receive Signal Path Caller ID data RING First Ring CID Signal levels not to scale Rev. 0.E Second Ring Signals to and from the telephone network appear on the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by the LITELINK two-wire to four-wire hybrid. Next, the receive signal is converted to infrared light by the receive photodiode amplifier and receive path LED. The intensity of the light is modulated by the receive signal and coupled across the electrical isolation barrier by a reflective dome. On the host equipment side of the barrier, the receive signal is converted by a photodiode into a photocurwww.clare.com 11 CPC5620/CPC5621 Variations in gain are controlled to within ±0.4 dB by factory gain trim, which sets the output of the photoamplifier to unity gain. set to unity at the factory, limiting insertion loss to 0, ±0.4 dB. Figure 7. Differential and Single-ended Transmit Path Connections to LITELINK To accommodate single-supply operation, LITELINK includes a small DC bias on the RX outputs of 1.0 Vdc. Most applications should AC couple the RX outputs as shown in Figure 6. 0.1uf TX- 0.1uf TX+ TXA1 + ar TXA2 LITELINK in Host CODEC or Transmit Circuit 0.1uf TX- 0.1uf TX+ TXA1 + im LITELINK may be used for differential or single-ended output as shown in Figure 6. Single-ended use will produce 6 dB less signal output amplitude. Do not exceed 0 dBm into 600 Ω (2.2 VP-P) signal input with the standard application circuit. See application note AN-149, Increased LITELINK II Transmit Power for more information. LITELINK Host CODEC or Transmit Circuit y rent. The photocurrent, a linear representation of the receive signal, is amplified and converted to a differential voltage output on RX+ and RX-. Figure 6. Differential and Single-ended Receive Path Connections to LITELINK RX+ 0.1uF 0.1uF RX- RX+ RX- Pr RX el LITELINK Host-side CODEC or Voice Circuit 0.1uF 3.4 Start-up Requirements OH must be de-asserted (set logic high) once after power-up for at least 50 ms to transfer internal gain trim values within LITELINK. This would be normal operation in most applications. RX+ 3.5 DC Characteristics 3.3.2 Transmit Signal Path Connect transmit signals from the host equipment to the TX+ and TX- pins of LITELINK. Do not exceed a signal level of 0 dBm in 600 Ω (or 2.2 VP-P). Differential transmit signals are converted to single-ended signals in LITELINK. The signal is coupled to the transmit photodiode amplifier in a similar manner to the receive path. The output of the photodiode amplifier is coupled to a voltage-to-current converter via a transconductance stage where the transmit signal modulates the telephone line loop current. As in the receive path, gain is The CPC5620 and CPC5621 are designed for worldwide application regarding DC characteristics, including use under the requirements of TBR-21. The ZDC, DCS1, and DCS2 pins control the VI slope characteristics of LITELINK. Selecting appropriate resistor values for RZDC (R16) and RDCS (R15) in the provided application circuits assure compliance with DC requirements. 3.5.1 Non-Current Limited Applications LITELINK includes a telephone line current limit feature that is selectable by selecting the desired value for RZDC (R16) using the following formula: 1V - + 0.011A I CL Amps = -----------R ZDC Clare recommends using 8.2 Ω for RZDC in North America and Japan, limiting telephone line current to 133 mA. 12 www.clare.com Rev. 0.E CPC5620/CPC5621 3.5.2 Current Limited Applications TBR-21 sets the telephone line current limit at 60 mA. To meet this requirement, set RZDC (R16) to 22.1 Ω. See Clare application note AN-146 Guidelines for Effective LITELINK Designs for information on FET heat sinking in this application. y 3.6 AC Characteristics 3.6.2 Reactive Termination Applications Line Impedance Model 750 Rb 270 C 150 nF 820 220 Pr Ra Australian el TBR-21 im Many countries use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. in North American and Japanese telephone line AC termination requirements are met with a resistive 600 Ω AC termination. Receive termination is applied to the LITELINK ZNT pin (pin 29) as a 301 Ω resistor, RZNT (R10). ar 3.6.1 Resistive Termination Applications 120 nF Matching a complex impedance requires the use of complex network on ZNT as shown in the “Reactive Termination Application Circuit” on page 8. 3.6.3 Mode Pin Usage Assert the MODE pin low to introduce a 7 dB pad into the transmit path and add 7 dB of gain to the receive path. These changes compensate for the gain changes made to the transmit and receive paths in reactive termination implementations. Insertion loss with MODE de-asserted and the resistive termination application circuit is 0 dB. Insertion loss with the reactive termination application circuit and MODE asserted is also 0 dB. Rev. 0.E www.clare.com 13 CPC5620/CPC5621 4. Regulatory Information y The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using LITELINK are advised to carefully verify that their end-product design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electro-static discharges resulting from inadequate protection measures at the board or system level. im 5. LITELINK Design Resources in ar LITELINK can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. LITELINK complies with the requirements of UL1577. LITELINK provides supplementary isolation. Metallic surge requirements are met through the inclusion of a Sidactor in the application circuit. Longitudinal surge protection is provided by LITELINK’s optical-across-thebarrier technology and the use of high-voltage components in the application circuit as needed. 5.1 Clare, Inc. Design Resources Pr el The Clare, Inc. web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: Application note AN-149, Increased LITELINK II Transmit Power Application note AN-150, Ground-start Supervision Circuit Using IAA110. LITELINK datasheets and reference designs 5.2 Third Party Design Resources Application note AN-107 LOCxx Series - Isolated Amplifier Design Principles The following also contain information useful for DAA designs. All of the books are available on amazon.com. Application note AN-114 ITC117P Application note AN-117 Customize Caller-ID Gain and Ring Detect Voltage Threshold for CPC5610/11 Understanding Telephone Electronics, Stephen J. Bigelow, et. al., Butterworth-Heinemann; ISBN: 0750671750 Newton’s Telecom Dictionary, Harry Newton, CMP Books; ISBN: 1578200695 Application note AN-140, Understanding LITELINK Application note AN-141, Enhanced Pulse Dialing with LITELINK Photodiode Amplifiers: Op Amp Solutions, Jerald Graeme, McGraw-Hill Professional Publishing; ISBN: 007024247X Application note AN-143, Loop Reversal Detection with LITELINK Teccor, Inc. Surge Protection Products Application note AN-146, Guidelines for Effective LITELINK Designs United States Code of Federal Regulations, CFR 47 Part 68.3 Application note AN-147, Worldwide Application of LITELINK 14 www.clare.com Rev. 0.E CPC5620/CPC5621 6. LITELINK Performance The following graphs show LITELINK performance using the North American application circuit shown in this data sheet. Figure 8. Receive Frequency Response at RX Figure 11. Transmit THD on Tip and Ring 2 0 0 y -20 -2 -40 ar -4 -60 Gain -6 dBm THD+N dB -80 -8 -100 -12 in -10 -120 -14 0 500 1000 1500 2000 2500 3000 3500 4000 -140 0 im Frequency Figure 9. Transmit Frequency Response at TX 0 Pr -2 -4 Gain dBm -6 -8 1000 1500 2000 2500 3000 3500 4000 Frequency Figure 12. Trans-Hybrid Loss 0 el 2 500 -5 -10 -15 THL -20 dB -25 -30 -10 -35 -12 -40 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 13. Return Loss Figure 10. Receive THD on RX 0 60 -20 55 -40 50 -60 THD+N dB Return Loss 45 (dB) -80 -100 40 -120 35 -140 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency 30 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Rev. 0.E www.clare.com 15 CPC5620/CPC5621 Figure 14. Snoop Circuit Frequency Response 5 0 -5 Gain (dBm ) -10 y -15 ar -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 in Frequency (Hz) Pr el im Figure 15. Snoop Circuit THD + N 500 1K 1.5K 2K 2.5K 3K 3.5K 4K Hz Figure 16. Snoop Circuit Common Mode Rejection +0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 500 1K 2K 4K Frequency (Hz) 16 www.clare.com Rev. 0.E CPC5620/CPC5621 7. Manufacturing Information 7.1 Mechanical Dimensions Figure 17. Dimensions 4° Max. 32 PL 7.493 + 0.127 (0.295 + 0.005) ar y 10.287 + .254 (0.405 + 0.010) 7.239 + 0.051 (0.285 + 0.002) 10.363 + 0.127 (0.408 + 0.005) 2.134 Max. (0.084 Max.) el 0.635 + 0.076 (0.025 + 0.003) im in 0.635 x 45° (0.025 x 45°) 1.016 Typ. (0.040 Typ.) 0.203 (0.008) 1.981 + 0.051 (0.078 + 0.002) DIMENSIONS A mm (Inches) 0.051 + 0.051 (0.002 + 0.002) 0.330 + 0.051 (0.013 + 0.002) Pr 9.525 + 0.076 (0.375 + 0.003) Coplanar to A 0.08/(0.003) 32 PL. Figure 18. Recommended Printed Circuit Board Layout 11.380 (0.448) 1.650 (0.065) 0.635 (0.025) 0.330 (0.013) 9.730 (0.383) Rev. 0.E www.clare.com 17 7.2 Tape and Reel Packaging Figure 19. Tape and Reel Dimensions 6.731 MAX. (.265) 1.753 ± .102 (.069 ± .004) .406 MAX. (.016) 12.090 (.476) 7.493 ± .102 (.295 ± .004) 3.20 (.126) 2.70 (.106) Top Cover Tape Embossed Carrier 10.897 ± .025 (.429 ± .001) 11.989 ± .102 (.472 ± .004) .050R TYP. 16.002 ± .305 (.630 ± .012) 10.693 ± .025 (.421 ± .001) 1.549 ± .102 (.061 ± .004) Feed Direction in Embossment Dimensions mm (inches) im 7.3 Soldering y Top Cover Tape Thickness .102 MAX. (.004) 2.007 ± .102 1.498 ±.102 3.987 ± .102 (.079 ± .004)(.059 ± .004) (.157 ±.004) ar 330.2 DIA. (13.00) which were used to determine the moisture sensitivity level of this component. el 7.3.1 Moisture Reflow Sensitivity Pr Clare has characterized the moisture reflow sensitivity of LITELINK using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labeled moisture sensitivity level (MSL), level 6. 7.4 Washing Clare does not recommend ultrasonic cleaning of LITELINK. 7.3.2 Reflow Profile The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard J-STD-020A, For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5620/CPC5621-R0.E Copyright © 2002, Clare, Inc. LITELINK™ is a trademark of Clare, Inc. All rights reserved. Printed in USA. 5/14/2002