CPC5622 RMS 3kV Isolation LITELINK® III Phone Line Interface IC (DAA) Features • Embedded modems for POS terminals, automated banking, remote metering, vending machines, security, and surveillance • Superior voice solution with low noise and excellent part-to-part gain accuracy • 3 kVRMS line isolation • Simultaneous ringing detection and CID monitoring for worldwide applications • Provides both full-wave ringing detect and half-wave ringing detect for maximum versatility • Transmit power of up to +10 dBm into 600 Ω • Data access arrangement (DAA) solution for modem speeds up to V.92 • 3.3V or 5 V power supply operation • Easy interface with modem ICs and voice CODECs • Worldwide dial-up telephone network compatibility • CPC5622 can be used in circuits that comply with the requirements of TIA/EIA/IS-968 (FCC part 68), UL60950 (UL1950), EN60950, IEC60950, EN55022B, CISPR22B, EN55024, and TBR-21 • Line-side circuit powered from telephone line • Compared to other silicon DAA solutions, LITELINK: - Uses fewer passive components - Takes up less printed-circuit board space - Uses less telephone line power - Is a single-IC solution Description LITELINK III is a single-package silicon phone line interface (PLI) DAA used in voice and data communication applications to make connections between host equipment and telephone networks. LITELINK uses on-chip optical components and a few inexpensive external components to form the required high voltage isolation barrier. LITELINK eliminates the need for large isolation transformers or capacitors used in other phone line interface configurations. LITELINK also provides AC and DC phone line terminations, switchhook, 2-wire to 4-wire hybrid, ringing detection, and full time receive on-hook transmission capability. The CPC5622 is a member of and builds upon Clare’s third generation of LITELINK products with improved insertion loss performance and lower minimum current draw from the phone line. The CPC5622 version of LITELINK III provides concurrent ringing detection and CID monitoring for world wide applications. Both half-wave and full-wave ringing detection are provided for maximum versatility. Applications • • • • • • Computer telephony and gateways, such as VoIP PBXs Satellite and cable set-top boxes V.92 (and other standard) modems Fax machines Voicemail systems Ordering Information Part Number CPC5622A CPC5622ATR Description 32-pin Phone Line Interface, 50/tube 32-pin Phone Line Interface, tape and reel, 1000/reel Figure 1. CPC5622 Block Diagram Isolation Barrier Tx+ Transmit Diff. Amplifier Tx- TIP Transmit Isolation Amplifier MODE Tx. Gain Trim OH Rx. Gain Trim Transconductance Stage 2-4 Wire Hybrid AC/DC Termination Hook Switch Receive Isolation Amplifier RING Rx+ Receive Diff. Amplifier Rx- Ringing Detect Outputs RING RING2 DS-CPC5622 - Rev. 1.0 Rx MUX & Ringing Det. CSNOOP Half Wave Full Wave Snoop Amplifier CSNOOP RSNOOP RSNOOP www.clare.com 1 CPC5622 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 5 2. Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Resistive Termination Application Circuit Part List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Reactive Termination Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9 3. Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 On-hook Operation: OH=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Ringing Signal Reception via the Snoop Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Off-Hook Operation: OH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Initialization Requirement Following Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Setting a Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Mode Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 12 12 12 13 13 13 13 13 13 13 4. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Clare, Inc. Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Manufacturing Assembly Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 17 17 18 18 18 18 Rev. 1.0 CPC5622 1. Electrical Specifications 1.1 Absolute Maximum Ratings Parameter Minimum Maximum Isolation Voltage - Unit 3000 VRMS 150 mA 1 W Continuous Tip to Ring Current (RZDC = 5.2Ω) Total Package Power Dissipation Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. VDD -0.3 6 V Logic Inputs -0.3 VDD + 0.3 V Operating temperature -40 +85 °C Storage temperature -40 +125 °C Unless otherwise specified all specifications are at 25°C and VDD=5.0V. 1.2 Performance Parameter Minimum Typical Maximum Unit Conditions Operating Voltage VDD 3.0 - 5.5 V Host side Operating Current IDD - 9 13 mA Host side Operating Voltage VDDL 2.8 - 3.2 V Operating Current IDDL - 7 8 mA DC Characteristics Line side, derived from tip and ring Line side, drawn from tip and ring while off-hook On-hook Characteristics Metallic DC Resistance 10 - - MΩ Tip to ring, 100 Vdc applied Longitudinal DC Resistance 10 - - MΩ 150 Vdc applied from tip and ring to Earth ground Ringing Signal Detect Level 5 - - VRMS 68 Hz ringing signal applied to tip and ring Ringing Signal Detect Level 28 - - VRMS 15 Hz ringing signal applied across tip and ring Snoop Circuit Frequency Response 166 - >4000 Hz -3 dB corner frequency @ 166 Hz, in Clare application circuit Snoop Circuit CMRR1 - 40 - dB 120 VRMS 60 Hz common-mode signal across tip and ring Ringer Equivalence - 0.01B - REN - dB Per FCC part 68 Longitudinal Balance1 60 Off-Hook Characteristics AC Impedance Longitudinal Balance1 Return Loss - 600 - Ω Tip to ring, using resistive termination application circuit 60 - - dB Per FCC part 68 - 26 - dB Into 600 Ω at 1800 Hz 30 - 4000 Hz -3 dB corner frequency 30 Hz Transmit and Receive Characteristics Frequency Response Rev. 1.0 www.clare.com 3 CPC5622 Parameter Transhybrid Loss Transmit and Receive Insertion Loss Minimum Typical Maximum Unit Conditions - 36 - dB Into 600 Ω at 1800 Hz, with C18 in the resistive termination application circuit 30 Hz to 4 kHz, Resistive termination application circuit with MODE de-asserted. Reactive termination application circuit with MODE asserted. -0.4 0 0.4 dB Average In-band Noise - -126 - dBm/Hz Harmonic Distortion - -80 - dB Transmit Level - - 2.2 VP-P Single-tone sine wave. Or 0 dBm into 600 Ω. Receive Level - - 2.2 VP-P Single-tone sine wave. Or 0 dBm into 600 Ω. RX+/RX- Output Drive Current - - 0.5 mA Sink and source 60 90 120 kΩ Isolation Voltage 3000 - - Vrms Line side to host side, one minute duration Surge Rise Time 2000 - - V/µS No damage via tip and ring Input Low Voltage - - 0.8 VIL Input High Voltage 2.0 - - VIH High Level Input Current - - -120 µA VIN ≤ VDD Low Level Input Current - - -120 µA VIN = GND Output High Voltage VDD -0.4 - - V IOUT = -400 µA Output Low Voltage - - 0.4 V IOUT = 1 mA TX+/TX- Input Impedance 4 kHz flat bandwidth -3 dBm, 600 Hz, 2nd harmonic Isolation Characteristics MODE and OH Control Logic Inputs RING and RING2 Output Logic Levels Specifications subject to change without notice. All performance characteristics based on the use of Clare application circuits. Functional operation of the device at conditions beyond those specified here is not implied. NOTES: 1) This parameter is layout and component tolerance dependent. 4 www.clare.com Rev. 1.0 CPC5622 1.3 Pin Description Pin Name Figure 2. Pinout Function 1 VDD 2 TXSM Transmit summing junction 3 TX- Negative differential transmit signal to DAA from host 4 TX+ Positive differential transmit signal to DAA from host 5 TX Transmit differential amplifier output 6 MODE When asserted low, changes gain of TX path (-7 dB) and RX path (+7 dB) to accommodate reactive termination networks 7 GND Host (CPE) side analog ground 8 OH Assert logic low for off-hook operation 9 RING Half wave ringing detect output signal Host (CPE) side power supply 10 RING2 Full wave ringing detect output signal 11 RX- Negative differential analog signal received from the telephone line. Must be AC coupled with 0.1 µF. 12 RX+ Positive differential analog signal received from the telephone line. Must be AC coupled with 0.1 µF. 13 SNP+ Positive differential snoop input 14 SNP- Negative differential snoop input 15 RXF Receive photodiode amplifier output 16 RX Receive photodiode summing junction 17 VDDL Power supply for line side, regulated from tip and ring. 18 RXS Receive isolation amp summing junction 19 RPB Receive LED pre-bias current set 20 BR- Bridge rectifier return 21 ZDC Electronic inductor DCR/current limit 22 DCS2 DC feedback output 23 DCS1 V to I slope control 24 NTF Network amplifier feedback 25 GAT External MOSFET gate control 26 NTS Receive signal input 27 BR- Bridge rectifier return 28 TXSL Transmit photodiode summing junction 29 ZNT Receiver impedance set 30 ZTX Transmit transconductance gain set 31 TXF Transmit photodiode amplifier output 32 REFL 1.25 Vdc reference Rev. 1.0 www.clare.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD TXSM TXTX+ TX MODE GND OH RING RING2 RXRX+ SNP+ SNPRXF RX REFL TXF ZTX ZNT TXSL BRNTS GAT NTF DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 CPC5622 2. Application Circuits The application circuits that follow address both types of line termination models. A reactive termination application circuit that describes a TBR-21 implementation is shown in Figure 2.2 on page 8. This circuit can be easily adapted for other reactive termination needs. LITELINK can be used with telephone networks worldwide. Some public telephone networks, notably in North America and Japan require a resistive line termination. Other telephone networks as in Europe, China and elsewhere require reactive line termination. 2.1 Resistive Termination Application Circuit Figure 3. Resistive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1µ FB1 600 Ω 200 mA C16 10µ A U1 A R1 (RTX) 80.6K TXTX+ REFL 32 2 TXSM TXF 31 ZTX 1 VDD C13 0.1µ 3 TX- C2 0.1µ 4 TX+ OH ZNT TXSL 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 RING 9 RING RING2 10 RING2 RXRX+ NTF C9 0.1µ BR- 30 29 5 TX A LITELINK R5 (RTXF) 60.4K R75 (RNTX) 261K BR- R12 (RNTF) 24 499K C14 C4 0.1µ 11 RX- DCS1 23 DCS2 C12 (CDCS) 0.027µ BR- ZDC 21 BR- 20 14 SNP- RPB 19 15 RXF RXS BR- R3 (RSNPD) 1.5M C8 (CSNP+) 4 220p C15 0.01µ 500V R20 (RVDDL) 2 5% BR- + DB1 TIP R18 (RZTX) 3.32K C18 15p 3 R10 (RZNT) 301 R4 (RPB) 68.1 C7 (CSNP-) 4 220p Q1 CPC5602C 47 5% BRR76 (RHTF) 200K R8 (R 221K HTX) VDDL 17 R2 (RRXF) 130K R14 (RGAT) R16 (R 3 ZDC) 8.2 18 BR- SP1 1 BR- RING BR- R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R7 (RSNP+2) R45 (RSNP+1) 1.8M 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. ³Optional for enhanced transhybrid loss. 6 R21 (RDCS1B) 6.49M R15 (RDCS2) 22 13 SNP+ R22 (RDCS1A) 6.49M C21 100p BR- (CGAT) 1.69M 0.1µ 12 RX+ 16 RX C10 0.01µ 500V R13 (RNTS) 1M 4Use voltage ratings based on the isolation requirements of your application. www.clare.com Rev. 1.0 CPC5622 2.1.1 Resistive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 µF, 16 V, ±10% 0.1 µF, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C18 (optional) C21 R1 R2 R3 R4 R5 220 pF, ±5% 2 1 1 1 1 1 1 1 1 1 0.01 µF, 500 V, ±10% 0.027 µF, 16 V, ±10% 10 µF, 16 V, ±10% 15 pF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 kΩ, 1/16 W, ±1% 130 kΩ, 1/16 W, ±1% 1.5 MΩ, 1/16 W, ±1% 68.1 Ω, 1/16 W, ±1% 60.4 kΩ, 1/16 W, ±1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 221 kΩ, 1/16 W, ±1% 301 Ω, 1/16 W, ±1% 499 kΩ, 1/16 W, ±1% 1 MΩ, 1/16 W, ±1% 47 Ω, 1/16 W, ±5% 1.69 MΩ, 1/16 W, ±1% 8.2 Ω, 1/8 W, ±1% 3.32 kΩ, 1/16 W, ±1% 2 Ω, 1/16 W, ±5% 6.49 MΩ, 1/16 W, ±1% 10 Ω, 1/16 W, ±5%, or 220 µH inductor 261 kΩ, 1/16 W, ±1% 200 kΩ, 1/16 W, ±1% 600 Ω, 200 mA ferrite bead S1ZB60 bridge rectifier 1 SP1 350 V 1 1 Q1 U1 CPC5602 FET CPC5622 LITELINK 4 Supplier(s) AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 MΩ, 1/10 W, ±1% Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S or similar Shindengen, Diodes, Inc. Bourns (TISP4350H3) or Teccor (P3100SC) Clare 1 Use voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. 2 Use components that allow enough space to account for the possibility of high-voltage arcing. Rev. 1.0 www.clare.com 7 CPC5622 2.2 Reactive Termination Application Circuit Figure 4. Reactive Termination Application Circuit Schematic 3.3 or 5V R23 2 10 C1 1µ FB1 600 Ω 200 mA C16 10µ A U1 A R1 (RTX) 80.6K TXTX+ 1 VDD TXF 3 TX- ZTX C2 0.1µ 4 TX+ ZNT 29 TXSL 28 6 MODE BR- 27 7 GND NTS 26 8 OH GAT 25 RING 9 RING RING2 10 RING2 NTF BR- 30 0.1µ OH C9 0.1µ 31 C13 A RX+ REFL 32 2 TXSM 5 TX RX- LITELINK R5 (RTXF) 60.4K R75 (RNTX) 110K BR- R12 (RNTF) 24 C14 0.1µ 11 RX- C4 0.1µ 12 RX+ DCS2 BR- RPB 15 RXF Q1 CPC5602C 47 5% C15 0.01µ 500V R20 (RVDDL) 2 5% BR- + DB1 BR- 19 R76 (RHTF) 200K R8 (RHTX) RXS TIP - 200K VDDL 17 R4 (RPB) 68.1 R2 (RRXF) 130K R14 (RGAT) R16 (R 3 ZDC) 8.2 BR- 20 18 16 RX C12 (CDCS) 0.027µ ZDC 21 14 SNP- R21 (RDCS1B) 6.49M R15 (RDCS2) 22 1.69M 13 SNP+ R22 (RDCS1A) 6.49M C21 100p BR- (CGAT) 221K DCS1 23 C10 0.01µ 500V R13 (RNTS) 1M BR- R10 59 (RZNT1) R18 (RZTX) 10K BR- SP1 1 BR- RING C20 (CZNT) 0.68µ R11 169 (RZNT2) BR- C7 (CSNP-) 4 220p R3 (RSNPD) 1.5M C8 (CSNP+) 4 220p R6 (RSNP-2) R44 (RSNP-1) 1.8M 1.8M R45 (RSNP+1) R7 (RSNP+2) 1.8M 1.8M NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this Sidactor. Other compliance requirements may require a different part. ²Higher-noise power supplies may require substitution of a 220 µH inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. 3 RZDC sets the loop-current limit, see “Setting a Current Limit” on page 13. Also see Clare application note AN-146 for heat sinking recommendations for the CPC5602C FET. 4 Use voltage ratings based on the isolation requirements of your application. 8 www.clare.com Rev. 1.0 CPC5622 2.2.1 Reactive Termination Application Circuit Part List Quantity Reference Designator Description 1 5 C1 C2, C4, C9, C13, C14 1 µF, 16 V, ±10% 0.1 µF, 16 V, ±10% 2 C7, C8 1 C10, C15 C12 C16 C20 C21 R1 R2 R3 R4 R5 220 pF, ±5% 2 1 1 1 1 1 1 1 1 1 0.01 µF, 500 V, ±10% 0.027 µF, 16 V, ±10% 10 µF, 16 V, ±10% 0.68 µF, 16 V, ±10% 100 pF, 16 V, 10% 80.6 kΩ, 1/16 W, ±1% 130 kΩ, 1/16 W, ±1% 1.5 MΩ, 1/16 W, ±1% 68.1 Ω, 1/16 W, ±1% 60.4 kΩ, 1/16 W, ±1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R6, R7, R44, R45 2 R8 R10 R11 R12 R13 R14 R15 R16 R18 R20 R21, R22 R23 R75 R76 FB1 DB1 200 kΩ, 1/16 W, ±1% 59 Ω, 1/16 W, ±1% 169 Ω, 1/16 W, ±1% 221 kΩ, 1/16 W, ±1% 1 MΩ, 1/16 W, ±1% 47 Ω, 1/16 W, ±5% 1.69 MΩ, 1/16 W, ±1% 8.2 Ω, 1/8 W, ±1% 10 kΩ, 1/16 W, ±1% 2 Ω, 1/16 W, ±5% 6.49 MΩ, 1/16 W, ±1% 10 Ω, 1/16 W, ±5%, or 220 µH inductor 110 kΩ, 1/16 W, ±1% 200 kΩ, 1/16 W, ±1% 600 Ω, 200 mA ferrite bead S1ZB60 bridge rectifier 1 SP1 350 V 1 1 Q1 U1 CPC5602 FET CPC5622 LITELINK 4 1Use 2 Supplier AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1.8 MΩ, 1/10 W, ±1% Panasonic, Electro Films, FMI, Vishay, etc. Murata BLM11A601S or similar Shindengen, Diodes, Inc. Bourns (TISP4350H3) or Teccor (P3100SC) Clare voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. Use components that allow enough space to account for the possibility of high-voltage arcing. Rev. 1.0 www.clare.com 9 CPC5622 3. Using LITELINK As a full-featured telephone line interface, LITELINK performs the following functions: • • • • • • • Asserting OH low causes LITELINK to answer or originate a call by entering the off-hook state. In the off-hook state, loop current flows through LITELINK. DC termination and V/I slope control AC impedance control 2-wire to 4-wire conversion (hybrid) Current limiting Ringing detect signalling reception Caller ID signalling reception Switch hook 3.2 On-hook Operation: OH=1 LITELINK can accommodate specific application features without sacrificing basic functionality or performance. Application features include, but are not limited to: • • • • • • • • High transmit power operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (line intrusion) Battery reversal detection Line presence detection World-wide programmable operation This section of the data sheet describes LITELINK operation in standard configuration for usual operation. Clare offers additional application information on-line (see Section 5 on page 14) for the following topics: • • • • • • Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection EMI considerations Other specific application materials are also referenced in this section as appropriate. 3.1 Switch Hook Control (On-hook and Off-hook States) LITELINK operates in one of two conditions, on-hook and off-hook. In the on-hook condition the telephone line is available for calls. In the off-hook condition the telephone line is engaged. The OH control input is used to place LITELINK in one of these two states. With OH high, LITELINK is on-hook and ready to make or receive a call. Also while on-hook, 10 LITELINK’s ringing detector and CID amplifiers are both active. The LITELINK application circuit leakage current is less than 10 µA with 100 V across ring and tip, equivalent to greater than 10 MΩ on-hook resistance. 3.2.1 Ringing Signal Reception via the Snoop Circuit In the on-hook state (OH not asserted), an internal multiplexer engages the snoop circuitry. This circuit simultaneously monitors the telephone line for two conditions; incoming ringing signal and caller ID data bursts. Refer to the application schematic diagram (see Figure 3 on page 6). C7 (CSNP-) and C8 (CSNP+) provide a high-voltage isolation barrier between the telephone line and SNP- and SNP+ input pins of the LITELINK while coupling AC signals to the snoop amplifier. The snoop circuit “snoops” the telephone line continuously while drawing no dc current. In the LITELINK, the incoming ringing signals are compared to a reference level. When the ringing signal exceeds the preset threshold, the internal comparators generate the RING and RING2 signals which are output from LITELINK at pins 9 and 10, respectively. Selection of which output to use is dependent upon the support logic responsible for monitoring and filtering the ringing detect signals. To reduce or eliminate false ringing detects this signal should be digitally filtered and qualified by the system as a valid ringing signal. A logic low output on RING or RING2 indicates that the LITELINK ringing signal detect threshold has been exceeded. In the absence of any incoming ac signal the RING and RING2 outputs are held high. The CPC5622 RING output signal is generated by a half-wave ringing detector while the RING2 output is generated by a full-wave ringing detector. A half-wave ringing detector’s output frequency follows the frequency of the incoming ringing signal from the Central Office (CO) while a full-wave ringing detector’s output frequency is twice that of the incoming signal. Because RING is the output of a half-wave detector, it will output one logic low pulse per cycle of the ringing frequency. Also, because the RING2 is the output of a www.clare.com Rev. 1.0 CPC5622 full-wave detector it will output two logic low pulses per cycle of the ringing frequency. Hence, the nomenclature RING2 for twice the output pulses. external snoop circuit components from a valid ringing signal. 3.2.3 On-hook Caller ID Signal Reception The set-up of the ringing detector comparator causes the RING output pulses to remain low for most of one half-cycle of the ringing signal and remains high for the entire second half-cycle of the ringing signal. For the RING2 output, the pulses remain low during most of both halves of the ringing cycle and returns high for only a short period near the zero-crossing of the ringing signal. Both of the ringing outputs remain high during the silent interval between ringing bursts. Hysteresis is employed in the LITELINK ringing detector circuit to improve noise immunity. On-hook Caller IDentity (CID) data burst signals are coupled through the snoop components, buffered through LITELINK and output at the RX+ and RXpins. In North America, CID data signals are typically sent between the first and second ringing signal while in other countries the CID information may arrive prior to any other signalling state. In applications that transmit CID after the first ringing burst such as in North American, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: The ringing detection threshold depends on the values of R3 (RSNPD), R6 & R44 (RSNP-), R7 & R45 (RSNP+), C7 (CSNP-), and C8 (CSNP+). The value of these components shown in the application circuits are recommended for typical operation. The ringing detection threshold can be changed according to the following formula: 1. Detect the first full ringing signal burst on RING or RING2. 2. Monitor and process the CID data from the RX outputs. 750mV V RINGPK = ----------------- R SNPD For applications as in China and Brazil where CID may arrive prior to ringing, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: ( R SNP 2 1 + R SNPD ) + ------------------------------------TOTAL 2 ( πf RING C SNP ) Where: • RSNPD = R3 in the application circuits shown in this data sheet. • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits shown in this data sheet. • CSNP = C7 = C8 in the application circuits shown in this data sheet. • And ƒRING is the frequency of the ringing signal. 1. Simultaneously monitor for CID data from the RX outputs and for ringing on RING or RING2. 2. Process the appropriate signalling data. Note: Taking LITELINK off-hook (via the OH pin) disconnects the snoop path from the receive outputs and disables the ringing detector outputs RING and RING2. CID gain from tip and ring to RX+ and RX- is determined by: Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the ringing detection threshold will also change the caller ID gain and the timing of the polarity reversal detection pulse, if used. 6R SNPD GAIN CID ( dB ) = 20 log ------------------------------------------------------------------------------------------------2 1 (R +R ) + ------------------------- 3.2.2 Polarity Reversal Detection in On-hook State Where: The full-wave ringing detector in the CPC5622 makes it possible to detect tip and ring battery polarity reversal using the RING2 output. When the polarity of the battery voltage applied to tip and ring reverses, a pulse on RING2 indicates the event. The system logic must be able to discriminate a single pulse of approximately 1 msec when using the recommended Rev. 1.0 SNP TOTAL SNPD ( πfC SNP ) 2 • RSNPD = R3 in the application circuits in this data sheet. • RSNPTOTAL = the total of R6, R7, R44, and R45 in the application circuits in this data sheet. • CSNP = C7 = C8 in the application circuits in this data sheet. • and ƒ is the frequency of the CID signal www.clare.com 11 CPC5622 The recommended components in the application circuits yield a gain 0.26 dB at 2000 Hz. Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the CID gain will also change the ringing detection threshold and the timing of the polarity reversal detection pulse, if used. application note AN-157, Increased LITELINK III Transmit Power for more information. Figure 5. Differential and Single-ended Receive Path Connections to LITELINK LITELINK Host-side CODEC or Voice Circuit For single-ended receive applications where only one RX output is used, the snoop circuit gain can be adjusted back to 0 dB by changing the value of the snoop series resistors R6, R7, R44 and R45 from 1.8MΩ to 715kΩ. This change results in negligible modification to the ringing detect threshold. RX+ 0.1uF RX+ 0.1uF RX- RX RX- 0.1uF RX+ 3.3 Off-Hook Operation: OH=0 3.3.1 Receive Signal Path Signals to and from the telephone network appear on the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by the LITELINK two-wire to four-wire hybrid then converted to infrared light by the receive path LED. The intensity of the light is modulated by the receive signal and coupled across the electrical isolation barrier to the SELV side photodiode. 3.3.2 Transmit Signal Path On the host equipment (low voltage) side of the barrier, the receive signal is converted by a photodiode into photocurrent. The photocurrent, a linear representation of the receive signal, is amplified and converted to a differential voltage output on RX+ and RX-. The output of the optical amplifier is coupled to a voltage-to-current converter via a transconductance stage where the transmit signal modulates the telephone line loop current. As in the receive path, the transmit gain is calibrated at the factory, limiting insertion loss to 0 ±0.4 dB. Variations in gain are controlled to within ±0.4 dB by factory gain trim. Differential and single-ended transmit signals into LITELINK should not exceed a signal level of 0 dBm referenced to 600 Ω (or 2.2 VP-P). For output power levels above 0dBm consult the application note AN-157, Increased LITELINK III Transmit Power for more information. To accommodate single-supply operation, LITELINK includes a small DC bias on the RX+ and RX- outputs of 1.0 Vdc. Most applications should AC couple the receive outputs as shown in Figure 5. Transmit signals from the CODEC to the TX+ and TXpins of LITELINK should be coupled through capacitors as shown in Figure 6 to minimize dc offset errors. Differential transmit signals are converted to single-ended signals within LITELINK then coupled to the optical transmit amplifier in a manner similar to the receive path. LITELINK may be used for differential or single-ended output as shown in Figure 5. Single-ended use will produce 6 dB less signal output amplitude. Do not exceed 0 dBm referenced to 600 Ω (2.2 VP-P) signal output level with the standard application circuits. See 12 www.clare.com Rev. 1.0 CPC5622 Figure 6. Differential and Single-ended Transmit Path Connections to LITELINK LITELINK Host CODEC or Transmit Circuit 0.1uf TX- 0.1uf TX+ - TXA1 TXA2 refer to the guidelines for FET thermal management provided in AN-146, Guidelines for Effective LITELINK Designs. 3.6 AC Characteristics + 3.6.1 Resistive Termination Applications North American and Japanese telephone line AC termination requirements are met with a resistive 600Ω ac 2-wire termination. For these applications LITELINK’s 2-wire network termination impedance is set by the resistor RZNT (R10) located at the ZNT pin (pin 29) with a value of 301Ω. LITELINK Host CODEC or Transmit Circuit 0.1uf TXA1 N/C TXTX+ + 3.6.2 Reactive Termination Applications Many countries use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. 3.4 Initialization Requirement Following Power-up Line Impedance Model OH must be de-asserted (set logic high) once after power-up for at least 50ms to transfer internal gain trim values within LITELINK. This would be normal operation in most applications. Failure to comply with this requirement will result in transmission gain errors and possibly distortion. 3.5 DC Characteristics The CPC5622 is designed for worldwide applications. Modification of the values of the components at the ZDC, DCS1, and DCS2 pins allow for control of the VI slope characteristics of LITELINK. Selecting appropriate resistor values for RZDC (R16) and RDCS2 (R15) in the provided application circuits enable compliance with various DC requirements. 3.5.1 Setting a Current Limit LITELINK includes a telephone line current limit feature that is selectable by choosing the desired value for RZDC (R16) using the following formula: RS RP Australia China TBR 21 RS 220 Ω 200 Ω 270 Ω RP 820 Ω 680 Ω 750 Ω CP 120 nF 100 nF 150 nF CP Proper gain and termination impedance circuits for a complex impedance requires the use of complex network on ZNT as shown in the “Reactive Termination Application Circuit” on page 8. 3.6.3 Mode Pin Usage Assert the MODE pin low (MODE = 0) introduces a 7 dB pad into the transmit path and adds 7 dB of gain to the receive path. These changes compensate for the gain changes made to the transmit and receive paths necessary for reactive termination implementations. Overall insertion loss with the reactive termination application circuit and MODE asserted is 0 dB. Overall insertion loss with MODE de-asserted (MODE = 1) for the resistive termination application circuit is 0 dB. 1V - + 0.008A I CL Amps = -----------R ZDC Clare recommends using 8.2 Ω for RZDC for most applications, limiting telephone line current to 130 mA. Whether using the recommended value above or when setting RZDC higher for a lower loop current limit Rev. 1.0 www.clare.com 13 CPC5622 4. Regulatory Information LITELINK III can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. LITELINK provides supplementary isolation. Metallic surge requirements are met through the inclusion of a crow bar protection device in the application circuit. Longitudinal surge protection is provided by LITELINK’s optical-across-the-barrier technology and the use of high-voltage components in the application circuit as needed. The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using LITELINK are advised to carefully verify that their end-product design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electrostatic discharges resulting from inadequate protection measures at the board or system level. 5. LITELINK Design Resources 5.1 Clare, Inc. Design Resources The Clare, Inc. web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: LITELINK datasheets and reference designs Application note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-155 Understanding LITELINK Display Feature Signal Routing and Applications 14 www.clare.com Rev. 1.0 CPC5622 6. LITELINK Performance The following graphs show LITELINK performance using the North American application circuit shown in this data sheet. Figure 10.Transmit THD on Tip and Ring Figure 7. Receive Frequency Response at RX 2 0 0 -20 -2 -40 -4 -60 Gain -6 dBm THD+N dB -80 -8 -100 -10 -12 -120 -14 0 500 1000 1500 2000 2500 3000 3500 -140 4000 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 8. Transmit Frequency Response at TX Figure 11.Transhybrid Loss 2 0 0 -5 -10 -2 -15 -4 Gain dBm THL -20 dB -6 -25 -8 -30 -10 -35 -12 -40 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Frequency 2000 2500 3000 3500 4000 Frequency Figure 12.Return Loss Figure 9. Receive THD on RX 0 60 -20 55 -40 50 -60 THD+N dB Return Loss 45 (dB) -80 -100 40 -120 35 -140 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency 30 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Rev. 1.0 www.clare.com 15 CPC5622 Figure 13.Snoop Circuit Frequency Response 5 0 -5 Gain (dBm ) -10 -15 -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Figure 14.Snoop Circuit THD + N 500 1K 1.5K 2K 2.5K 3K 3.5K 4K Hz Figure 15.Snoop Circuit Common Mode Rejection +0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 500 1K 2K 4K Frequency (Hz) 16 www.clare.com Rev. 1.0 CPC5622 7. Manufacturing Information 7.1 Mechanical Dimensions Figure 16. Dimensions 4 Max. 32 PL 10.287 + .254 (0.405 + 0.010) 7.493 + 0.127 (0.295 + 0.005) 7.239 + 0.051 (0.285 + 0.002) 10.363 + 0.127 (0.408 + 0.005) 0.635 x 45 (0.025 x 45 ) 1.016 Typ. (0.040 Typ.) 0.203 (0.008) 0.635 + 0.076 TYP (0.025 + 0.003 TYP) 1.981 + 0.051 (0.078 + 0.002) 2.134 Max. (0.084 Max.) DIMENSIONS A mm (Inches) 0.102 MAX (0.004 MAX) 0.330 + 0.051 (0.013 + 0.002) 9.525 + 0.076 (0.375 + 0.003) Coplanar to A 0.08/(0.003) 32 PL. Figure 17. Recommended Printed Circuit Board Layout 11.380 (0.448) 1.650 (0.065) 0.635 (0.025) 0.330 (0.013) 9.730 (0.383) Rev. 1.0 www.clare.com 17 CPC5622 7.2 Tape and Reel Packaging Figure 18. Tape and Reel Dimensions 330.2 DIA. (13.00 DIA) Top Cover Tape Thickness .102 MAX. (.004 MAX) W = 16.30 MAX (0.642 MAX) B0 = 10.70 (0.421) Top Cover Tape Embossed Carrier Embossment K1 = 2.70 (0.106) P = 12.00 (0.172) A0 = 10.90 (0.430) Feed Direction K1 = 4.90 (0.193) Dimensions mm (inches) 7.3 Manufacturing Assembly Processes 7.3.1 Moisture Reflow Sensitivity 7.3.2 Reflow Profile Clare has characterized the moisture reflow sensitivity of LITELINK using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020 per the labelled moisture sensitivity level (MSL), level 3. Recommended soldering processes are limited to 245°C component body temperature for 10 seconds. 7.3.3 Washing Ultrasonic cleaning of LITELINK will cause permanent damage to the device. Clare does not recommend ultrasonic cleaning or the use of chlorinated solvents. For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5622 - Rev. 1.0 Copyright © 2005, Clare, Inc. LITELINK® is a registered trademark of Clare, Inc. All rights reserved. Printed in USA. 2/18/2005 18