CPC7508 Data Sheet

CPC7508
Line Card Access Switch
INTEGRATED CIRCUITS DIVISION
Features
Description
•
•
•
•
•
•
The CPC7508 is a member of IXYS Integrated
Circuits Division’s next generation Line Card Access
Switch family. When used with ringing SLICs it
provides the necessary functions to replace the two
2-Form-C electromechanical test relays used in
contemporary Fiber To The Home (FTTH) and Optical
Network Unit (ONU) deployments as well as Voice
over IP (VoIP) telephony terminals.
TTL logic level inputs for 3.3V logic interfaces
Smart logic for power up / hot plug state control
Monolithic IC reliability
Low matched RON
Clean, bounce-free switching
Tertiary protection consisting of integrated current
limiting and thermal shutdown for SLIC protection
• +12.5V operation with power consumption 25mW
• Latched logic level inputs, no external drive circuitry
required
• Small 16-pin SOIC
Solid state switches provide the mechanism for tip and
ring line break, drop test, and channel test while
requiring only a single +12V supply for operation.
Interface compatibility with 3.3V or 5V logic for switch
state control is provided by the TTL logic level inputs.
The CPC7508 is designed for fiber access units where
EMR’s are used for test access and line monitoring
functions, but solid-state switches are desired due to
reduced operating noise, lower power consumption
and longer lifetimes.
Applications
•
•
•
•
•
•
Fiber to the Home (FTTH)
Fiber in the Loop (FITL)
VoIP Gateways
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
This monolithic 8-pole solid-state switch is available in
a 16-pin SOIC package.
Ordering Information
Part Number Description
CPC7508B
CPC7508BTR
8-pole LCAS, 16-pin SOIC in tubes (50/tube)
8-pole LCAS, 16-pin SOIC in reels (1000/reel)
Figure 1. CPC7508 Block Diagram
TTEST_IN (TCHAN_TEST)
CPC7508
+12VDC
TTEST_OUT (TDROP_TEST)
1 VDD
8
7
X
Tip
SW7
X SW3
TLINE 6
X SW5
5 TBAT
X
SW1
Secondary
Protection
Ring
Ringing
SLIC
SW2
RLINE 11
12 RBAT
X
X SW4
X SW6
SW8
X
RTEST_OUT (RDROP_TEST)
10
L
A
T
C
H
Switch
Control
Logic
9
2
GND
16
INA
15
INB
14
13
INC
LATCH
3
TSD
RTEST_IN (RCHAN_TEST)
Pb
DS-CPC7508-R05
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1
CPC7508
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.2 TEST_OUT Switches SW3 & SW4 and TEST BRIDGE Switches SW7 & SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.3 TEST_IN Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Protection Circuitry Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
3
4
4
5
6
7
7
7
8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Switch Logic and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Under Voltage Detection and Switch Lock Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2.3 Power Loss Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.1 Current Limiting function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.2 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Tape and Reel Packaging Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R05
CPC7508
INTEGRATED CIRCUITS DIVISION
1. Specifications
1.1 Package Pinout
1.2 Pin Description
CPC7508
VDD 1
16 INA
GND 2
15 INB
TSD 3
14 INC
N/C 4
13 LATCH
TBAT 5
12 RBAT
TLINE 6
11 RLINE
Pin
Name
1
2
3
VDD
+12.5VDC supply
GND
TSD
Ground
I/O, All Off control, Thermal shutdown flag
4
5
N/C
TBAT
No Connect - Do not use
Tip lead to the SLIC
6
TLINE
Tip lead of the line side
7
8
9
Description
TTEST_OUT Tip lead of the Test Out (Drop Test) bus
TTEST_IN Tip lead of the Test In (Channel Test) bus
RTEST_IN Ring lead of the Test In (Channel Test) bus
RTEST_OUT Ring lead of the Test Out (Drop Test) bus
TTEST_OUT 7
10 RTEST_OUT
10
TTEST_IN 8
9 RTEST_IN
11
RLINE
Ring lead of the line side
12
13
14
RBAT
LATCH
INC
Ring lead to the SLIC
Input, Data latch enable
Input, Logic control
15
INB
Input, Logic control
16
INA
Input, Logic control
1.3 Absolute Maximum Ratings
1.4 ESD Rating
Parameter
+12 V power supply (VDD)
Logic input voltage
Logic input to switch output
isolation
Switch open-contact to
ground isolation
Switch open, contact to
contact isolation
Operating relative humidity
Operating temperature
Storage temperature
Minimum Maximum
Unit
-0.3
-0.3
15
6
V
V
-
225
V
-
225
V
-
320
V
5
-40
-40
95
+110
+150
%
C
C
ESD Rating (Human Body Model)
1000 V
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements.
Typical values are characteristic of the device at 25 C
and are the result of engineering evaluations. They are
provided for information purposes only and are not
part of the testing requirements.
Absolute maximum electrical ratings are at 25C.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
R05
Specifications cover the operating temperature range
TA = -40 C to +85 C. Also, unless otherwise specified
all testing is performed with VDD = 12.5 Vdc, logic low
input voltage is 0 Vdc and logic high voltage is 3.3 Vdc.
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CPC7508
INTEGRATED CIRCUITS DIVISION
1.6 Switch Specifications
1.6.1 Break Switches, SW1 and SW2
Parameter
Off-State
Leakage Current
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
Applied voltage maximum ±225 V to ground
All-Off state.
+25 C, VSW (differential) = ±320 V
+85 C, VSW (differential) = ±330 V
0.1
ISW
-
-40 C, VSW (differential) = ±310 V
0.3
0.1
ISW(on) = ±10 mA, ±40 mA
On Resistance
Per SW1 & SW2 On Resistance test
conditions.
RON
VSW (on) = ±10 V, +25 C
DC current limit
VSW (on) = ±10 V, +85 C
ISW
VSW (on) = ±10 V, -40 C
Dynamic current limit
(t  0.5 s)
Break switches on, all other switches off.
Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
ISW
+25 C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±225 V
VSW (TBAT, RBAT) = ±225 V
Logic input to switch
output isolation
+85 C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±225 V
VSW (TBAT, RBAT) = ±225 V
ISW
-40 C, Logic inputs = gnd,
VSW (TLINE, RLINE) = ±225 V
VSW (TBAT, RBAT) = ±225 V
dv/dt sensitivity
4
-
21.1
28
8
10.7
-
-
0.15
0.8
-
300
80
160
-
400
425
-
1.0
-
A
-
0.1
-
0.3
1
A
-
0.1
-
500
-
V/s
RON
+85 C
-40 C
On Resistance
Matching
14.7
+25 C
-
-
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-


mA
R05
CPC7508
INTEGRATED CIRCUITS DIVISION
1.6.2 TEST_OUT Switches SW3 & SW4 and TEST BRIDGE Switches SW7 & SW8
Parameter
Off-State
Leakage Current
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
60
-
85
110

30
50
-
-
0.5
2
-
135
70
85
-
210
250
-
0.7
-
A
1
A
-
V/s
VSW3 (differential) = TLINE to TTEST_OUT
VSW4 (differential) = RLINE to RTEST_OUT
VSW7 (differential) = TTEST_OUT to TTEST_IN
VSW8 (differential) = RTEST_OUT to RTEST_IN
Applied voltage maximum ±225 V to ground
All-Off state.
+25 C, VSW (differential) = ±320 V
+85 C, VSW (differential) = ±330 V
0.1
ISW
-
-40 C, VSW (differential) = ±310 V
0.3
0.1
ISW(on) = ±0 mA, ±10 mA,
On Resistance
+25 C
RON
+85 C
-40 C
On Resistance
Matching
Per On Resistance test conditions.
SW3 & SW4
RON
SW7 & SW8
VSW (on) = ± 10 V, +25 C
DC current limit
VSW (on) = ± 10 V, +85 C
ISW
VSW (on) = ± 10 V, -40 C
Dynamic current limit
(t  0.5 s)
Test_OUT switches on, all other switches
off. Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
ISW
+25 C, Logic inputs = gnd,
VSW3 (TTEST_OUT) = ±225 V
VSW4 (RTEST_OUT) = ±225 V
Logic input to switch
output isolation
+85 C, Logic inputs = gnd,
VSW3 (TTEST_OUT) = ±225 V
VSW4 (RTEST_OUT) = ±225 V
R05
-
mA
0.1
ISW
-
-40 C, Logic inputs = gnd,
VSW3 (TTEST_OUT) = ±225 V
VSW4 (RTEST_OUT) = ±225 V
dv/dt sensitivity
-

0.3
0.1
-
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500
5
CPC7508
INTEGRATED CIRCUITS DIVISION
1.6.3 TEST_IN Switches, SW5 and SW6
Parameter
Off-State
Leakage Current
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW5 (differential) = TTEST_IN to TBAT
VSW6 (differential) = RTEST_IN to RBAT
Applied voltage maximum ±225 V to ground
All-Off state.
+25 C, VSW (differential) = ±320 V
+85 C, VSW (differential) = ±330 V
0.1
ISW
-
-40 C, VSW (differential) = ±310 V
0.2
0.1
ISW(on) = ±10 mA, ±40 mA
On Resistance
+25 C
RON
+85 C
-40 C
On Resistance
Matching
Per SW5 & SW6 On Resistance test
conditions.
RON
VSW (on) = ±10 V, +25 C
DC current limit
VSW (on) = ±10 V, +85 C
ISW
VSW (on) = ±10 V, -40 C
Dynamic current limit
(t  0.5 s)
Break switches on, all other switches off.
Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
ISW
+25 C, Logic inputs = gnd,
VSW5 (TTEST_IN) = ±225 V
VSW6 (RTEST_IN) = ±225 V
Logic input to switch
output isolation
+85 C, Logic inputs = gnd,
VSW5 (TTEST_IN) = ±225 V
VSW6 (RTEST_IN) = ±225 V
ISW
-40 C, Logic inputs = gnd,
VSW5 (TTEST_IN) = ±225 V
VSW6 (RTEST_IN) = ±225 V
dv/dt sensitivity
6
-
-
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
46
70
20
28
-
-
0.35
1.4
-
125
80
95
-
165
250
-
1
-
A
-
0.1
-
0.3
1
A
-
0.1
-
500
-
V/s
-

mA
R05
CPC7508
INTEGRATED CIRCUITS DIVISION
1.7 Digital I/O Electrical Specifications
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Input voltage, Logic low
Input voltage falling
VIL
0.8
1.0
-
Input voltage, Logic high
Input voltage rising
VIH
-
1.7
2.0
Unit
Input Characteristics
V
Input leakage current,
Logic high
VDD = 13.4 V, VHI = 2.4 V
IIH
-
0.1
1
A
Input leakage current,
Logic low
VDD = 13.4 V, VIL = 0.4 V
IIL
-
0.1
1
A
VDD = 13.4 V, ITSD = mA
VTSD_on
-
0
0.4
V
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
-
VDD
11.4
12.5
13.4
V
IDD
-
1.67
2
mA
P
-
20
25
mW
Symbol
Minimum
Typical
Maximum
Unit
TTSD_on
110
125
150
C
TTSD_off
10
-
25
C
Output Characteristics
Output voltage,
TSD Logic low
1.8 Voltage and Power Specifications
Parameter
Voltage Requirements
VDD
Power Specifications
VDD current
VDD = 12.5 V, All states
Power consumption
VDD = 12.5 V, All states, Measure IDD
1.9 Protection Circuitry Specifications
Parameter
Conditions
Thermal Shutdown Specifications
Shutdown activation
temperature
Shutdown circuit
hysteresis
R05
Not production tested - limits are
guaranteed by design and Quality Control
sampling audits.
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CPC7508
INTEGRATED CIRCUITS DIVISION
1.10 Truth Table
Break
Switches
TEST_OUT
Switches
TEST
BRIDGE
Switches
TEST_IN
Switches
0
On
Off
Off
Off
0
1
Off
Off
Off
On
1
0
Off
On
Off
Off
INA
INB
INC
Talk
0
0
TEST_IN
0
TEST_OUT
0
State
TEST_IN Monitor
0
1
1
TEST_OUT Monitor
1
0
0
TEST_IN & OUT
1
0
All-Off
1
1
LATCH
On
Off
Off
On
On
On
Off
Off
1
Off
On
Off
On
0
Off
Off
Off
Off
Off
Off
On
On
Off
Off
0
TEST_IN Bridge
1
1
1
Latched
X
X
X
1
All-Off
X
X
X
X
1
TSD
Z1
Unchanged
0
Off
Off
Z = High Impedance. Because TSD has a high impedance output for a logic high it needs to be pulled up to the logic supply through an external resistor.
Break Switches: SW1 and SW2
TEST_OUT Switches: SW3 and SW4
TEST_IN Switches: SW5 and SW6
TEST BRIDGE Switches: SW7 and SW8
8
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CPC7508
INTEGRATED CIRCUITS DIVISION
2. Functional Description
2.1 Introduction
The CPC7508 LCAS provides the necessary test
access functions for line card interfaces supported by
ringing SLICs in contemporary Fiber In The Loop
(FITL), Fiber To The Home (FTTH) applications and
Voice over Internet Protocol (VoIP).
These applications have a different working
environment than standard traditional Digital Loop
Carrier (DLC) equipment and therefore have unique
requirements. Two significant differences are the
diverse supply voltages and the interface to ringing
SLICs.
The once common 5V supply is generally not available
in the modern short loop products made feasible with
the advent of broadband services. To support
applications where a 5V supply is not available but a
12V supply is, the VDD input power specification for
the CPC7508 has been set accordingly.
Ringing SLICs have replaced the customary standard
SLIC and ringing relay configuration and for the LCAS
to be compatible with a ringing SLIC. the LCAS
internal protection circuits have been removed. This
was essential so as not to clip the ringing waveform
output from the ringing SLIC.
Traditional test access is provided by two pair of test
access switches, TEST_IN and TEST_OUT,
employing the TEST_IN & OUT state. Supplementing
the traditional test access switches is the TEST
BRIDGE switch pair capable of cross connecting the
test busses thereby providing the means to validate
the status of SW1 and SW2, the Break Switches.
2.2 Description
minimum open contact breakdown voltage of 320 V
and a minimum contact to ground breakdown voltage
of 225 V at +25C, sufficiently high with proper
protection to prevent breakdown in the presence of a
transient fault condition.
Integrated into the CPC7508 is a dynamic active
current limit, a DC current limit and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the dynamic
current limiting circuitry and excess power-cross
potentials are restricted by the DC current limit and
thermal shutdown circuits.
To protect the CPC7508 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
it’s tip and ring line terminals to a level below the
maximum breakdown voltage of the switches. With
proper selection of the secondary protector, a line
interface circuit using the CPC7508 will meet all
relevant ITU, LSSGR, TIA/EIA and IEC protection
requirements.
The CPC7508 operates from a single +12.5 V supply
giving the device extremely low power consumption in
any state.
State control is via TTL logic-level compatible inputs
so no additional driver circuitry or level translators are
required. TTL compatible inputs make state control of
the CPC7508 with low voltage logic devices possible.
2.2.2 Logic States
The CPC7508 provides eight distinct states enabling
sufficient configurations to satisfy most design
requirements. They are defined below.
2.2.1 Overview
Because the CPC7508 LCAS utilizes solid-state
switch construction to implement the switching
functions this means no impulse noise is generated
when switching large line potentials. To ensure proper
voice performance the linear break switches SW1 and
SW2 have exceptionally low RON and excellent
matching characteristics. The switches have a
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• Talk. Break switches SW1 and SW2 closed, all other
switches open. This provides a path between the
ringing SLIC and the drop allowing communication
and signalling to pass between the subscriber and
the network.
• Test_IN. Test switches SW5 and SW6 closed, all
other switches open. In this state the SLIC, CODEC
and digital carrier performance can be tested via the
Test In or Channel Test bus
• Test_OUT. Test switches SW3 and SW4 closed and
all other switches open. This state provides the
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9
CPC7508
INTEGRATED CIRCUITS DIVISION
•
•
•
•
•
means to test the drop without the loading effects of
the line feed circuitry.
Test_IN Monitor. Break switches SW1 and SW2
plus the TEST_IN switches SW5 and SW6 closed,
all other switches open. With this state it is possible
to monitor the SLIC output while the SLIC is driving
the line.
Test_OUT Monitor. Break switches SW1 and SW2
plus the TEST_OUT switches SW3 and SW4
closed, all other switches open. With this state it is
possible to monitor the LCAS output while the SLIC
is driving the line.
Test_IN & OUT. TEST_IN switches SW5 and SW6
plus the TEST_OUT switches SW3 and SW4
closed, all other switches open. This state allows
simultaneous testing of the transmission channel
and the drop.
Test_IN BRIDGE. TEST_IN switches SW5 and
SW6 plus TEST BRIDGE switches SW7 and SW8
closed, all other switches open. This state allows
connecting the SLIC output to the Test Out bus to
compare the on-hook TEST_OUT Monitor
evaluation. This makes it possible to determine if
there is a failure with the Break Switches.
All-Off. All switches open. Activation of this state can
be accomplished by setting the appropriate INX
pattern or by pulling the TSD input/output low.
2.3 Switch Logic and Control
2.3.1 Introduction
The CPC7508 uses a three input transparent latch as
the interface between the externally controlled inputs,
INA, INB and INC and the switch logic. Control of the
transparent latch is by means of the LATCH input.
Data output from the latch is fed into the switch control
logic which decodes the inputs and drives the
appropriate switches. To prevent undesirable switch
activity during both start-up and power down the
switch control logic also contains under voltage lock
out detection circuitry to manage the behavior of the
CPC7508. The under voltage lock out release
threshold is internally set to ensure all internal logic is
properly biased before accepting external switch
commands from the INx inputs to control the switch
states. Prior to release of the under voltage lock out,
the switch control logic is conditioned to the All-Off
state
10
2.3.2 Under Voltage Detection and Switch Lock Out
Under voltage detection circuitry in the CPC7508
consists of an internal detector to evaluate the VDD
supply and smart logic to provide for switch state
control during both power up and power loss
transitions.
Any time an unsatisfactory condition causes the VDD
supply to fall below the internally set under voltage
lockout threshold, the smart logic overrides user
switch control by blocking the information at the INx
input pins and conditions the switch control logic to
place the switches into the All-Off state.
2.3.2.1 Power Up Sequence
Upon power up, the under voltage detector and smart
logic become active before the switch driver circuits
and the switch control logic can activate any of the
switches. As the VDD supply starts up, the rising
supply voltage is evaluated by the under voltage
detector to determine when to de-assert the under
voltage switch lock out command. Prior to release of
the lock out command, the smart logic preconditions
the switch control logic for the All-Off state.
The All_Off state is sustained by holding the LATCH
input at a logic high level. This is accomplished by an
external resistor at the LATCH pin which pulls the
input to the supply voltage used by the on-board logic.
The LATCH logic high secures the switch control logic
and the CPC7508 remains in the All-Off state until the
LATCH input is pulled down to a logic low. Prior to the
assertion of a logic low at the LATCH pin, the control
inputs INA, INB and INC must be properly conditioned.
2.3.2.2 Hot Plug and Power Up Circuit Design
Considerations
To facilitate hot plug insertion and power up control the
LATCH pin has an external pull up resistor to the local
logic power rail that will hold a non-driven LATCH pin
at a logic high state. This enables board designers to
use the CPC7508 with FPGAs and other devices that
provide high impedance outputs during power up and
configuration.
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CPC7508
INTEGRATED CIRCUITS DIVISION
2.3.3 Data Latch
There are six possible start up scenarios that can
occur during power up. They are:
1.
2.
3.
4.
5.
6.
All inputs defined at power up & LATCH = 0
All inputs defined at power up & LATCH = 1
All inputs defined at power up & LATCH = Z
All inputs not defined at power up & LATCH = 0
All inputs not defined at power up & LATCH = 1
All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7508 will hold all of it’s switches in the all-off state
during power up. When VDD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7508 will transition
from the all-off state to the state defined by the inputs
when VDD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7508 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all-off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid VDD the
LCAS will revert to one of the legitimate states listed in
the truth tables and there after may randomly change
states based on input pin leakage currents and
loading. Because the LCAS state after power up can
not be predicted with this start up condition it should
never be utilized.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.3.2.3 Power Loss Sequence
For a falling VDD event, the under voltage lock out
detector monitors the supply voltage and upon
reaching the internally set threshold point asserts the
under voltage lock out command. This feature protects
the integrity of the application during power dropouts
by assuring proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed. Upon assertion of the under
voltage lock out command the switch control logic is
conditioned into the All_Off state where it will remain
until VDD recovers and the LATCH input is pulled low.
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The CPC7508 has an integrated transparent data
latch controlled by the LATCH input which can be used
as an enable or a chip select function when the INx
inputs of multiple LCAS devices are connected to
common busses. The latch enable operation is
controlled by TTL input logic levels at the LATCH pin.
Control data is input to the latch via the input pins INA,
INB and INC while the output of the data latch are
internal nodes used for state control. When the
LATCH enable input control pin is a logic 0 (low) the
data latch is transparent and any change to the inputs
will flow directly through the latch to the state control
circuitry and be reflected by a change in the switches
status.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls INA, INB and INC will not
result in a change to the control logic or affect the
existing switch state.
2.4 TSD Pin Description
The TSD pin is a bi-directional I/O structure used as an
output to indicate a thermal shutdown event is in effect
and as an input to condition the device into the All-Off
state.
As an output, this pin indicates the status of the
thermal shutdown circuitry. During normal operation
the output will be pulled up to a logic high by an
external resistor tied to the local logic supply voltage.
Under a line fault situation that creates excess thermal
loading, the CPC7508 will enter thermal shutdown
and a logic low will be output.
As an input, the TSD pin is utilized to place the
CPC7508 into the “All-Off” state by simply pulling the
input to a logic low. IXYS Integrated Circuits Division
recommends the use of an open-collector or an
open-drain type output from the control logic to
manage the All-Off state using the TSD pin.
Forcing TSD to a logic 1 or tying this pin to VCC will not
prevent normal operation of the thermal shutdown
circuitry inside the CPC7508. It will however prevent
the user from detecting a thermal shutdown condition
and is therefore not recommended.
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11
CPC7508
INTEGRATED CIRCUITS DIVISION
Neither the TSD input control nor the TSD output
functions are affected by the latch function. Since
internal thermal shutdown control and external “All-off”
control is not affected by the state of the LATCH
enable input, TSD will override state control.
2.5 Power Supplies
Only a +12 V supply and ground are connected to the
CPC7508. Switch state control is powered exclusively
by the +12 V supply while internal level shifters
provide the necessary translation from the low voltage
inputs to the switch driver circuitry.
2.6 Protection
The CPC7508 uses a combination of current limiting
and a thermal shutdown mechanism to protect the
SLIC device and itself from damage during transient
line faults such as lightning.
For power induction or power-cross fault conditions
the DC current limit function restricts the maximum
current through the switches. Excess power
dissipation during current limiting events will trigger
the thermal shutdown circuit to shut down all of the
switches.
2.6.1 Current Limiting function
If a lightning strike transient occurs when any of the
devices switches are operating, the current will be
restricted by the dynamic current limit response of the
active switches. For instance, during the talk state,
when a 1000V 10x1000 s lightning pulse
(GR-1089-CORE) is applied to the line though a
properly clamped external protector, the current seen
at TLINE and RLINE will be a pulse with a typical
magnitude of 2.5 A and a duration less than 0.5 s.
If a power-cross fault occurs with the device in the talk
state, the current is passed though the break switches
SW1 and SW2 but is limited by the DC current limit
response of the two break switches. The DC current
limit specified over temperature is between 80 mA and
425 mA and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power cross fault condition,
the measured current at TLINE and RLINE will decrease
as the device temperature increases. If the device
temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
12
2.6.2 Thermal Shutdown
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110 C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown events the TSD
pin will output a logic low with a nominal 0 V level. A
logic high is output from the TSD pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the all-off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate shunting the fault current to
ground.
2.7 External Protection Elements
The CPC7508 requires only the over voltage
secondary protector normally used to protect the
ringing SLIC placed on the line side of the LCAS. The
secondary protector must limit voltage transients to
levels that do not exceed the breakdown voltage or
input-output isolation barrier of the CPC7508. Use of a
foldback or crowbar type protector is recommended to
minimize stresses on the LCAS.
Consult IXYS Integrated Circuits Division’s application
note, AN-100, “Designing Surge and Power Fault
Protection Circuits for Solid State Subscriber Line
Interfaces” for equations related to the specifications
of external secondary protectors, fused resistors and
PTCs.
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CPC7508
INTEGRATED CIRCUITS DIVISION
3. Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC7508B
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC7508B
260°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
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13
CPC7508
INTEGRATED CIRCUITS DIVISION
3.5 Package Dimensions
Recommended PCB Land Pattern
10.211 ± 0.254
(0.402 ± 0.010)
1.27
(0.050)
PIN 16
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
9.40
(0.370)
2.00
(0.079)
PIN 1
0.406 ± 0.076
(0.016 ± 0.003)
1.270 TYP
(0.050 TYP)
0.60
(0.024)
2.337 ± 0.051
(0.092 ± 0.002)
45º
0.649 ± 0.102
(0.026 ± 0.004)
0.203 ± 0.102
(0.008 ± 0.004)
0.889 ± 0.178
(0.035 ± 0.007)
0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
DIMENSIONS
mm
(inches)
3.6 Tape and Reel Packaging Dimensions
330.2 DIA.
(13.00 DIA.)
W=16
(0.630)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
B0=10.70
(0.421)
K0=3.20
(0.126)
A0=10.90
(0.429)
P=12.00
(0.472)
K1=2.70
(0.106)
Embossed Carrier
Embossment
NOTES:
1. All dimensions carry tolerances of EIA Standard 481-2
2. The tape complies with all “Notes” for constant dimensions
listed on page 5 of EIA-481-2
Dimensions
mm
(inches)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-DS-CPC7508-R05
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/18/2012
14
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