EB01 - High-Speed SERDES Briefcase Board User`s Guide

High-Speed SERDES Briefcase Board
Evaluation Board for ORSO/ORT82G5, ispGDX2™ and ispPAC ® Devices
User’s Guide
March 2007
Revision: EB01_01.1
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Introduction
This user’s guide describes the Lattice High-Speed SERDES Briefcase Board, a stand-alone evaluation board for
the Lattice ORSO82G5 and ORT82G5 Field Programmable System Chips (FPSCs). The board also contains a
socket and test connections for evaluation of the ispGDX2-256 programmable digital crosspoint switch, and an integrated power supply controller by the ispPAC-POWR1208. The board includes the following features:
• Stand-alone power source
• ispVM® programming support
• On-board reference clock sources (external clock source can be used)
• Discrete high speed interface SMA test points and clock connections
• Simulated matched backplane controlled impedance test runs
The contents of this user’s guide include top level functional descriptions of the various portions of the evaluation
board, descriptions of all connectors, diodes and switches and a complete set of schematics for version 1.1 of the
board. Figure 1 shows the functional partitioning of the board.
Figure 1. Lattice High-Speed SERDS Briefcase Board
ORCAstra Interface
Stripline
DIP Switches
Stripline
ispGDX2
Device
ispGDX2
SERDES I/O
ORSO/ORT82G5
SERDES I/O
Logic
Analyzer
Connectors
ORSO/ORT
82G5
Device
LEDs
Clocks
Programming
Interface
ispPACPOWR1208
Device
Power
The evaluation board is also supported by the ORCAstra™ graphical user interface (GUI). ORCAstra enables the
user to configure bits on the control registers of the FPSC devices via a PC. For more information, refer to the
ORCAstra Users Manual available on the Lattice web site at www.latticesemi.com. The Lattice web site also contains further information about the Lattice devices used on this board, including device data sheets and application
notes.
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Electrical, Mechanical and Environmental Specifications
The nominal board dimensions are 12 inches by 12 inches. The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: < 95% without condensation
Regulated power is available from on-board supplies operated from a wall-type 5V supply. Alternately, power may
be supplied from an external source. 3.3V, 2.5V, 1.8V and 1.5V power buses are supplied.
The devices may be driven by the on-board 156MHz oscillator or, to allow operation at different speeds, from independent differential clock sources. When the clock is sourced from the internal oscillator, a trigger output for test
equipment is available.
In addition to the high-speed SMA connectors, five logic analyzer connections are supplied for Agilent P/N 0165063203 isolation adapters or equivalents. Standard headers and DIP switches are provided for setup of the evaluation environment, and LEDs are provided to indicate current board and device status. Connections are provided
both to device pins with dedicated functions, and to general purpose I/Os from the FPGA portion of the FPSC.
Jacks, Connectors, Diodes and Switches
Bitstream Configuration Connectors
The following connectors are used for configuration and programming.
Table 1. Programming Connections
Jack Number
Size
J1
8 pins (6 used)
ispVM Download - FPSCs and ispGDX2
J4
8 pins (6 used)
ORCA® Download (not populated)
J60
8 pins (6 used)
ispVM Download - ispPAC-POWR1208
Function
Notes:
1. LEDs are used to indicate the status of FPSC and ispGDX2 downloads.
2. The preference selections shown in Figure 2 are recommended for generating ORCA bitstreams. Note particularly the selections of the “Cycle 2” and “Cycle 4” options.
3. Programming jacks J1 and J60 are intended for use with the Lattice ispDOWNLOAD® Cable,
type pDS4102-DL2.
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 2. ispVM Preference Settings for ORCA Bitstreams
Note: With some operating system configurations, the ispVM software will generate failure and error messages
related to the USB when programming is first attempted. If this occurs, do the following:
1. Click on Options in the ispVM toolbar and select Cable and I/O Port Setup
2. Verify that “Cable Type” is “USB” and “Port Setting” is “Ezusb-0”
3. Unplug the USB cable from the system running ispVM
4. Replug the USB cable into the system running ispVM
5. Click OK
The device should now program successfully.
ORCAstra Interface Connectors
The following connectors are used to interface with the ORCAstra GUI.
Table 2. ORCAstra GUI Connections
Jack Number
Size
Function
P1
24 pin
Parallel Port (LPT) ORCAstra Interface
J53
4 pin
Universal Serial Bus (USB) ORCAstra Interface
Note: The USB serial interface device and supporting EPROM are not specifically highlighted on the board photograph in Figure 1.
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Headers
Standard 0.100 headers are provided for interconnecting points on the board. This can be accomplished with 0.100
IDC connectors and ribbon cable for bus connections or 0.025 pin socket patch cords (such as Pomona Electronics
#5948. See www.pomonaelectronics.com for more information).
The following standard headers are used on the evaluation board. Boards are provided with default connections
(ORSO/ORT82G5 listed here. Refer to the schematics in Appendix A for other configuration options).
Table 3. General Purpose Headers
Related
Jack
Number Schematic
Size
Function
Default
Connection
J2
Figure 6
1x2
Tristates ORSO/ORT82G5 (located between J55 and J56)
J3
Figure 6
3x2
Sets up configuration path, U1, U2 or daisy chain (located under
J128)
J37
Figure 8
1x2
ORSO/ORT82G5 PTEMP pin (located to the right of J69)
None
J39
Figure 9
2>1
On-Board Oscillator Power, +3.3 or GND (located below the LEDs and
J54)
[1-2]
J41
Figure 9
2>1
External/On-board Clock Select (located below the LEDs and J54)
[1-2]1
J42
Figure 9
2>1
On-Board Clock __2 (located below the LEDs and J54)
[2-3]1
J45
Figure 10
2>1
ORSO/ORT82G5 REF_CLKA Select for Quad A (located below the
LEDs and J54)
[1-2]
J50
Figure 10
2>1
ORSO/ORT82G5 REF_CLKB Select, for Quad B (located below the
LEDs and J54)
[2-3]
J51
Figure 11
4x2
VDD select for DIP Switches
[1-2]
J52
Figure 12
1x2
Enables ORCAstra Parallel Port Interface (located above J68)
None
J141
Figure 12
3x12
Configures ORCAstra Parallel Port or USB Interface
J61
Figure 14
1x2
ispPAC Input (jumper shorts to ground)
None
J62
Figure 14
1x2
ispPAC Input (jumper shorts to ground)
None
J63
Figure 14
1x2
ispPAC Input (jumper shorts to ground)
None
None
[1-2][3-4][5-6]
[2,3][5-6][8-9]
[11-12][14-15]
[17-18][20-21][23-24]
J64
Figure 14
1x2
ispPAC Input (jumper shorts to ground)
None
J140
Figure 14
1x2
5V connection to evaluation board – remove jumper to configure ispPAC (located to the right of J58 and left of SW8)
[1-2]
J65
Figure 15
4x2
VDDIO0 Select, ORSO/ORT82G5 I/O
[1-8]
J66
Figure 15
4x2
VDDIO1 Select, ORSO/ORT82G5 I/O
[1-8]
J67
Figure 15
4x2
VDDIO2 Select, ORSO/ORT82G5 I/O
[1-5]
J68
Figure 15
4x2
VDDIO6 Select, ORSO/ORT82G5 I/O
[1-5]
J69
Figure 15
4x2
VDDIO5 Select, ORSO/ORT82G5 I/O
[1-5]
J70
Figure 16
2>1
External/Internal Power Select, 3.3V
[1-2]
J71
Figure 16
2>1
External/Internal Power Select, analog 1.5V
[1-2]
J74
Figure 16
2>1
External/Internal Power Select, 2.5V
[1-2]
J76
Figure 16
2>1
External/Internal Power Select, 1.5V
[1-2]
J77
Figure 16
2>1
External/Internal Power Select, 1.8V
J81
Figure 17
4x2
Input Configure, ORCA Primary Clock 0 Test
J84
Figure 17
4x2
Input Configure, ORCA Primary Clock 1 Test
[1-2] [7-8]
J86
Figure 17
4x2
Input Configure, ORCA PLL Clock 0 Test
[1-2] [7-8]
J90
Figure 17
4x2
Input Configure, ORCA PLL Clock 1 Test
[1-2] [7-8]
J92
Figure 17
4x2
Input Configure, ORCA PLL Clock 6 Test
[1-2] [7-8]
5
[1-2]
[1-2] [7-8]
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Table 3. General Purpose Headers (Continued)
Jack
Related
Number Schematic
Size
Function
Default
Connection
J96
Figure 17
4x2
Input Configure, ORCA PLL Clock 7 Test
J98
Figure 18
2>1
External/Internal Power Select, VDD_OB (located left of J69)
[1-2] [7-8]
J100
Figure 18
2>1
External/Internal Power Select, VDD_IB (located left of J69)
[1-2]
J102
Figure 18
2>1
External/Internal Power Select, VDDA (located left of J69)
[1-2]
[1-2]
JP1
Figure 20
2x2
Pushbutton/FPGA GDXRESET Select
None
J116
Figure 21
1x2
ispGDX2 Manual Tristate (jumper tristates ispGDX2), located above
J124
None
J117
Figure 22
4x2
VCC Select, ispGDX2
[2-4]
J118
Figure 22
2>1
External/Internal Power Select, ispGDX2 VCC
[1-2]
J120
Figure 23
4x2
VCCO0 Select, ispGDX2
[1-5]
J121
Figure 23
4x2
VCCO5 Select, ispGDX2
[1-5]
J122
Figure 23
4x2
VCCO6 Select, ispGDX2
[1-5]
J123
Figure 23
4x2
VCCO1 Select, ispGDX2
[1-5]
J124
Figure 23
4x2
VCCO2 Select, ispGDX2
[1-5]
J125
Figure 23
4x2
VCCO3 Select, ispGDX2
[1-5]
J126
Figure 23
4x2
VCCO4 Select, ispGDX2
[1-5]
J127
Figure 23
4x2
VCCJ Select (JTAG voltage)
[1-5]
J128
Figure 23
4x2
VCCO7 Select, ispGDX2
[1-5]
J129
Figure 23
2>1
External/Internal Power Select, ispGDX2 VCCP (located above J131)
[1-2]2
J130
Figure 23
4x2
VCCA Select, ispGDX2 (located to the left of J131)
[2-6]2
1. Errata for Jacks J41 and J42 is as follows: To select an external clock source via SMA connections, remove default jumpers on J41 and J42
and add a connection between J42[1] to J41[2]. This can be accomplished using a 0.25 pin socket 6" patch cord(Pomona P/N 5948 or similar).
2. Lattice recommends VCCP0 and VCCP1 be connected to the appropriate voltage supply, even when the PLL and sysHSI circuits will not be
used.
J54 and TP1
This evaluation board has wiring for a 12x3 header (J54) to support SERDES testing, and a test point (TP1) for
observing the ATMOUT_A signal (see Figure 13). Both are located next to the PASB RESET pushbutton. In general, this header location is not populated.
TP2 through TP9
The evaluation board has wiring for 8 test points (TP2 through TP9) for observing the operation of the ispPAC
PWR1208 Power Sequencer (see Figure 14).
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
SMA Connectors
The following SMA connectors are used on the evaluation board (see Figure 1).
Table 4. ORSO/ORT82G5 Quad A Serial I/O (see Figure 7)
Jack Number
I/O Name
J14
HDIN_AA
J13
HDIP_AA
J16
HDIN_AB
J15
HDIP_AB
J18
HDIN_AC
J17
HDIP_AC
J2O
HDIN_AD
J 19
HDIP_AD
J10
HDOUTN_AA
J7
HDOUTP_AA
J6
HDOUTN_AB
J5
HDOUTP_AB
J9
HDOUTN_AC
J8
HDOUTP_AC
J12
HDOUTN_AD
J11
HDOUTP_AC
Table 5. ORSO/ORT82G5 Quad B Serial I/O (see Figure 8)
I/O Name
Jack Number
HDIN_BA
J22
HDIP_BA
J23
HDIN_BB
J25
HDIP_BB
J26
HDIN_BC
J29
HDIP_BC
J30
HDIN_BD
J33
HDIP_BD
J34
HDOUTN_BA
J21
HDOUTP_BA
J24
HDOUTN_BB
J27
HDOUTP_BB
J28
HDOUTN_BB
J31
HDOUTP_BB
J32
HDOUTN_BB
J35
HDOUTP_BB
J36
Note: Outputs for channels AA and BA have on-board bias_T’s to the VDD_OB supply. Channels AB and AC are
AC coupled with 100ohm pull-up resistors to VDD_OB. The remaining output channels and all input channels are
DC coupled.
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Table 6. Clock SMA Connectors
Jack Number
Related
Schematic
J38
Figure 9
External System Clock Input_P
J40
Figure 9
External System Clock Input_N
J43
Figure 10
ORSO/ORT External Ref Clk A_P Input
J44
Figure 10
ORSO/ORT External Ref Clk A_N Input
J46
Figure 10
ORSO/ORT External Ref Clk B_P Input
J47
Figure 10
ORSO/ORT External Ref Clk B_P Input
J48
Figure 10
Trigger (Clock) Out_P
J49
Figure 10
Trigger (Clock) Out_N
Function
Notes:
1. On-board header connections determine the clock source for the FPSC. The FPSC reference clocks may be
provided by the onboard oscillator, a common external clock source, or multiple external clocks.
2. If an external clock source is used, it must be a differential clock.
3. The trigger outputs are DC coupled in the default configuration. They can be converted to AC coupling by
replacing resistors R204 and R215 with 0.01 µF surface mount capacitors.
Table 7. OECA/PLL Clock Test SMA Connectors (see Figure 17)
Jack Number
Function
J80
True Input, PLL Clock 0 Test
J82
Complementary Input, PLL Clock 0 Test
J83
True Input, Primary Clock 0 Test
J85
True Input, PLL Clock 1 Test
J87
Complementary Input, Primary Clock 0 Test
J88
Complementary Input, PLL Clock 1 Test
J89
True Input, Primary Clock 1 Test
J91
True Input, PLL Clock 6 Test
J93
Complementary Input, Primary Clock 1 Test
J94
Complementary Input, PLL Clock 6 Test
J95
True Input, PLL Clock 7 Test
J97
Complementary Input, PLL Clock 7 Test
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High-Speed SERDES Briefcase Board User’s Guide
Table 8. ispGDX2 SMA Connectors (see Figure 20)
Jack Number
Function
J104
Negative Clock Out, SS_CLKOUT0N
J105
Positive Clock Out, SS_CLKOUT0P
J106
Positive Clock In, SS_CLKIN1P
J107
Negative Clock Out, SS_CLKIN1N
J108
Positive Serial Data In, HSI2A_SINP
J109
Negative Serial Data In, HSI2A_SINN
J110
Positive Serial Data Out, HSI2A_SOUTP
J111
Negative Serial Data Out, HSI2A_SOUTN
J112
Positive Serial Data Out, HSI4B_SOUTP
J113
Negative Serial Data Out, HSI4B_SOUTN
J114
Positive Serial Data In, HSI4B_SINP
J115
Negative Serial Data In, HSI4B_SINN
Table 9. Backplane Test SMA Connectors (see Figure 24 and areas marked “stripline” in Figure 1)
Jack Number
Connection
J132
J133
40” backplane, 8 mil coplanar stripline
J134
J135
40” backplane, 8 mil coplanar stripline
J136
J137
24” backplane, 8 mil coplanar stripline
J138
J139
24” backplane, 8 mil coplanar stripline
All connections have 100Ω balanced impedance between pairs.
Logic Analyzer Connections
The Logic Analyzer connections are connectors for Agilent P/N 01650-63203 isolation adapters or an equivalent.
As shown in Figure 1, each connector has an associated LED that lights when a proper connection is made. See
Figure 1 and Figure 8.
This 10x2 connector is used for ORSO/ORT82G5 Quad B SERDES testing (PSCHAR).
Table 10. Logic Analyzer Connectors
Pin
Signal
Signal
Pin
1
Ground via D3
N/C
2
3
PSCHAR_XCK
ATM_OUT_B
4
5
PSCHAR_CV
PSCHAR_BYTSYNC
6
7
PSCHAR_CKIO1
PSCHAR_WDSYNC
8
9
PSCHAR_CKIO0
PSCHAR_LDIO9
10
11
PSCHAR_LDIO8
PSCHAR_LDIO7
12
13
PSCHAR_LDIO6
PSCHAR_LDIO5
14
15
PSCHAR_LDIO4
PSCHAR_LDIO3
16
17
PSCHAR_LDIO2
PSCHAR_LDIO1
18
19
PSCHAR_LDIO0
Ground
20
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
LA2 and LA3
These 10x2 ORCA to ispGDX2 bus analyzer connectors are used for clock, control, status and reset signals for the
ispGDX2 device (see Figure 20). Each pin is also connected to a general purpose I/O pin in the ORSO/ORT82G5
FPGA logic.
Table 11. LA2 Signals
Pin
Signal
1
Ground via D19
2
N/C
3
N/C
4
CAL
5
GOE0
6
CSLOCK4
7
SYDT2A
8
SYDT4BF
9
CDRLOCK2A
10
LOSS4B
11
RECCLK2A
12
EXLOSS4B
13
EXLOSS2A
14
RECCLK4B
15
LOSS2A
16
CDRLOCK4B
17
SYDT2AF
18
STDT4B
19
CSLOCK2
20
Ground
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High-Speed SERDES Briefcase Board User’s Guide
Table 12. LA3 Signals
Pin
Signal
1
Ground via D20
2
N/C
3
N/C
4
N/C
5
N/C
6
N/C
7
GOE1
8
CDRRST2A
9
GOE2
10
CDRRST4B
11
GOE3
12
FIFO_EMPTY
13
SEL0
14
FIFO_FULL4B
15
SEL1
16
GCLKCE3
17
SEL2
18
GCLKCE2
19
SEL3
20
Ground
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
LA4 and LA5
These 10x2 ORCA to ispGDX2 bus analyzer connectors are used for TX data, RX data and general purpose I/O
signals for the ispGDX2 device (see Figure 21). Each pin is also connected to a general purpose I/O pin in the
ORSO/ORT82G5 FPGA logic.
Table 13. LA4 Signals
Pin
Signal
1
Ground via D21
2
N/C
3
N/C
4
GP_5
5
GP_4
6
GP_3
7
GP_2
8
GP_1
9
GP_0
10
TXD9
11
TXD8
12
TXD7
13
TXD6
14
TXD5
15
TXD4
16
TXD3
17
TXD2
18
TXD1
19
TXD0
20
Ground
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High-Speed SERDES Briefcase Board User’s Guide
Table 14. LA5 Signals
Pin
Signal
1
Ground via D22
2
N/C
3
N/C
4
GP_11
5
GP_10
6
GP_9
7
GP_8
8
GP_7
9
GP_6
10
RXD9
11
RXD8
12
RXD7
13
RXD6
14
RXD5
15
RXD4
16
RXD3
17
RXD2
18
RXD1
19
RXD0
20
Ground
Power Supply Notes
The evaluation board includes five on-board regulated power supplies that operate from an external 5V supply.
Headers are used to allow a choice of voltage for the on-board voltage buses, and to control the relays for either
on-chip or off-chip power for each voltage level. Each supply is fused and has an associated LED indicating that
the voltage is present (see Figure 1). The fuses are Littelfuse Alarm Indicating Fuses, 0481 Series (F1 is Digikey
P/N F725 and the other four fuses are Digikey P/N F723).
The evaluation board also includes an ispPAC-POWR1208 power control device. Programming files for this device
can be developed using Lattice PAC-Designer® software. The top level PAC-Designer screen used for the default
programming of the ispPAC-POWR1208 device is shown in Figure 3.
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High-Speed SERDES Briefcase Board User’s Guide
Figure 3. PAC-Designer Configuration Interface for ispPAC-POWR1208
As provided, the device is programmed to provide power in the sequence shown in Figure 4.
Figure 4. Default Power Sequence for ispPAC-POWR1208 Used on the Evaluation Board
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High-Speed SERDES Briefcase Board User’s Guide
Turret Connectors
The following turret connectors are available for monitoring the power buses on the evaluation board.
Table 15. Turret Connectors
Turret Number
Related
Schematic
T1
Figure 14
5V
T2
Figure 14
Ground
T3
Figure 14
Ground
T4
Figure 14
Ground
T5
Figure 16
3.3V, relay side of fuse
T6
Figure 16
Analog 1.5V, relay side of fuse
T7
Figure 16
3.3V, LED side of fuse
T8
Figure 16
Analog 1.5V, LED side of fuse
Connected to – Power Bus
T9
Figure 16
2.5V, relay side of fuse
T10
Figure 16
2.5V, LED side of fuse
T11
Figure 16
1.5V, relay side of fuse
T12
Figure 16
1.8V, relay side of fuse
T13
Figure 16
1.5V, LED side of fuse
T14
Figure 16
1.8V, LED side of fuse
Banana Jack Connectors
The following banana jack connectors are available for supplying power to the evaluation board from an external
source.
Table 16. Banana Jack Connectors
Jack Number
Related
Schematic
Color
Function
J55
Figure 14
Red
5V external supply (VDD5)
J56
Figure 14
Black
Ground (GND)
J57
Figure 14
Black
Ground (GND)
J59
Figure 14
Black
Ground (GND)
J72
Figure 16
Red
Analog 1.5V external supply (VDDA)
J73
Figure 16
Red
3.3V external supply (VDD33)
J75
Figure 16
Red
2.5V external supply (VDD25)
J78
Figure 16
Red
1.5V external supply (VDD15)
J79
Figure 16
Red
1.8V external supply (VDD18)
J99
Figure 18
Red
VDD_OB external supply (located beneath DIP switches)
J101
Figure 18
Red
VDD_IB external supply (located beneath DIP switches)
J103
Figure 18
Red
VDDA external supply (located beneath DIP switches)
J119
Figure 22
Red
ispGDX2 VCC external supply
J131
Figure 23
Red
ispGDX2 VCCP (analog) external supply
J58
A 2.5 mm male power jack (J58) is provided for connection to the 5V wall power adapter (Condor SA-054A00-1206IP or equivalent). See Figure 14.
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High-Speed SERDES Briefcase Board User’s Guide
Diodes
The following diodes are used on the evaluation board.
Table 17. Diodes
Diode Number
Related
Schematic
D1
Figure 6
Red LED
D2
Figure 6
Green LED
Type
Function/Indication
ORSO/ORT82G5 Configuration INIT
ORSO/ORT82G5 Configuration DONE
D3
Figure 8
Yellow LED
ORSO/ORT82G5 SERDES Test LA Pod OK
D4
Figure 111
Quad Red LED
Outputs from ORSO/ORT82G5 FPGA Logic
D5
Figure 111
Quad Red LED
Outputs from ORSO/ORT82G5 FPGA Logic
D6
Figure 111
Quad Red LED
Outputs from ORSO/ORT82G5 FPGA Logic
D7
1
Figure 11
Quad Red LED
Outputs from ORSO/ORT82G5 FPGA Logic
D8
Figure 12
1N4148
Voltage dropping diode, parallel port input
D9
Figure 12
Green LED
USB Interface Active
D10
Figure 14
Green LED
5V (VDD5) present on evaluation board
D11
Figure 14
1N4148
D12
Figure 14
Green LED
D13
Figure 14
1N5226
D14
Figure 16
Green LED
3.3V (VDD33) present on evaluation board
D23
Figure 16
Green LED
Analog 1.5V (VDDA) present on evaluation board
D16
Figure 16
Green LED
2.5V (VDD25) present on evaluation board
D24
Figure 16
Green LED
1.5V (VDD15) present on evaluation board
D25
Figure 16
Green LED
1.8V (VDD18) present on evaluation board
D19
Figure 20
Yellow LED
ORCA to ispGDX2 Test LA Pod 2 OK
D20
Figure 20
Yellow LED
ORCA to ispGDX2 Test LA Pod 3 OK
D21
Figure 21
Yellow LED
ORCA to ispGDX2 Test LA Pod 4 OK
D22
Figure 21
Yellow LED
ORCA to ispGDX2 Test LA Pod 5 OK
ispPAC VDD bias network
ispPAC Configuration Done
ispPAC VDD bias network, Zener
1. Also see LED and DIP table (Table 19).
16
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Switches
The following switches are used on the evaluation board.
Table 18. Switches
Switch Number
Related
Schematic
Type
SW1
Figure 6
Momentary PB
ORSO/ORT82G5 RESETN
SW2
Figure 6
Momentary PB
ORSO/ORT82G5 PRGMN
Function
SW3[A:D]
1, 2
Figure 11
Quad DIP
Switch Inputs to ORSO/ORT82G5 FPGA Logic
SW4[A:D]
Figure 111, 2
Quad DIP
Switch Inputs to ORSO/ORT82G5 FPGA Logic
SW5[A:D]
Figure 111, 2
Quad DIP
Switch Inputs to ORSO/ORT82G5 FPGA Logic
SW6[A:D]
Figure 111, 2
Quad DIP
Switch Inputs to ORSO/ORT82G5 FPGA Logic
SW7
Figure 13
Momentary PB
SW8
Figure 14
SPDT
ORSO/ORT82G5 PASB_RESETN (SERDES Test)
Disconnects +5 volts from evaluation board
SW11
Figure 14
Momentary PB
PWR1208 RESET
SW9
Figure 20
Momentary PB
GDX-RESET4B
SW10
Figure 20
Momentary PB
GDX-RESET2A
1. Also see the LED and DIP table (Table 19).
2. For the Quad DIP switches, “off” is toward the banana jacks.
LED and DIP Connections to ORSO/ORT82G5
Table 19. LED and DIP Connectors
FPGA Logic Options from ORSO/ORT82G5
FPGA Logic Inputs to ORSO/ORT82G5
FPSC Pin
LED
DIP Switch
FPSC Pin
C21
D4 - Pin 2
SW3A
AL18
E18
D4 - Pin 4
SW3B
AN21
E19
D4 - Pin 6
SW3C
AM21
D19
D4 - Pin 8
SW3D
AN22
D20
D5 - Pin 2
SW4A
AK18
B24
D5 - Pin 4
SW4B
AN23
C23
D5 - Pin 6
SW4C
AP26
C22
D5 - Pin 8
SW4D
AK19
C24
D6 - Pin 2
SW5A
AL21
A27
D6 - Pin 4
SW5B
AM23
B27
D6 - Pin 6
SW5C
AN25
B25
D6 - Pin 8
SW5D
AL22
B26
D7 - Pin 2
SW6A
AL23
A28
D7 - Pin 4
SW6B
AN27
D22
D7 - Pin 6
SW6C
AM25
E22
D7 - Pin 8
SW6D
AP29
17
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Ordering Information
Description
Ordering Part Number
ORT82G5, ispGDX256, and ispPAC Power Manager 1208
Briefcase Board
ORT82G5-G2-PAC-EV
ORSO82G5 Evaluation Board
ORSO82G5-G2-PAC-EV
China RoHS Environment-Friendly
Use Period (EFUP)
10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
March 2003
01.0
Initial release.
March 2007
01.1
Added Ordering Information section.
Change Summary
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
18
19
A
B
C
REF
CLOCK
A
REF
CLOCK
B
SERDES QUAD A
D
5
OSC
SERDES QUAD B
16
16
LEDs
4
PC
GUI
Intf.
PLL & CLOCK SMAs
U1
ORT82G5
4
Power Supplies
DIP Switches
U1S
1/2
SYSTEM
CLOCK
9
General
Purpose
I/O
Tx
ISP VM
3
ispPAC
PWR1208
12
Rx
JTAG Daisy Chain
3
LOGIC ANALYSIS
5
9
2
ISP VM
U2F
2
U2
Backplane Test
Date:
Size
B
Title
Friday, May 02, 2003
Document Number
Briefcase Demo Board
Lattice Semiconductor Corp.
Block Diagram
ISPGDX2
1
HSI SMAs
1
Sheet
1
of
20
Rev
1.1
SSCLKIN
SSCLKOUT
SOUT4B
SIN4B
SOUT2A
SIN2A
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Appendix A. Schematics
The current schematics for the High-Speed SERDES Briefcase Board are given in this appendix.
Figure 5. Lattice High-Speed SERDES Briefcase Board Schematic
20
A
B
C
ispGDX2
3_3
G
5
R17
1
10K
HEADER 3X2
2
4
6
J3
7
1x8 HEADER
1
+
L1
1UH
C2
100NF
3_3
R7
4_75K
4
To Daisy Chain U1 & U2
jumper 1-2, jumper 3-4, jumper 5-6
U2 Only/jumper 1-3/5-6
To program:
U1 Only/jumper 1-2/4-6
1
3
5
J1
RED LED INDICATES PINITN WENT LOW
4_75K
R14
HLMP1700
R
D1
TCK
TMS
TDI
GREEN LED INDICATES COMPLETION
OF CONFIGURATION LOAD
680R
R15
3_3
end view of PC
board ispVM
Connector
Pinout
D12
A4
B19
2
3
4
5
6
8
isp Download
Connection
4_75K
8
7
6
5
4
3
2
1
VDD
TDI
TMS
TCK
TDO
RD_CFG
INIT_N
GND
J4
R115
4_7K
2
1
Do Not
Populate
2
1
J2
R2
4_75K
3
A14
A13
C13
C12
F1
E4
B6
C7
D10
G5
D3
F5
1
D4
3_3
RESET
ORCA 8 Pin JTAG Connector
1039067
3_3
1x2 0.100" Header
TSW-102-07-T-S
Add jumper to Tristate
ORT82G5
R1
4_75K
3_3
3
HDC
LDC_N
DOUT
CCLK
4
2
JTAG
5
J2
3
ORT82G5
6
78
RDY_BUSY_N_RCLK
LVDS_R
DONE
M0
M1
M2
M3
INIT_N
TDO
TCK
TDI
TMS
RD_CFG_N
PRGRM_N
RESET_N
U1A
M3
AJ5
C1
D2
G1
E6
4
2
PRGRMN
2
SW2
3
12
13
9
10
Date:
Size
B
Title
+
R3
3
1
U3
4Y
OUT2
OUT1
Friday, May 02, 2003
Document Number
Briefcase Demo Board
GND
4
6
U4A
2A
2OE_N
1A
1OE_N
3_3
1
1
Sheet
SN74LVC125A
2Y
1Y
Lattice Semiconductor Corp.
Configuration
11
8
6
3
MAX6817
IN2
IN1
3Y
3_3
C1
100NF
+
3_3
SN74LVC125A
4A
4OE_N
3A
3OE_N
U4B
C300
100NF
4_75K
2
4
Momentary Switch
B3F-1150
1
Momentary Switch
B3F-1150
3
SW1
RESETN
1
2
100R
R13
TOP VIEW OF AMP JTAG CONNECTOR
GND
Q1
2N2222
J1
RESETb
GDX2_TMS
GDX2_TCK
AB19
1
2
4_75K
AA4
1
2
1x2 0.100" Header
TSW-102-07-T-S
When programming both devices, VCCOJ cannot be < 2.5V
VCCJ
R8
J143
4
3_3
5
4
2
1
2
R4
4_75K
5
R6
GDX2_TDI
8
R16
4_75K
R9
GDX2_TDO
7
AMP
D2
HLMP1790
3
680R
4_75K
R10
5
VCC
U2D
6
VDD
2
GND
2
R5
4_75K
D
5
14
4
VCC
3
7
2
R11
of
100R
1
R12
100R
20
Rev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 6. Lattice High-Speed SERDES Briefcase Board Schematic
21
A
B
C
5
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J14
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J12
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J9
1
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J6
1
2
3 SMA 50r Connector
1
4 SMA_901_144_8
2
5
3 SMA 50r Connector
J19
4 SMA_901_144_8
5
J20
1
2
3 SMA 50r Connector
1
4 SMA_901_144_8 2
5
3 SMA 50r Connector
J17
4 SMA_901_144_8
5
J18
2
3 SMA 50r Connector
1
4 SMA_901_144_8
2
5
3 SMA 50r Connector
J15
4 SMA_901_144_8
5
J16
1
1
2
3 SMA 50r Connector
SMA_901_144_8
4
5
J13
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J11
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J8
1
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J5
4
4
3
FERRITE/SMT-1210/100uH
R19
51R
L2
SUPPLY_VDDOB
BIAS_T
C8
100NF
R21
100R
R22
100R
3
2
R23
OPEN
R24
100R
2
SUPPLY_VDDOB
R25
100R
Date:
Size
B
Title
51R
51R
NOTE: PLACE
TERMINATIONS
CLOSE TO
DEVICE.
K31
K30
R34
R33
N34
N33
L34
L33
J34
J33
T34
T33
P34
P33
M34
M33
K34
K33
Wednesday, July 09, 2003
Document Number
Briefcase Demo Board
Lattice Semiconductor Corp.
R31
R30
QUADA_REF_CLK_P [6]
QUADA_REF_CLK_N [6]
SUPPLY_VDDOB
Place all components
as close as possible
to device
SUPPLY_VDDOB
R18
OPEN
SUPPLY_VDDOB
SUPPLY_VDDOB
SUPPLY_VDDOB
All 2 inch (max.) matched trace length per pair.
R29
OPEN
C5
100NF C6
100NF
C7
100NF
C4
0.1UF
R26
51R
L3
C3
0.1UF
R20
OPEN
SUPPLY_VDDOB
+
FERRITE/SMT-1210/100uH
1
SUPPLY_VDDOB
2
SUPPLY_VDDOB
3 SMA 50r Connector
4 SMA_901_144_8
R27
R28
5
OPEN OPEN
J10
2
3 SMA 50r Connector
4 SMA_901_144_8
5
J7
1
+
D
5
U1F
1
Sheet
ORT82G5
REFCLKP_A
REFCLKN_A
HDINP_AD
HDINN_AD
HDINP_AC
HDINN_AC
HDINP_AB
HDINN_AB
HDINP_AA
HDINN_AA
U1G
ORT82G5
HDOUTP_AD
HDOUTN_AD
HDOUTP_AC
HDOUTN_AC
HDOUTP_AB
HDOUTN_AB
HDOUTP_AA
HDOUTN_AA
1
3
of
20
Rev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 7. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
5
ALLpairs
mustbe length
matched
& have 100ohm diff
erential
impedence
2
1
3 SM A 50rConnector2
4 SM A_901_144_8 3 SM A 50rConnector
5
4 SM A_901_144_8
J35
5
J36
1
2
1
3 SM A 50rConnecto r 2
4 SM A_901_144_8
3 SM A 50rConnector
5
4 SM A_901_144_8
J33
5
J34
1
2
1
3 SM A 50rConnector2
4 SM A_901_144_8 3 SM A 50rConnector
5
4 SM A_901_144_8
J31
5
J32
1
2
1
3 SM A 50rConnector2
4 SM A_901_144_8 3 SM A 50rConnector
5
4 SM A_901_144_8
J29
5
J30
1
1
2
1
3 SM A 50rConnecto r 2
4 SM A_901_144_8
3 SM A 50rConnector
5
4 SM A_901_144_8
J27
5
J28
2
1
3 SM A 50rConnector2
4 SM A_901_144_8 3 SM A 50rConnector
5
4 SM A_901_144_8
J25
5
J26
1
1
2
3 SM A 50rConnector
4 SM A_901_144_8
5
J24
1
2
3 SM A 50rConnector
4 SM A_901_144_8
5
J21
4
4
C9
0.1UF
R37
O PEN
C10
0.1UF
R34
51R
L5
FERRITE/SM T-1210/
SUPPLY_V
DD OB
R33
O PEN
R32
51R
100uH
L4
FERRITE/SM T-1210/100uH
SUPPLY_V
DD OB
BIAS_T
+
BIAS_T
+
W 33
W 34
Y33
Y34
AA33
AA34
AB33
AB34
AC33
AC34
AD33
AD34
AE33
AE34
J22
HDOU TP_BD
HDOU TN_BD
HDINN _BD
HDINP_BD
HDOU TN_BC
HDOU TP_BC
HDINN _BC
HDINP_BC
HDOU TP_BB
HDOU TN_BB
HDINN _BB
HDINP_BB
330K
R40
3_3
1
1
SM A 50rConnector
SM A_901_144_8
HDOU TN_BA
HDOU TP_BA
U1B
2
3
4
5
3
AF33
AF34
3
HDINN _B A
HDINP_B A
D
5
REFCLKN_B
PSCHAR_LDIO8
PSCHAR_LDIO6
PSCHAR_LDIO4
PSCHAR_LDIO2
PSCHAR_LDIO0
PSCHAR_LDIO1
PSCHAR_LDIO3
PSCHAR_LDIO5
PSCHAR_LDIO7
PSCHAR_LDIO9
PSCHAR_CKIO1
PSCHAR_CKIO0
PSCHAR_XCK
PSCHAR_CV
ATM OU T_B
PSCHAR_BYTSYNC
PSCHAR_W DSYNC
TSW 1X2
1x2 0.100"Header
J37
REXTN_B
REXT_B
REFCLKP_B
2
3 SM A 50rConnector
4 SM A_901_144_8
5
ORT82G 5
J23
PTEM P
AM 3
2
1
2
1
D3
1
3
5
7
9
11
13
15
17
19
NC
D15
D13
D11
D9
D7
D5
D3
D1
GND
51R
51R
R36
R35
2
4
6
8
10
12
14
16
18
20
LED w ill
Light
w hen LA pod
isoriented
correctl
y
H EADER 10X 2
5V
CK
D14
D12
D10
D8
D6
D4
D2
D0
LA 1
R39
HLM P171 9
1K
3_32K
R38
2
D ate:
Size
B
Title
W ednesday,JulyS09,2003
DocumentNumb e r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
SERDES Quad
[6]
B
NOTE: PLACE
TERMINATION S
CLOSE TO
DEVICE.
Q UADB_RE F_CLK_N
Logic Analyzer conn
ecti
on for
Agile
ntP/N 01650-63203 isolati
on
adapters orequivalent .
AP33
AM 31
AM 33
AL32
AK33
AJ30
AK30
AL31
AN32
AP32
AK34
AJ31
AJ33
AH30
AH32
AH31
AJ34
AE30
AE31
AF31
AF30
[6] Q U ADB_REF_CLK_P
2
2
Y
22
1
1
heet
R
1
4
of
20
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 8. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
J3 9
2
100NF
TS W 1X3
3
1
Oscillator
3_3 Control
C16
R42
5
Y1
1_6R
14
+ C15
Q
C17
100NF
XO-500/156M Hz
1
8
10uF
Q_N
VD D
GN D
7
R59
82R
82R
R 202
O PEN
5_0
RST
CLK
CLK
U6
Divide by
R 203
4_7K
1
2
3
NOTE:PLACE
TERM INATIONS
CLOSE T
O
DEVICE.
M C100EL32/SO
130R
R49
3_3
R58
130R
R48
3_3
5_0
8
VC C
VEE
5
4
VBB
Q
Q
+
R61
O PEN
R51
O PEN
+
2
1
C18
10NF
82R
82R
3_3
137R
R68
107R
R64
Jumper 1-2 Selects156MHz XtalOutput
Jumper2-3 Selects78MHz XtalOutput
4
C30 1
10NF
COM _SEL
SEL0
VBB0
D0B_N
D0B
D0A_N
D0A
U5A
M UX
130R
R69
270R
R65
J42
TS W 1X3
3
Q0
Q0_N
3_3
M C100LVEL56
156MHZ/77.8MHZ XTAL
16
17
3
5
R56
O PEN
R44
O PEN
C13
+ + C14
100NF
100NF
6
R60
130R
R50
NOTE:PLACE
TERM INATIONS
CLOSE T
O
DEVICE.
3_3
4
R55
130R
R45
3_3
3_3
7
2
C19
100NF
3_3
3
18
19
82R
R53
130R
R43
3_3
82R
R57
130R
R46
3_3
EXTERNAL CLK
INPU T
2
3_3
Jumper 1-2 SelectsExternalCloc
k Input
from SMA s
Jumper2-3 SelectsOn-Board Cloc
k
NOTE:PLACE
TERM INATIONS
CLOSE T
O
DEVICE.
3_3
137R
107R
R66
R62
D ate:
Size
B
Title
+
R47
O PEN
R41
O PEN
3_3
C 302
10NF
R54
O P EN
1
R52
2
3 SM A 50rConnecto r O PEN
4 SM A_901_144_8
5
J40
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J38
1
2
3_3
100NF
+ C12
M UX
M C100LVEL56
SEL1
VBB1
D1B_N
D1B
D1A_N
D1A
U5B
+
1
2
W ednesday,JulyS09,2003
DocumentNumb e r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
Reference Clocks
130R
270R
R67
J41
TS W 1X3
R63
XTAL/EXTERNAL
15
8
10
9
7
6
100NF
C11
3
4
1
20
VC C
14
VC C
D
5
2
23
3
Q1
Q1_N
VEE
11
3_3
3_3
1
heet
R
R 211
82R
12
13
R 214
130R
1
5
R213
82R
of
REF_CLK_N
20
ev
1.1
[6]
REF_CL K_P [6]
R212
130R
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 9. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
D
J48
0R
J49
1 R 204
0R
5
A SM T CAPACITOR CANBE SUBSTITUTED
FOR R215 & R204 TO AC OU
C PLED THE
TRIGGER OU TPUTS
SM A 50rConnecto r
SM A_901_144_8
2
3
4
5
3_3
R 103
82R
R98
130R
R 206
0R
0R
R 205
R20 9
130R
R 210
82R
3_3
3_3
R94
82R
R92
130R
3_3
R 208
82R
1 R 215
EXTERNAL TR
IGGER OU T
SM A 50rConnector
SM A_901_144_8
2
3
4
5
[16] GDXCLK N
[16] GDXCLK P
R 207
130R
[5] REF_CLK_N
[5] REF_CL K_ P
14
15
12
13
9
10
+ C23
100NF
5
4
U8A
100NF
+ C22
Q2B_N
Q2B
Q1B_N
Q1B
Q0B_N
Q0B
M C100LVEL13D
CLKA_N
CLKA
100NF
+
3_3
3_3
3
VC C
C21
16
VC C
5
Q0A
4
CLKB_N
CLKB
M C100LVEL13D
U8B
Q2A_N
Q2A
Q1A_N
Q1A
Q0A_N
4
20
3_3
R 225
82R
R 224
130R
7
6
17
18
19
3_3
R22 7
82R
R22 6
130R
R83
82R
R82
130R
EXTERNAL REF CLK B
2
3
4
5
O RCA_GP_CLK_N
[13]
O RCA_G P_CLK_P [13]
SM A 50rConnector
SM A_901_144_8
R87
82R
R84
130R
J46
1
J47
QU AD B_EXT_IN_P
3
2
3
4
5
R77
82R
R96
82R
R99
R90
130R 130R
O PEN
R97
R79
2
O PEN
+
O PEN
R91
3_3
+
3
16
17
U7B
D1A_N
J4 5
3_3
M UX
3
2
1
D ate:
Size
B
Title
Active
Low
3
REFCLKB
1
J5 0
Q0
Q0_N
Q1_N
Q1
R80
137R
18
19
12
13
R95
51R
R93
51R
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R10 1
137R
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3_3
QU ADA_REF_ CLK_N
QU ADA_REF_CLK_P
QU ADB_REF_CLK_P
R 105
270R
W ednesday,JulyS09,2003
1
heet
6
QU ADB_REF_ CLK_N
3_3
R 102
107R
Latti
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Briefcase Demo B oard
[3]
[3]
of
[4]
[4]
20
J46Jump er1-2 Selects ExternalReference Clock
InputforQuad Afr
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Jump er2-3 SelectsOn-board
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15
8
10
9
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20
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A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 10. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
D
1_8
2_5
+3.3 V
1_5
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VDD IO
SELECTING DIP INPUT
VOLTAGES
5
6
7
8
5
6
7
8
7
7
6
SW 6D
9
6
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9
4
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10
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12
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1
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6
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9
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2
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1
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8
1
0
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0
11
1
0
11
25
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4.7K
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4
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4
3
2 4.7K
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4 4.7K
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5
6
7
8
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6
7
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3
AL18
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U1H
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DATA_IN_00
DATA_IN_01
DATA_IN_02
DATA_IN_03
DATA_IN_04
DATA_IN_05
DATA_IN_06
DATA_IN_07
DATA_IN_08
DATA_IN_09
DATA_IN_10
DATA_IN_11
DATA_IN_12
DATA_IN_13
DATA_IN_14
DATA_IN_15
2
U1I
2
6
7
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3
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4 RN4D
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heet
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FPGA LEDs& DIPS
7
3 RN4C
2 RN4B
4 RN3D
5
EXB38V471JV
1 RN4A
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3 RN3C
2 RN3B
4 RN2D
5
EXB38V471JV
1 RN3A
8
6
C22 8
7
5
3 RN2C
R
2 RN2B
4 RN1D
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3 RN1C
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7
7
2 RN1B
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8
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1
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3
R
R
R
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D19 8
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NOTE: TH
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ON 2.5V.FIALOW ER VOLTAGE SI APPLIED
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L.
DATA_OUT_15
DATA_OUT_14
DATA_OUT_13
DATA_OUT_12
DATA_OUT_11
DATA_OUT_10
DATA_OUT_09
ORT82G 5 DATA_OUT_08
DATA_OUT_07
DATA_OUT_06
DATA_OUT_05
DATA_OUT_04
DATA_OUT_03
DATA_OUT_02
DATA_OUT_01
DATA_OUT_00
LEDS
1
7
of
20
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 11. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
33pf
C31 +
Y2
+
33pf
C32
ZTT-6M Hz w /cap-Digikey X904
R 113
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1
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RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/TOCKI
RA5/AN4/SS
M CLR/Vpp
OSC1/CLKIN
OSC2/CLKOUT
U10
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
28
2
3
4
5
6
7
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1
2
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4
3
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2
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4
8
7
6
5
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1
2
3
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8
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6
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SELECT Between
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B8
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A4
A3
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11
10
9
8
7
6
5
4
3
2
1
23
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J141
TSW 3X1 2
R 111
4_75K
3_3
S
Friday,M ay 02,2003
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FPSC Config.Interfaces
R 110
4_75K
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IDTQ S3861S O
13
14
15
16
17
18
19
20
21
22
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C28
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13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
20
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TS W 1X2
1x2 0.100"Header
JUMPER MUSTBE ON
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2
1
2
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D
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3
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8
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16
18
20
13
15
19
21
23
23
16
18
22
24
26
26
19
21
29
22
24
25
27
29
R10 9
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33
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28
30
32
32
25
27
35
28
30
35
34
36
31
33
26
34
36
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 12. Lattice High-Speed SERDES Briefcase Board Schematic
27
A
B
C
5
4
2
M om entary Sw it
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1
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4_75K
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3_3
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2
8
35
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23
20
17
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11
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36
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33
28
30
25
27
22
24
19
21
16
18
13
15
10
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17
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11
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28
30
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27
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24
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21
16
18
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ATM OUT_A
D
5
GN D
2
3_3
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SERDES Test
1
9
of
20
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1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 13. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
R 228
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R 222
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3
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1
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5
R 229
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M AX 6817
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2
3
4
5
6
7
8
9
10
11
HVOUT4
HVOUT3
HVOUT2
HVOUT1
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IN1
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VM ON1
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DEVICE
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Connecti
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[12]
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DocumentNumb e r
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1
heet
R
Pow er5V/Pow erSequencer
ispPAC
PW R1208
Pow erSequencer
1x8 HEADER
2
3
4
5
6
8
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R 134
4_75 K
R 135
4_75 K
R 136
4_75 K
R 137
4_75 K
1
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1
1
1
33
32
31
30
29
28
27
26
25
24
23
Turr
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NOTE: PIN 2
ISUSED AS
LINE SIDE
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44
43
42
41
40
39
38
37
36
35
34
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VM ON11
VM ON10
VM ON9
VM ON8
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VM ON6
VM ON5
VM ON4
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OUT5
OUT6
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OUT8
COM P8
COM P7
COM P6
COM P5
COM P4
COM P3
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28
12
13
14
15
16
17
18
19
20
21
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A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 14. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
5
+3.3V
1_8
1_5
3_3
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1
2
3
4
1_8
2_5
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6
7
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Place caps lose
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5
6
7
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3
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1
2
3
4
2x4 0.100"HDR
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5
6
7
8
5
6
7
8
Place caps lose
as c tovice
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3_3
58
59
60
61
100NF
100NF
100NF
100NF
5
6
7
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+C +C +C +C
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AM 5
AM 9
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AN3
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AP2
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Place caps lose
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6
7
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51
52
53
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62
63
64
65
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VDD IO6_BL
VDD IO6_BL
VDD IO6_BL
VDD IO6_BL
VDD IO6_BL
VDD IO6_BL
VDD IO6_BL
VDD IO7_CL
VDD IO7_CL
VDD IO7_CL
VDD IO7_CL
VDD IO7_CL
VDD IO7_CL
VDD IO0_TL
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VDD IO0_TL
VDD IO0_TL
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B15
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C
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C
C
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54
55
56
57
66
67
68
69
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29
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6
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2
3
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5
6
7
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1
2
3
4
1_5
3_3
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VddI/OORT82G 5
Place caps as close to device as possible
5
6
7
8
Place caps as close to device as possible
5
6
7
8
2
1
heet
R
1
11
of
20
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 15. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
D
R 139
O PEN
1uF
C82 +
1_5
R 145
O PEN
100UF
4
CONT
4
1
U18
1uF
1uF
1_5
R 150
O PEN
100UF
C92 +
[10] EN_1_8
C91 +
C90 +
5
4
1
VOUT
CONT
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
CONT
3
1uF
VOUT
TY CO-108505686
3
1uF
[10] RELAY_5
TY CO-108505702
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
U23
1uF
[10] RELAY_5
TY CO-108505710
3
[10] RELAY_5
VOUT
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
NOTE: PLACE ALLAPS
C CLOS
E TO INPUTS
AND OUTPUTS OF REGULATORS
[10] EN_2_5
C81 +
1uF
5_0
1_5
100UF
1
U15
NOTE: PLACE ALLAPS
C CLOS
E TO INPUTS
AND OUTPUTS OF REGULATORS
C80 +
5_0
1uF
1uF
C72 +
[10] EN_3_3
C71 +
C70 +
PLACE ALLCAPS LOSE
C
TO INPUTS
5_0 AND OUTPUTS OF REGULATORS!
0_47R
R138
J70
1
2 2
3
C74
1
2
3
J74
2
C84
1
2
3
J77
2
10NF
+ C93
C94
VDD _RELA Y_1_8
3
1
TSW 1X3
10NF
+ C83
VDD _RELA Y_2_5
3
1
TSW 1X3
10NF
+ C73
VDD _RELA Y_3_3
TSW 1X3
3
1
5
3
4
+5V
NO
NC
U13
GND
COMM
1
2
1
+5V
NO
NC
GND
COMM
1
2
U22
+5V
NO
NC
GND
COMM
1
2
4
J79
111-0702-001
Binding Post
1
5Vdc Coil
,10A Capacit
y Relay
G5LE-14-DC5
5
3
4
111-0702-001
Binding Post
1
J75
5Vdc Coil
,10A Capacit
y Relay
G5LE-14-DC5
5
3
4
U17
111-0702-001
Binding Post
J73
5Vdc Coil
,10A Capacit
y Relay
G5LE-14-DC5
4
5_0
T5
Q5
2N 2222
1
GREEN LE
D
INDICATES
3.3V
PRESENCE
T14
F14 00-ND
Socketed Fuse
V DD _FUSE_1_8
1.8V
T10
GREEN LE
D
INDICATES
2.5 V
PRESENCE
F14 00-ND
Socketed Fuse
V DD _FUSE_2_5
2.5V
R 221
10K
GREEN LE
D
INDICATES
1.8 V
PRESENCE
T12
T9
T7
F14 00-ND
Socketed Fuse
V DD _FUSE_3_3
3.3V
3_3
330R
F6
1_8
270R
3
1uF
C87
R14 6
+
5_0
1uF
1uF
1_5
R14 2
O PEN
100UF
VOUT
CONT
VOUT
CONT
3
3
1uF
1uF
2
J71
2
J76
2
G
D ate:
Size
B
U14
+5V
NO
NC
GND
COMM
J72
111-0702-00 1
Binding Post
1
1
U20
GND
COMM
J78
G 5LE-14-DC 5
+5V
NO
NC
1
2
2
1
Friday,M ay 02,2003
S
DocumentNumb e r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
5_0
T6
Q4
2N2222
R217
10K
GREEN LE
D
INDICATES
VDDA
PRESENCE
R
1
heet
1
12
of
R220
10K
GREEN LE
D
INDICATES
1.5 V
PRESENCE
T13
F140 0-ND
Socketed Fuse
V DD _FUSE_1_ 5
1.5V
1
T8
F1 400-ND
Socketed Fuse
V DD _FUSE_VDD A
VDD A
1.5V
1
T11
5_0
Q3
2N2222
Pow erRegulators
111-0702-001
Binding Post
5
3
4
5Vdc Coil
,10A Capacit
y Relay
C86
Title
10NF
5
3
4
5Vdc Coil
,10A Capacit
y Relay
G5LE-14-DC 5
1_5_A _BAN
VDD _RELA Y_1_5
Q2
IRLR 8103V/TO
1
2
3
C79
TS W 1X3
3
1
10NF
+ C78
O P EN
R20 1
1
2
3
V DD _RE LA Y_ VDD A
3
1
TS W 1X3
[10] EN_FET_1_5
+ C85
[10] RELAY_5
TY CO-10850567 8
3
2
[10] RELAY_5
VOUT
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
TY CO-108505678
4
1
U21
TY CO-108505678
[10] EN _1_5
1uF 100UF
C88 C89
+
+
4
1
U16
TYCO ELECT
RONICS
AUSTIN POW ER
VIN
4 CONT
CT RL_PW R
1
U19
C77 +
[10] EN_1_5_A
C76 +
5_0
NOTE: PLACE ALLAPS
C CLOSE TO INPUTS
AND OUTPUTS FO REGULATORS
C75 +
R14 0
2_5
F4
F2
3
GN D
2
5
0_47R
R141
GN D
2
GN D
2
GN D
2
3_3_ BAN
2_5_ BAN
1_8_ BAN
0_47R
R144
0_47R
R149
R21 9
470R
D25
HLM P1790
3
G
2
GN D
2
GN D
HLM P1790
2
0_47R
30
G
R147
D 16
1_5_ BAN
R21 6
470R
D23
HLM P1790
3
2
G
R21 8
HLM P1790
D24
HLM P179 0
3
470R
D 14
G
2
20
F5
1_5
F3
ev
1.1
VDD _A
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 16. Lattice High-Speed SERDES Briefcase Board Schematic
31
A
B
C
D ate:
Size
B
Title
S
Friday,M ay 02,2003
DocumentNumb er
Briefcase Demo Board
5
Latti
ce Sem iconductorCorp.
ORT82G5 PLL/CLK Test
1
3
5
7
2
4
6
8
J84
2
4
6
8
2
4
6
8
2
4
6
8
13
of
C 111
10NF
TSW-104-07-T-D
10NF
J90
C 103
10NF
TSW-104-07-T-D
10NF
C 107
1
3
5
7
C99
heet
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J93
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8 1
3
5
5
7
J89
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J87
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8 1
5
3
5
7
J83
20
Re v
1.1
R 174
51R
10NF
C 110
R 162
51R
10NF
C 102
R 175
4_75K
4_75K
R 170
3_3
R 163
4_75K
4_75K
3_3
R 158
[6]O RCA_GP_CLK_P
[6]O RCA_GP_CLK_ N
4
R 176
51R
10NF
C 109
R 164
51R
10NF
C 101
4
R17 7
4_75K
R17 1
4_75K
3_3
R16 5
4_75K
R15 9
4_75K
3_3
1
3
5
7
9
11
13
15
J1 42
HEADER 8X 2
2
4
6
8
10
12
14
16
Y5
W5
U4
U5
ORT82G 5
PLCK1C
PLCK1T
PLCK0C
PLCK0T
U1N
PPLL_T
PP LL_C
HPPLL_T
H PPLL_C
PTC K1T
PT CK1C
PTC K0T
PT CK0C
B20
B19
B22
A21
PTCK0C
PTCK0T
PTCK1C
PTCK1T
D
5
3
PLL_CK7C
PLL_CK7T
PLL_CK6C
PLL_CK6T
PLL_CK1C
PLL_CK1T
PLL_CK0C
PLL_CK0T
3
AN1
AM 2
AP4
AP3
C4
B4
F4
G4
R184
4_75K
R182
4_75K
3_3
R178
4_75K
R 185
51R
10NF
C 116
R 179
51R
10NF
C 112
R 167
51R
10NF
C 104
R 155
51R
10NF
C96
3_3
R172
4_75K
R166
4_75 K
R160
4_75 K
3_3
R154
4_75 K
R152
4_75 K
3_3
R 186
4_75 K
4_75 K
3_3
R18 3
R 180
4_75 K
4_75 K
R 187
51R
10NF
C117
R 181
51R
10NF
C113
R169
51R
10NF
C10 5
R157
51R
10NF
C97
3_3
R17 3
R 168
4_75K
4_75K
3_3
R16 1
R 156
4_75K
4_75K
3_3
R15 3
2
2
1
3
5
7
C98
C106
C 114
10NF
C 118
TSW-104-07-T-D
1
3
5
7
J82
1
J85
1
2
SM A 50rConnecto r 3
SM A_901_144_8
4
5
1
J88
J91
J94
J95
J97
2
SM A 50rConnecto r 3
SM A_901_144_8
4
5
1
2
SM A 50rConnecto r 3
4
1 SM A_901_144_8
3
5
5
7
1
2
SM A 50rConnecto r 3
SM A_901_144_8
4
5
1
2
SM A 50rConnecto r 3
4
1 SM A_901_144_8
5
3
5
7
1
2
SM A 50rConnecto r 3
SM A_901_144_8
4
5
C 115
J96
2 210NF
4 4
6 6
8 8
10NF
J80
2
SM A 50rConnecto r 3
4
1 SM A_901_144_8
5
3
5
7
TSW-104-07-T-D
1
3
5
7
1
2
SM A 50rConnecto r 3
1 SM A_901_144_8
4
3
5
5
7
C 108
J92
2 210NF
4 4
6 6
8 8
10NF
TSW-104-07-T-D
1
3
5
7
C10 0
J8 6
2 210NF
4 4
6 6
8 8
10NF
TSW-104-07-T-D
J8 1
2 210NF
4 4
6 6
8 8
C95
1
1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 17. Lattice High-Speed SERDES Briefcase Board Schematic
32
A
B
C
L9
J103
R ed Banana Jack
2300
J101
R ed Banana Jack
2300
1_5
J99
R ed Banana Jack
2300
L8
5
1
1
1UH
1
JACK_SERDES_
JACK _VDD IB
100NF
C 135
+
JACK_V DD O B
100NF
C119
+
1
2
3
1
2
3
3
1
1
2
3
10uF
100NF 10NF
100NF 10NF
C129
+
4
1uF
100NF 10NF
100NF 10NF
10NF
100NF 10NF
100NF
+ C 150 C 152 C15 3 C 154 C 155
+
+
+
+
10NF
100NF 10NF
100NF
10NF
100NF 10NF
3
100NF 10NF
SUPPLY_VDD OB
100NF
C 161
+
SUPPLY_VDD A
SUPPLY_VDD IB
100NF
C 133 C 134
+
+
100NF 10NF
C15 6 C 157 C 158 C15 9 C160
+
+
+
+
+
100NF 10NF
100NF 10NF
C 130 C 131 C132
+
+
+
C 146 C14 7 C 148
+
+
+
100NF 10NF
C 126 C 127 C128
+
+
+
+ C 137 C 139 C 140 C14 1 C 142 C 143 C14 4 C145
+
+
+
+
+
+
+
10NF
+ C 121 C 123 C 124 C125
+
+
+
+ C 149
1uF
1uF
+ C12 0
+ C 136
C 151
10uF
100NF
J102
2
100NF
10uF
C12 2
C 138
100NF
2
J98
2
J1 00
TS W 1X3
ANALOG
VDD _A
TS W 1X3
3
1
TS W 1X3
3
1
AB32
G33
AH33
V34
U34
N32
AC32
AG31
AG34
H32
ORT82G 5
VSSAUX_B
VSSGB_A
VSSGB_B
VSSIB_AB
VSSIB_AC
VSSIB_AD
VSSIB_BA
VSSIB_BB
VSSIB_BC
VSSIB_BD
U1R
SUPPLY_VDD A
SUPPLY_VDD A
SUPPLY_VDD IB
2
D ate:
Size
B
Title
VDD TX_AA
VDD TX_BA
VDD RX_AA
VDD RX_AA
VDD RX_BA
VDD RX_BA
Friday,M ay 02,2003
S
DocumentNumb e r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
SERDESPow er
1
L32
K32
R
1
heet
P32
R32
AD32
AE32
SUPPLY_VDD OB
G34
AH34
VDD GB_ A
VDD GB_ B
1UH
Y32
AA32
VDD AUX_A
VDD AUX_B
1_5
2
L30
N30
P30
T30
VDD IB_AA
VDD IB_AB
VDD IB_AC
VDD IB_AD
VSSOB_AB
VSSOB_AC
VSSOB_AD
VSSOB_BA
VSSOB_BB
VSSOB_BC
VSSOB_BD
V33
U33
M 32
AF32
AG3 2
H30
H33
3
AD30
AB3 0
AA30
W 30
VDD IB_BA
VDD IB_BB
VDD IB_BC
VDD IB_BD
VSSRX_AA
VSSRX_AB
VSSRX_AC
VSSRX_AD
L31
M 31
P31
T31
4
M 30
N31
R31
R30
U31
U30
VDD OB_AA
VDD OB_AB
VDD OB_AC
VDD OB_AC
VDD OB_AD
VDD OB_AD
VSSRX_BA
VSSRX_BB
VSSRX_BC
VSSRX_BD
AD31
AC31
AA31
W 31
D
5
AC30
AB3 1
Y30
Y31
V30
V31
VDD OB_BA
VDD OB_BB
VDD OB_BC
VDD OB_BC
VDD OB_BD
VDD OB_BD
VSSTX_AB
VSSTX_AC
VSSTX_AD
VSSTX_BA
VSSTX_BB
VSSTX_BC
VSSTX_BD
V32
U32
J32
AG3 0
AG3 3
H31
H34
14
of
20
SUPPLY_VDD A
SUPPLY_VDD A
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 18. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
D
10NF
C 230
+
1_5
10NF
C 222
+
1_5
10NF
C 212
+
1_5
10NF
C 204
+
1_5
10NF
C 196
+
1_5
10NF
C 186
+
1_5
10NF
C 174
+
1_5
10NF
C 162
+
1_5
5
100NF
C 231
+
1_5
100NF
C 223
+
1_5
100NF
C 213
+
1_5
100NF
C 205
+
1_5
100NF
C 197
+
1_5
100NF
C 187
+
1_5
100NF
C 175
+
1_5
100NF
C 163
+
1_5
10NF
C 232
+
1_5
10NF
C 224
+
1_5
10NF
C 214
+
1_5
10NF
C 206
+
1_5
10NF
C 198
+
1_5
10NF
C 188
+
1_5
10NF
C 176
+
1_5
10NF
C 164
+
1_5
100NF
C 233
+
1_5
100NF
C 225
+
1_5
100NF
C 215
+
1_5
100NF
C 207
+
1_5
100NF
C 199
+
1_5
100NF
C 189
+
1_5
100NF
C 177
+
1_5
100NF
C 165
+
1_5
10NF
C 234
+
1_5
10NF
C 226
+
1_5
10NF
C 216
+
1_5
10NF
C 208
+
1_5
10NF
C 200
+
1_5
10NF
C 190
+
1_5
10NF
C 178
+
1_5
10NF
C 166
+
1_5
Place capsclose
as to device
as possible
100NF
C 235
+
1_5
100NF
C 227
+
1_5
100NF
C 217
+
1_5
100NF
C 209
+
1_5
100NF
C 201
+
1_5
100NF
C 191
+
1_5
100NF
C 179
+
1_5
100NF
C 167
+
1_5
10NF
C 236
+
1_5
10NF
C 228
+
1_5
10NF
C 218
+
1_5
10NF
C 210
+
1_5
10NF
C 202
+
1_5
10NF
C 192
+
1_5
10NF
C 180
+
1_5
10NF
C 168
+
1_5
4
100NF
C 237
+
1_5
100NF
C 229
+
1_5
100NF
C 219
+
1_5
100NF
C 211
+
1_5
100NF
C 203
+
1_5
100NF
C 193
+
1_5
100NF
C 181
+
1_5
100NF
C 169
+
1_5
4
+
1_5
C220
100UF
+
1_5
C 221
100UF
B34
C33
C34
D33
D34
E32
E33
F32
F34
N16
N17
N18
N19
P16
P17
P18
P19
R16
R17
R18
R19
T13
T14
T15
T20
T21
T22
U13
U14
U15
U20
U21
U22
V13
V14
V15
V20
V21
V22
W 13
W 14
W 15
W 20
W 21
W 22
Y16
Y17
Y18
Y19
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
U1O
3
1_5
1.5V
ORT82G 5
GND
3.3V
3
2
3_3
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN34
AM 34
AL34
AL33
AK3 2
AJ3 2
AB1 9
AB1 8
AB1 7
AB1 6
AA19
AA18
AA17
AA16
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
VDD 15
5
C3
AL4
AK5
AK2 8
AM 32
AK3 1
E3 1
C31
A31
E5
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
33
Y2 2
Y2 1
Y2 0
Y1 5
Y1 4
Y1 3
W 19
W 18
W 17
W 16
V19
V18
V17
V16
U19
U18
U17
U16
T19
T18
T17
T16
R22
R21
R20
R15
R14
R13
P2 2
P2 1
A1
A34
AA13
AA14
AA15
AA20
AA21
AA22
AB13
AB14
AB15
AB20
AB21
AB22
AN33
AP34
B2
B33
E34
N13
N14
N15
N20
N21
N22
P13
P14
P15
P20
C 195
100UF
Friday,M ay 02,2003
S
1
R
heet
Document Numbe r
Briefcase Demo B oard
5
Date:
Latti
ce Sem iconductorCorp.
Pow er& BypassORT82G
+
3_3
100NF
C 184
+
3_3
Size
B
Title
+
3_3
C183
+
10NF
C18 2
+
C 194
100UF
3_3
10NF
100NF
100NF
3_3
C 171
+
3_3
C 170
+
3_3
1
15
10NF
C185
+
3_3
100NF
C172
+
3_3
of
20
10NF
C 173
+
3_3
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 19. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
5
1 R 193
100R
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J114
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J112
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J1 15
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J1 09
H17
H16
G17
H18
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J1 11
H7
H6
1
J7
2
3 SM A 50rConnecto rJ6
4 SM A_901_144_8
5
J1 13
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J108
R 192
100R
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J110
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J1 07
M 17
M 18
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J106
R 191
100R
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J105
4
HSI4B_SOUTP
HSI4B_SOUTN
HSI4B_SINP
HSI4B_SINN
HSI2A_SINN
HSI2A_SINP
HSI2A_SOUTP
HSI2A_SOUTN
SS_CLKIN1N
SS_CLKIN1P
U2B
ispGDX 2
N5
N6
SS_CLKOUT0 P
SS_CLKOUT0 N
R190
100R
CAL
CSLOCK4
SYDT4BF
LOSS4B
EXLOSS4B
RECCLK4B
CDRLOCK4B
STDT4B
CSLOCK2
SYDT2AF
LOSS2A
EXLOSS2A
RECCLK2A
CDRLOCK2A
SYDT2A
GOE0
GOE1
GOE2
GOE3
SEL0
SEL1
SEL2
SEL3
GCLKCE2
GCLKCE3
FIFO_FULL4B
FIFO_EM PTY
CDRRST4B
CDRRST2A
[6] GDXCLK N
[6] GDXCLK P
L4
N1
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J104
ALLTraces must 50
be
ohm impedance
Y
D19
1
JP1
HEADER 2X 2
H22
E3
D1
E1
F2
G11
G10
A9
E21
D22
E22
F20
F13
F12
D13
Y4
B4
C19
AA19
K3
K2
N21
K21
N20
K20
H5
D2
E4
E19
R18 8
1K
HLM P171 9
2
4
2
4
2
3
1
3
1
GCLKCE 0
GCLKCE 1
3
3
3_3
3_3
R19 5
4_75K
ALL pairs must be length
tched ma
& ha
ve 100ohm di
ff
erential
impedence
LED w ill Light
w hen LA od
p
isorientedorrectl
c y
4
6
1
3
5
7
9
11
13
15
17
19
NC
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
3_3
OUT2
OUT1
U24
M AX 6817
IN2
IN1
3
1
C 238
100NF
+
H EADER 10X 2
5V
CK
D14
D12
D10
D8
D6
D4
D2
D0
LA2
LED w ill Light
w hen LA od
p
isorientedorrectl
c y
4_75K
2
3
1
SW 10
2
1
2
M om entary Sw it
ch
B3F-1150
4
3
CDRRST
GDX-RESET
2A
4
2
M om entary Sw it
ch
B3F-1150
Y
D20
CDRRST
GDX-RESET4B
SW9
R 189
1K
HLM P1719
2
1
1
3
5
7
9
11
13
15
17
19
NC
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
D ate:
Size
B
Title
T5
R1
P1
T1
V1
U2
V5
V4
Y1
W1
Y3
Y4
AA1
Y2
AA2
AB1
AC4
AC3
AE3
AD4
AF4
AE4
AF5
AE5
AH3
AK2
AL1
AH5
AG5
PL18B
PL18C
PL18D
PL19A
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
PL23B
PL23C
PL23D
PL24A
PL24B
PL27A
PL27B
PL30A
PL30B
PL32A
PL32B
PL33C
PL33D
PL35A
PL36C
PL36D
PL38A
PL38B
W ednesday,JulyS09,2003
DocumentNumb e r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
ispGDX 2
H EADER 10X 2
5V
CK
D14
D12
D10
D8
D6
D4
D2
D0
LA3
Logic Analyzer conn
ecti
onsforAgile
ntP/N 01650-63203 isolati
on adapters orequivalent
4_75 K
R194
4
R19 6
4_75K
D
5
VC C
5
GN D
2
34
R197
U1E
.
1
heet
R
ORT82G 5
1
16
of
20
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 20. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
5
Rx
Tx
U2G
ispGDX 2
General I/O
D
5
BK4_IO0/TXD0
BK4_IO1/TXD1
BK4_IO2/TXD2
BK4_IO3/TXD3
BK4_IO4/TXD4
BK4_IO5/TXD5
BK4_IO6/TXD6
BK4_IO7/TXD7
BK4_IO8/TXD8
BK4_IO9/TXD9
BK3_IO16/RXD0
BK3_IO17/RXD1
BK3_IO18/RXD2
BK3_IO19/RXD3
BK3_IO20/RXD4
BK3_IO21/RXD5
BK3_IO22/RXD6
BK3_IO23/RXD7
BK3_IO24/RXD8
BK3_IO25/RXD9
BK0_IO0
BK0_IO1
BK0_IO2
BK0_IO3
BK0_IO4
BK0_IO5
BK0_IO6
BK0_IO7
BK0_IO8
BK0_IO9
BK0_IO10
BK0_IO11
GDX2_TOE
3
2
A10
B10
E11
E10
F11
F10
C10
C9
D10
D9
D15
D14
B16
C15
G13
G12
B15
A15
C14
A14
AB13
AA13
V13
V14
U12
U13
W 12
Y13
W 13
Y14
T12
T13
AB10
4
Y
D21
1
GP_4
GP_2
GP_0
TXD8
TXD6
TXD4
TXD2
TXD0
R 198
1K
HLM P1719
2
LED w illLight
when LA pod
isoriented corre
ctly
1
3
5
7
9
11
13
15
17
19
NC
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
H EADER 10X 2
5V
CK
D14
D12
D10
D8
D6
D4
D2
D0
LA4
GP_5
GP_3
GP_1
TXD9
TXD7
TXD5
TXD3
TXD1
3
Y
D22
GP_10
GP_8
GP_6
1
1
3
5
7
9
RXD8 11
RXD6 13
RXD4 15
RXD2 17
RXD019
R 199
1K
HLM P1719
2
LED w illLight
when LA pod
isoriented
corre
ctly
NC
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
H EADER 10X 2
5V
CK
D14
D12
D10
D8
D6
D4
D2
D0
LA5
AL5
AN4
AK6
AK7
AN5
AP5
AK8
AP7
AM 7
AN6
AL8
AL9
AK9
AN8
AM 8
AN9
AP8
AL10
AP9
AM 10
AM 11
AK11
AP10
AN11
AP11
AL12
AK12
AN12
AM 12
AP13
AM 13
AN14
AH1
2
U1T
D ate:
Size
B
Title
ORT82G 5
PB2B
PB3B
PB3C
PB3D
PB4C
PB4D
PB5B
PB5D
PB6A
PB6B
PB6C
PB6D
PB7B
PB7C
PB7D
PB8A
PB8B
PB8D
PB9B
PB9C
PB9D
PB10B
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12D
PB13A
PB13B
PL31A
Add jumperto
m anuall
y
Tris
tate GDX2 devic
e
J1 16
TS W -102-07-T-S
GP_11
GP_9
GP_7
RXD9
RXD7
RXD5
RXD3
RXD1
Logic Analyzer conn
ecti
onsforAgile
ntP/N 01650-63203 isolati
on adapters orequivalent.
4
2
1
35
2
1
ispGDX2/ORT82G5 I/O
Friday,M ay 02,2003
S
Document Numbe r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
1
heet
R
1
17
of
20
ev
1.1
A
B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 21. Lattice High-Speed SERDES Briefcase Board Schematic
36
A
B
C
5
K11
G16
N12
N10
K10
N11
A12
M 10
P11
D19
E5
M 14
M 13
AB21
AB2
AA11
K9
M9
U17
J11
M7
AA2
AB12
AB11
W 19
K14
AA22
J12
R8
F17
H15
M 16
P10
A22
T16
B22
E18
B1
L16
U6
F6
J13
L7
AB1
Y20
AA1
G7
V5
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ispGDX 2
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
4
L20
C21
R10
H12
R12
R9
L8
B3
K8
M 15
K15
R11
R14
P8
M 20
M8
U2A
4
C2
N8
H10
AA20
H11
N15
H13
H14
Y21
R13
Y12
B20
P15
H9
M3
L15
Y11
AA3
C11
C12
J15
Y2
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
VC C
D
5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L11
P14
M2
M 11
J9
M 21
J1
M 12
R15
P13
J10
C20
B12
M 22
C3
W4
AA21
L2
P12
A11
L9
L21
L14
N9
L12
N13
L10
L1
M1
D4
P9
B21
Y3
B2
T7
J14
K22
A21
N14
K12
A2
AA12
H8
B11
L22
K13
AB22
L13
GDX_VC C
3
3
2
100NF
C 240
+
10NF
C 241
+
100NF
C 242
+
10NF
C 243
+
100NF
C24 4
+
10NF
C245
+
100NF
C 246
+
10NF
C 247
+
100NF
C 248
+
10NF
C249
+
100NF
C25 1
+
10NF
C 252
+
100NF
C25 3
+
10NF
C 254
+
100NF
C25 5
+
10NF
C 256
+
100NF
C 257
+
10NF
C258
+
100NF
C 259
+
10NF
C 260
+
GND
COMM
+5V
NO
NC
U25
100NF
C26 2
+
5
3
4
10NF
C 265
+
100NF
C26 6
+
10NF
C 267
+
3
VCC_G DX 2
TSW 1X3
3
1
5_0
2
5
6
7
8
100NF
C 268
+
10NF
C269
+
100NF
C 270
+
10NF
C 271
+
5
6
7
8
+3.3V
+2.5V
+1.8V
+1.5V
J117
D ate:
Size
B
Title
1_5
3_3
+1.8 V
1_8
2_5
+1.5 V
1
R
heet
Friday,M ay 02,2003
S
1
Document Numbe r
Briefcase Demo B oard
Latti
ce Sem iconductorCorp.
ispGDX2-Pow er
1
2
3
4
+2.5V
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
VCC
SELECTING GDX VCC VOLTAGES
Place caps as close to device as possible
100NF
C26 4
+
J1 18
1
2 2
10NF
C 263
+
J1 19
2300
111-0702-001
5Vdc Coil
,10A Capacit
y Relay
G 5LE-14-DC5
2
1
10NF
C 261
+
GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C
10NF
C 250
+
GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C
10NF
C 239
+
GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C GDX_VC C
1
18
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20
ev
1.1
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B
C
D
Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 22. Lattice High-Speed SERDES Briefcase Board Schematic
A
B
C
1_8
2_5
1_5
3_3
VCCP
Select
5_0
1
2
3
4
J1 29
1
2 2
3
5
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
+2.5V
+1.8V
+1.5V
J130
TSW 1X3
3
1
5
6
7
8
5
6
7
8
+ + +
C27 2
C27 3
C27 4
100NF
100NF
100NF
+ + +
C27 8
C27 9
C28 0
+ + +
C28 4
C28 5
C28 6
100NF
100NF
100NF
1_8
1_5
1
2
3
4
1_8
2_5
1_8
2_5
VCCO7
1_8
2_5
VCCO6
VCCO5
VCCO4
VCCA _G DX 2
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
+2.5V
+1.8V
+1.5V
J1 27
C29 0
C29 1
C29 2
100NF
100NF
100NF
3_3
C29 3
C29 4
C29 5
100NF
100NF
100NF
2_5
+ + +
+ + +
VCCO3
VCCO2
VCCO1
+ + +
+ + +
+ + +
100NF
100NF
100NF
C27 5
C27 6
C27 7
100NF
100NF
100NF
C28 1
C28 2
C28 3
C28 7
C28 8
C28 9
100NF
100NF
100NF
100NF
100NF
100NF
VCCO0
5
6
7
8
1_5
3_3
1_5
3_3
1_5
3_3
5
6
7
8
4
VCCJ
1
2
3
4
1
2
3
4
1
2
3
4
1_5
111-0702-001
2300
J1 31
5
3
4
5
6
7
8
5
6
7
8
5
6
7
8
+5V
NO
NC
U26
5
6
7
8
VCCO3
5
6
7
8
5
6
7
8
3_3
+2.5V
GND
COMM
VCCJ
+1.5 V
2
1
L10
+
VCCO2
L3
C22
E20
J21
C17
A20
B14
A3
C6
B9
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
+2.5V
+1.8V
+1.5V
J1 23
VCCO4
1
2
3
4
+1.8 V
5Vdc Coil
,10A Capacit
y Relay
G 5LE-14-DC5
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
+2.5V
+1.8V
+1.5V
TSW -104-07-T-D
2x4 0.100"HDR
J1 26
+3.3V
+2.5V
+1.8V
+1.5V
TSW -104-07-T-D
2x4 0.100"HDR
J1 25
+3.3V
+2.5V
+1.8V
+1.5V
J1 24
1_8
2_5
+3.3V
VDDIO
SELECTING VCCIO
VOLTAGES
U2E
5
6
7
8
1UH
VCCO1
+
VCCO0
+
VCC05
VCC05
VCC05
VCC06
VCC06
VCC06
VCC07
VCC07
VCC07
3
Place caps ase clos
to device as possible
ispGDX 2
VCCJ
VCC02
VCC02
VCC02
VCC03
VCC03
VCC03
VCC04
VCC04
VCC04
5
6
7
8
3
C29 7
Place capsclose
as to device as possible
4
VCC00
VCC00
VCC00
D
5
1
C29 6
100NF
Y22
P21
U20
VCC01
VCC01
VCC01
100NF
AB2 0
Y17
AA14
VCCP 0
VCCP 1
K1
N22
C29 8
37
100NF
5
6
7
8
5
6
7
8
5
6
7
8
C1
J2
F3
Y1
U3
P2
AB3
AA9
Y6
J1 20
+3.3V
+2.5V
+1.8V
+1.5V
5
6
7
8
5
6
7
8
VCCO7
1
2
3
4
1
2
3
4
1
2
3
4
2
1
2
3
4
1_5
3_3
1_5
3_3
1_5
3_3
J1 28
+3.3V
+2.5V
+1.8V
+1.5V
TSW -104-07-T-D
2x4 0.100"HDR
VCCO6
TSW -104-07-T-D
2x4 0.100"HDR
+3.3V
+2.5V
+1.8V
+1.5V
TSW -104-07-T-D
2x4 0.100"HDR
J1 22
+3.3V
+2.5V
+1.8V
+1.5V
TSW -104-07-T-D
2x4 0.100"HDR
J1 21
VCCO5
5
6
7
8
5
6
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Lattice Semiconductor
High-Speed SERDES Briefcase Board User’s Guide
Figure 23. Lattice High-Speed SERDES Briefcase Board Schematic
38
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40 " 8mil min. line width coplanar Stripline trace
Backplane TestPoint
s
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
J134
1
J1 35
2
3
4
5
2
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4
5
24 " 8miln.miline width
coplanar Stripline trace
1
1
2
SM A 50rConnecto r
3 SM A 50rConnector
SM A_901_144_8
4 SM A_901_144_8
5
J1 38
J1 39
4
2
3
4
5
100 ohmbalan ced impedance
between pair
s
2
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SM A_901_144_8 4
5
J1 37
ALL pair
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ALLTrace
s mustbe 50 ohm impedance
5
1
J1 33
SM A 50rConnector
SM A_901_144_8
24 " 8miln.miline width
coplanar Stripline trace
2
3 SM A 50rConnector
4 SM A_901_144_8
5
J1 36
1
40 " 8mil min. line width coplanar Stripline trace
1
SM A 50rConnector
SM A_901_144_8
4
100 ohmbalan ced impedance
between pair
s
1
2
3 SM A 50rConnecto r
4 SM A_901_144_8
5
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W ednesday,JulyS09,2003
Document Numbe r
Briefcase Demo B oard
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Condor_SA-054A00-1-206I P
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Backplane Test/Misc.
AM P-382811-9
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AM P-382811-9
AM P-382811-9
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High-Speed SERDES Briefcase Board User’s Guide
Figure 24. Lattice High-Speed SERDES Briefcase Board Schematic