8BIT 30MSPS ADC GENERAL AL1211H DESCRIPTION FEATURES ¡¤Resolution : 8Bit ¡¤Differential Linearity Error : ¡¾1.0 LSB ¡¤Integral Linearity Error : ¡¾1.0 LSB ¡¤Maximum Conversion Rate : 30MSPS ¡¤Sample & Hold Function Implemented ¡¤Power Supply : 5V Single The AL1211H is a CMOS 8-bit A/D converter for video applications. It is a two-step ping-pong A/D converter which consists of reference resistor-matrix, 4-bit coarse A/D converter and 4-bit fine A/D converter. The maximum conversion rate of AL1211H is 30MSPS and supply voltage is 5V single. TYPICAL APPLICATIONS ¡¤Multi-media applications ¡¤Frame-grabber scanner ¡¤Camcorder ¡¤Digital video (TV/VCR) ¡¤Broadcasting and studio equipments. ¡¤Medical Electronics (ultra-sound and imaging) ¡¤High speed instruments (Digital scope, radar) FUNCTIONAL BLOCK VDDA Coarse Sampling Amplifier DIAGRAM VSSA VDD VSS COUT Latch Latch DO<1> FREF Reference Matrix VIN DO<0> (LSB) Encoder Error Correction Circuit Fine Sampling Amplifier Analog Mux Latch FOUT Data Latches and 3-state Output Buffer DO<3> DO<4> DO<5> Encoder DO<6> Fine Sampling Amplifier DO<7> (MSB) Timing Generator VRT DO<2> VRB Ver 1.1 (Feb. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. CLK AL1211H 8BIT 30MSPS ADC CORE PIN DESCRIPTION I/O TYPE ABBR. NAME I/O TYPE I/O PAD VRT DB pia_bb 2.6V External Reference Top Bias VRB DB pia_bb 0.6V External Reference Bottom Bias VIN AI pia_bb Analog Input Input Span : VRB ~ VRT CLK DI picc_bb Clock Input D<7:0> DO pot2_bb Digital Output VDDA AP vdda Analog Power VSSA AG vssa Analog Ground VDD DP vdd3 Digital Power VSS DG vssd Digital Ground CORE PIN DESCRIPTION ¡¤AI : Analog Input ¡¤DI : Digital Input ¡¤AO : Analog Output ¡¤DO : Digital Output ¡¤AB : Analog Bidirectional ¡¤DB : Digital Bidirectional ¡¤AP : Analog Power ¡¤DP : Digital Power ¡¤AG : Analog Ground ¡¤DG : Digital Ground ¡¤AB : Analog Bidirection ¡¤DB : Digital Bidirection CONFIGURATION VDDA VSSA VDD VSS al1211h VIN CLK SEC ASIC VRB 2 / 11 D<7:0> VRT ANALOG AL1211H 8BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristic Value Symbol Unit Supply Voltage VDD 7.0 V Analog Input Voltage VIN -0.3 to VDD+0.3 V Digital Input Voltage CLK -0.3 to VDD+0.3 V VOH, VOL -0.3 to VDD+0.3 V VRT/VRB -0.3 to VDD+0.3 V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -40 to 125 ¡É Operating Temperature Range Topr 0 to 70 ¡É NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5§Ú resistor (Human body model) RECOMMENDED OPERATING Characteristics CONDITIONS Symbol Min Typ Max Unit Supply Voltage VDDA - VSSA VDD - VSS 4.75 5 5.25 V Supply Voltage Difference VDDA - VDD -0.1 0.0 0.1 V Reference Input Voltage VRT VRB - 2.6 0.6 - V Analog Input Voltage AIN VRB - VRT V Clock High Time Clock Low Time Tpwh Tpwl - 16.6 16.6 - ns VIL VIH 4.5 - 0.5 - V Topr 0 - 70 ¡É Digital Input 'L' Voltage Digital Input 'H' Voltage Operating Temperature NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDD) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 11 ANALOG AL1211H 8BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit - 8 - - Bits - Reference Current IREF 7 10.5 11 mA VRT : 2.6V VRB : 0.6V Differential Linearity Error DLE ¡¾0.2 ¡¾0.3 ¡¾1.0 LSB VIN : 0.6 ~ 2.6V (sine wave 4Mhz) Integral Linearity Error ILE ¡¾0.2 ¡¾0.5 ¡¾1.0 LSB Fs : 1MHz 20MHz Bottom Offset Voltage Error EOB - - 2.5 LSB EOB = VIN(0,1) - VRB Top Offset Voltage Error EOT - - * 15 LSB EOT = VRT - VIN(254,255) Resolution Conditions NOTES 1. Converter Specifications (unless otherwise specified) VDDA=5V VDD=5V VSSA=GND VSS=GND VRT=2.6V VRB=0.6V Ta=25¡É * EOT has large value because of long routing between PAD and VRT. Top offset voltage error can be reduced to 25mV by modifying layout AC ELECTRICAL CHARACTERISTICS Characteristics Conversion Rate Dynamic Supply Current Digital Output Data Delay Signal to Noise Ratio SEC ASIC Symbol Min Typ Max Unit Fs 30 - - MSPS 15 23 30 mA Is = I(VDDA) + I(VDDD) Fs : 30MHz Td - 5 10 ns * Td is Core internal delay See "DELAY TIMING DIAGRAM" SNR 40 43 - dB VIN : 4MHz (Sine Input) Fs : 30MHz Is 4 / 11 Conditions VIN : 4MHz (Sine Input) ANALOG AL1211H 8BIT 30MSPS ADC DELAY TIMING DIAGRAM A1 A2 A3 A4 VIN CLK td DO DO (-2) DO (-1) DO (0) DO (1) 2.5 CLK PIPELINE DELAY TIMING SPECIFICATION Patameter Limit Units Conditions/Comments Td 10 ns Output Data Delay Time Tpd 2.5¡¿CLK ns Pipe lined delay SEC ASIC 5 / 11 ANALOG AL1211H 8BIT 30MSPS ADC FUNCTIONAL DESCRIPTION 1. AL1211H is two-step ping-pong A/D converter with subranging reference resistor matrix. It consists of 4-bit coarse A/D converter and fine A/D converter whose resolution is 4.459 bits approximately. The latching comparators in coarse and fine A/D converters have offset cancellation features built in such as auto-zero and averaging, and the number of comparators are 15 in the coarse converter and 42 in the fine. The sampling operation of fine A/D converter is performed, through 21 analog MUXs, in a ping-pong manner between its two sampling amplifier banks each of which consists of 21 latching comparators. digital output 'DOUT' results. The overall pipeline delay, measured from the sampling instance to the time that the 'DO' comes to be available, is 2.5 clock cycles. 4. AL1211H implements the correction scheme to correct the error which stems from the mismatch between the offset of coarse A/D converter and that of the fine A/D converter. This scheme can handle a error of up to 3LSBs and helps reducing the differential linearity error consequently. 2. One of 16 different sets of reference voltages are switched, according to the states of the coarse comparators, to the fine sampling amplifier banks by the reference resistor matrix. This fact and the use of a CMOS auto-zero comparator surely eliminate the extra pain for implementing high accuracy D/A converter of 8 bit or more, and thus a low-power, high-performance and high speed A/D converter follows. 3. The operation of AL1211H can be stated as follows. (refer to the 'TIMING DIAGRAM' that follows) During the first cycle of external clock the analog input 'VIN' is traced by each converter, and at the falling edge of CLK 'VIN' is sampled and held to be compared with the 16-level coarse reference voltages. The result of comparison in coarse comparator, 'COUT', is latched and chooses a set of fine reference voltage 'FREF' which, to be compared with the sampled analog input, is fed to the fine sampling amplifier banks. The result of the comparison is reproduced by successive comparators with sufficiently large gain and then multiplexed to the latching digital logics in a ping-pong manner. Latching logics in coarse and fine converters refine the results of comparison to generate A/D converter output 'FOUT' and 'COUT' and from which the final SEC ASIC 6 / 11 ANALOG AL1211H 8BIT 30MSPS ADC TIMING DIAGRAM A1 A2 A3 A4 A1 A2 A3 A4 A0 A1 A2 A3 FComp2 FComp1 FComp2 A0 A1 A2 A3 A0 A1 A2 A5 VIN C1T CSamp C2T CComp A0 FREF COUT C1T1 FSamp1 C2T1 FComp1 C1T2 FSamp2 C2T2 FComp2 MUX OUT FComp1 FOUT DATA FComp1 2.5 Clock Pipeline Delay SEC ASIC 7 / 11 ANALOG VIN CLK +5V Analog Power VDDA VSSA GND GND +5V Digital Power VDD VSS 0.6V Bottom Reference VRB al1211h VRT 2.6V Top Reference D<7:0> NOTES : 10uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED CORE DSP HOST : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED MUX BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing ANALOG 8 / 11 SEC ASIC GUIDE EVALUATION CORE AL1211H 8BIT 30MSPS ADC 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased externally through VRT and VRB pins AL1211H 8BIT 30MSPS ADC CORE LAYOUT GUIDE VRT VRB VSS P+ Guardring VDD VIN CROM DO<0> ~ DO<7> Digtal Output Coarse RMATRIX COMP CRORRECT SSA DDA Fine COMP VBB CKGEN FROM NWELL Guardring CLK * It is recommended that you use thick VDDA,VSSA ,VRT, VRB Pin. when connecting to PAD, the path should be kept as short as possible. * Digital power and analog power are separately used. * When P+ Guardring and NWELL Guarding are connected to other blocks, it must be double shielded using N-well and P+ active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. SEC ASIC 9 / 11 ANALOG AL1211H 8BIT 30MSPS ADC PACKAGE CONFIGURATION NOTES 1. You can test ADC function by checking external bidirectional pad connected to internal signal path. 2. ESD (ElectroStatic Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 3. NC denotes "No Connection". D igital Pow e r NC 1 Ref Top 47u Ref Bottom 0.1u 0.1u 47u Analog Pow e r VRT 2 47 NC VRB 3 46 VSS NC 4 45 NC NC 5 44 NC NC 6 43 NC 7 42 NC NC 8 41 NC VSSA 9 40 NC VDDA 47u 0.1u VIN 11 NC 12 NC 13 NC 14 NC 15 I/O PAD Power Clock Signal SEC ASIC 0.1u 0.1u 39 NC 38 NC 37 NC 36 NC 35 NC 34 D < 0> NC 16 33 D < 1> V D D O B 17 32 D < 2> VSSOB 18 31 D < 3> NC 19 30 D < 4> CLK 20 29 D < 5> NC 21 28 D < 6> NC 22 27 D < 7> NC 23 26 NC NC 24 25 NC 10 / 11 47u Digital Output 47u AL1211H NC 10 Analog Input 48 V D D ANALOG AL1211H 8BIT 30MSPS ADC ADC Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Supply voltage V Reference Input voltage V Analog Input voltage Vpp Operating temperature ¡É Integral non-linearity error LSB Differential non-linearity Remarks LSB error Offset voltage error mV (Bottom) Offset voltage error mV (Top) Maximum conversion rate MSPS Dynamic supply current mA Power dissipation mW Signal-to-noise ratio dB Digital output format (Provide detailed description & timing diagram) - What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. the digital VDD can be 3.3V/5V. - What resolution do you need for ADC? - How about the conversion speed(data in¡ædata out)? - How many cycles do exist during the latency of ADC (pipelined delay)? - What's the input range? And what do you need between the single input and differential input? - Can the bus interface be compatible with TTL? - Could you explain external/internal pin configurations as required? Specially requested function list : SEC ASIC 11 / 11 ANALOG