SiliconBlue ICE™ Technology Library Version 2.3 ICE Technology Library - SiliconBlue Technologies Confidential 1 Version 2.0 2.1 Changes Added Version Number to document. Added sections on Default Signal Values for unconnected ports. Modified Added PLL primitives 2.2 Corrected SB_CARRY connections to LUT inputs 2.3 Added iCE40 RAM, PLL primitives ICE Technology Library - SiliconBlue Technologies Confidential 2 Table of Contents Register Primitives .......................................................................................................... 5 SB_DFF ................................................................................................................... 5 SB_DFFE ................................................................................................................. 7 SB_DFFSR .............................................................................................................. 9 SB_DFFR ............................................................................................................... 11 SB_DFFSS ............................................................................................................ 13 SB_DFFS ............................................................................................................... 15 SB_DFFESR .......................................................................................................... 17 SB_DFFER ............................................................................................................ 19 SB_DFFESS .......................................................................................................... 21 SB_DFFES ............................................................................................................ 23 SB_DFFN ............................................................................................................... 25 SB_DFFNE ............................................................................................................ 27 SB_DFFNSR .......................................................................................................... 29 SB_DFFNR ............................................................................................................ 31 SB_DFFNSS .......................................................................................................... 33 SB_DFFNS ............................................................................................................ 35 SB_DFFNESR ....................................................................................................... 37 SB_DFFNER .......................................................................................................... 39 SB_DFFNESS........................................................................................................ 41 SB_DFFNES .......................................................................................................... 43 Combinational Logic Primitives ..................................................................................... 45 SB_LUT4 ............................................................................................................... 45 SB_CARRY ............................................................................................................ 47 Block RAM Primitives .................................................................................................... 49 iCE65 Block RAM ........................................................................................... 49 SB_RAM4K ............................................................................................................ 54 SB_RAM4KNR ....................................................................................................... 54 SB_RAM4KNW ...................................................................................................... 54 SB_RAM4KNRW ................................................................................................... 54 iCE40 Block RAM ........................................................................................... 55 SB_RAM256x16..................................................................................................... 58 SB_RAM256x16NR ............................................................................................... 58 SB_RAM256x16NW ............................................................................................... 58 SB_RAM256x16NRNW ......................................................................................... 58 SB_RAM512x8....................................................................................................... 61 SB_RAM512x8NR ................................................................................................. 61 SB_RAM512x8NW ................................................................................................. 61 SB_RAM512x8NRNW ........................................................................................... 61 SB_RAM1024x4..................................................................................................... 64 SB_RAM1024x4NR ............................................................................................... 64 ICE Technology Library - SiliconBlue Technologies Confidential 3 SB_RAM1024x4NW ............................................................................................... 64 SB_RAM1024x4NRNW ......................................................................................... 64 SB_RAM2048x2..................................................................................................... 67 SB_RAM2048x2NR ............................................................................................... 67 SB_RAM2048x2NW ............................................................................................... 67 SB_RAM2048x2NRNW ......................................................................................... 67 SB_RAM40_4K ...................................................................................................... 68 IO Primitives .................................................................................................................. 70 SB_IO .................................................................................................................... 71 Global Buffer Primitives ................................................................................................. 75 SB_GB_IO ............................................................................................................. 75 SB_GB Primitive .................................................................................................... 76 PLL Primitives ............................................................................................................... 77 iCE65 PLL Primitives ...................................................................................... 77 SB_PLL_CORE...................................................................................................... 77 SB_PLL_PAD......................................................................................................... 80 SB_PLL_2_PAD..................................................................................................... 83 iCE40 PLL Primitives ...................................................................................... 86 SB_PLL40_CORE.................................................................................................. 86 SB_PLL40_PAD..................................................................................................... 90 SB_PLL40_2_PAD................................................................................................. 94 SB_PLL40_2F_CORE ........................................................................................... 97 SB_PLL40_2F_PAD ............................................................................................ 101 Device Configuration Primitives .................................................................................. 106 SB_WARMBOOT ................................................................................................. 106 ICE Technology Library - SiliconBlue Technologies Confidential 4 Register Primitives SB_DFF D Flip-Flop Data: D is loaded into the flip-flop during a rising clock edge transition. D SB_DFF Q C Inputs D Power on State 0 1 X Output C Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL use This register is inferred during synthesis and can also be explicitly instantiated. Verilog Instantiation // SB_DFF - D Flip-Flop. SB_DFF SB_DFF_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data ); // End of SB_DFF instantiation ICE Technology Library - SiliconBlue Technologies Confidential 5 VHDL Instantiation -- SB_DFF - D Flip-Flop. SB_DFF_inst : SB_DFF port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data ); -- End of SB_DFF instantiation ICE Technology Library - SiliconBlue Technologies Confidential 6 SB_DFFE D Flip-Flop with Clock Enable Data D is loaded into the flip-flop when Clock Enable E is high, during a rising clock edge transition. D SB_DFFEQ E C Inputs Output E D C Q 0 1 1 Power on State X 0 1 X X Previous Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the logic „1‟. It is recommended that the user leave the port E unconnected, or use the corresponding flip-flop without Enable functionality i.e. the DFF primitive. Verilog Instantiation // SB_DFFE - D Flip-Flop with Clock Enable. SB_DFFE SB_DFFE_inst ( .Q(Q), // Registered Output ICE Technology Library - SiliconBlue Technologies Confidential 7 .C(C), .D(D), .E(E), ); // Clock // Data // Clock Enable // End of SB_DFFE instantiation VHDL Instantiation -- SB_DFFE - D Flip-Flop with Clock Enable. SB_DFFE_inst : SB_DFFE port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data E => E, -- Clock Enable ); -- End of SB_DFFE instantiation ICE Technology Library - SiliconBlue Technologies Confidential 8 SB_DFFSR D Flip-Flop with Synchronous Reset Data: D is loaded into the flip-flop when Reset R is low during a rising clock edge transition. Reset: R input is active high, overrides all other inputs and resets the Q output during a rising clock edge. DSB_DFFSRQ C Inputs R D 1 X 0 0 Power on State X X 0 1 X R Output C 0 X Q 0 No Change 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Verilog Instantiation // SB_DFFSR - D Flip-Flop, Reset is synchronous with the rising clock edge SB_DFFSR SB_DFFSR_inst ( .Q(Q), // Registered Output ICE Technology Library - SiliconBlue Technologies Confidential 9 .C(C), .D(D), .R(R) ); // Clock // Data // Synchronous Reset // End of SB_DFFSR instantiation VHDL Instantiation -- SB_DFFSR - D Flip-Flop, Reset is synchronous with the rising clock edge SB_DFFSR_inst : SB_DFFSR port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data R => R -- Synchronous Reset ); -- End of SB_DFFSR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 10 SB_DFFR D Flip-Flop with Asynchronous Reset Data: D is loaded into the flip-flop when R is low during a rising clock edge transition. Reset: R input is active high, overrides all other inputs and asynchronously resets the Q output. D SB_DFFRQ C R Inputs Output R D C Q Key 1 0 0 Power on State X 0 1 X X 0 0 1 0 1 0 X ? X Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Verilog Instantiation // SB_DFFR - D Flip-Flop, Reset is asynchronous to the clock. SB_DFFR SB_DFFR_inst ( .Q(Q), // Registered Output .C(C), // Clock ICE Technology Library - SiliconBlue Technologies Confidential 11 .D(D), .R(R) ); // Data // Asynchronous Reset // End of SB_DFFR instantiation VHDL Instantiation -- SB_DFFR - D Flip-Flop, Reset is asynchronous to the clock. SB_DFFR_inst: SB_DFFR port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data R => R -- Asynchronous Reset ); -- End of SB_DFFR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 12 SB_DFFSS D Flip-Flop with Synchronous Set Data: D is loaded into the flip-flop when the Synchronous Set S is low during a rising clock edge transition. Set: S input is active high, overrides all other inputs and synchronously sets the Q output. DSB_DFFSSQ C Inputs S D 1 0 0 Power on State X 0 1 X S Output C Q Key X 1 0 1 0 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Verilog Instantiation // SB_DFFSS - D Flip-Flop, Set is synchronous with the rising clock edge, SB_DFFSS SB_DFFSS_inst ( .Q(Q), // Registered Output .C(C), // Clock ICE Technology Library - SiliconBlue Technologies Confidential 13 .D(D), .S(S) ); // Data // Synchronous Set // End of SB_DFFSS instantiation VHDL Instantiation -- SB_DFFSS - D Flip-Flop, Set is synchronous with the rising clock edge SB_DFFSS_inst SB_DFFSS port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data S => S -- Synchronous Set ); -- End of SB_DFFSS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 14 SB_DFFS D Flip-Flop with Asynchronous Set Data: D is loaded into the flip-flop when S is low during a rising clock edge transition. Set: S input is active high, and it overrides all other inputs and asynchronously sets the Q output. D SB_DFFSQ C Inputs S Output S D C Q Key 1 0 0 Power on State X 0 1 X X 1 0 1 0 1 0 X ? X Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Verilog Instantiation // SB_DFFS - D Flip-Flop, Set is asynchronous to the rising clock edge SB_DFFS SB_DFFS_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data ICE Technology Library - SiliconBlue Technologies Confidential 15 .S(S) ); // Asynchronous Set // End of SB_DFFS instantiation VHDL Instantiation -- SB_DFFS - D Flip-Flop, Set is asynchronous to the rising clock edge SB_DFFS_inst: SB_DFFS port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data S => S -- Asynchronous Set ); -- End of SB_DFFS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 16 SB_DFFESR D Flip-Flop with Clock Enable and Synchronous Reset Data: D is loaded into the flip-flop when Reset R is low and Clock Enable E is high during a rising clock edge transition. Reset: R, when asserted with Clock Enable E high, synchronously resets the Q output during a rising clock edge. D SB_DFFESRQ E C R Inputs Output R E D 1 X 0 0 Power on State 1 0 1 1 X X X 0 1 X C Q 0 X Previous Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always ICE Technology Library - SiliconBlue Technologies Confidential 17 enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. Verilog Instantiation // SB_DFFESR - D Flip-Flop, Reset is synchronous with rising clock edge // Clock Enable. SB_DFFESR SB_DFFESR_inst ( .Q(Q), .C(C), .E(E), .D(D), .R(R) ); // Registered Output // Clock // Clock Enable // Data // Synchronous Reset // End of SB_DFFESR instantiation VHDL Instantiation -- SB_DFFESR - D Flip-Flop, Reset is synchronous with rising clock edge -- Clock Enable. SB_DFFESR_inst: SB_DFFESR port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data R => R -- Synchronous Reset ); -- End of SB_DFFESR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 18 SB_DFFER D Flip-Flop with Clock Enable and Asynchronous Reset Data: D is loaded into the flip-flop when Reset R is low and Clock Enable E is high during a rising clock edge transition. Reset: R input is active high, overrides all other inputs and asynchronously resets the Q output. D SB_DFFERQ E C R Inputs Output R E D C Q 1 0 0 0 Power on State X 0 1 1 X X X 0 1 X X X 0 Previous Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF primitive without a Clock Enable port be used. ICE Technology Library - SiliconBlue Technologies Confidential 19 Verilog Instantiation // SB_DFFER - D Flip-Flop, Reset is asynchronously on rising clock edge with Clock Enable. SB_DFFER SB_DFFER_inst ( .Q(Q), // Registered Output .C(C), // Clock .E(E), // Clock Enable .D(D), // Data .R(R) // Asynchronously Reset ); // End of SB_DFFER instantiation VHDL Instantiation -- SB_DFFER - D Flip-Flop, Reset is asynchronously -- on rising clock edge with Clock Enable. SB_DFFER_inst : SB_DFFER port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data R => R -- Asynchronously Reset ); End of SB_DFFER instantiation ICE Technology Library - SiliconBlue Technologies Confidential 20 SB_DFFESS D Flip-Flop with Clock Enable and Synchronous Set Data: D is loaded into the flip-flop when S is low and E is high during a rising clock edge transition. Set: Asserting S when Clock Enable E is high, synchronously sets the Q output. D SB_DFFESSQ E C S Inputs Output S E D 1 0 0 0 Power on State 1 0 1 1 X X X 0 1 X C Q 1 X Previous Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Input S: Logic „0‟ Verilog Instantiation // SB_DFFESS - D Flip-Flop, Set is synchronous with rising clock edge and Clock Enable. SB_DFFESS SB_DFFESS_inst ( .Q(Q), // Registered Output .C(C), // Clock ICE Technology Library - SiliconBlue Technologies Confidential 21 .E(E), .D(D), .S(S) ); // Clock Enable // Data // Synchronously Set // End of SB_DFFESS instantiation VHDL Instantiation -- SB_DFFESS - D Flip-Flop, Set is synchronous with rising clock edge and Clock Enable. SB_DFFESS_inst : SB_DFFESS port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data S => S -- Synchronously Set ); -- End of SB_DFFESS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 22 SB_DFFES D Flip-Flop with Clock Enable and Asynchronous Set Data: D is loaded into the flip-flop when S is low and E is high during a rising clock edge transition. Set: S input is active high, overrides all other inputs and asynchronously sets the Q output. D SB_DFFESQ E C S Inputs Output S E D CLK Q 1 0 0 0 Power on State X 0 1 1 X X X 0 1 X X X 1 Previous Q X 0 1 0 Key 1 0 X ? Rising Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Input E: Logic „1‟ Verilog Instantiation // SB_DFFES - D Flip-Flop, Set is asynchronous on rising clock edge with Clock Enable. SB_DFFES SB_DFFES_inst ( .Q(Q), // Registered Output ICE Technology Library - SiliconBlue Technologies Confidential 23 .C(C), .E(E), .D(D), .S(S) ); // Clock // Clock Enable // Data // Asynchronously Set // End of SB_DFFES instantiation VHDL Instantiation -- SB_DFFES - D Flip-Flop, Set is asynchronous on rising clock edge with Clock Enable. SB_DFFES_inst : SB_DFFES port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data S => S -- Asynchronously Set ); -- End of SB_DFFES instantiation ICE Technology Library - SiliconBlue Technologies Confidential 24 SB_DFFN D Flip-Flop – Negative Edge Clock Data: D is loaded into the flip-flop during the falling clock edge transition. SB_DFFN D Q C Inputs D 0 1 X Power on State Output C Q X 0 1 0 Key 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Verilog Instantiation // SB_DFFN - D Flip-Flop – Negative Edge Clock. SB_DFFN SB_DFFN_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data ); ICE Technology Library - SiliconBlue Technologies Confidential 25 // End of SB_DFFN instantiation VHDL Instantiation -- SB_DFFN - D Flip-Flop – Negative Edge Clock. SB_DFFN_inst : SB_DFFN port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data ); -- End of SB_DFFN instantiation ICE Technology Library - SiliconBlue Technologies Confidential 26 SB_DFFNE D Flip-Flop – Negative Edge Clock and Clock Enable Data: D is loaded into the flip-flop when E is high, during the falling clock edge transition. D SB_DFFNEQ E C Inputs Output E D C Q Key 0 1 1 Power on State X 0 1 X X 0 0 1 0 1 0 X ? X Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. Verilog Instantiation // SB_DFFNE - D Flip-Flop – Negative Edge Clock and Clock Enable. ICE Technology Library - SiliconBlue Technologies Confidential 27 SB_DFFNE SB_DFFNE_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data .E(E), // Clock Enable ); // End of SB_DFFNE instantiation VHDL Instantiation -- SB_DFFNE - D Flip-Flop – Negative Edge Clock and Clock Enable. SB_DFFNE_inst : SB_DFFNE port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data E => E, -- Clock Enable ); -- End of SB_DFFNE instantiation ICE Technology Library - SiliconBlue Technologies Confidential 28 SB_DFFNSR D Flip-Flop – Negative Edge Clock with Synchronous Reset Data: D is loaded into the flip-flop when R is low during the falling clock edge transition. Reset: R input is active high, overrides all other inputs and resets the Q output during the falling clock edge transition. D SB_DFFNSRQ E C Inputs R Output R D 1 X 0 0 Power on State X X 0 1 X C Q X 0 No Change 0 1 0 Key 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ ICE Technology Library - SiliconBlue Technologies Confidential 29 Verilog Instantiation // SB_DFFNSR - D Flip-Flop – Negative Edge Clock, Reset is synchronous with the falling clock edge SB_DFFNSR SB_DFFNSR_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data .R(R) // Synchronous Reset ); // End of SB_DFFNSR instantiation VHDL Instantiation -- SB_DFFNSR - D Flip-Flop – Negative Edge Clock, Reset is synchronous with the falling clock edge SB_DFFNSR_inst: SB_DFFNSR port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data R => R -- Synchronous Reset ); -- End of SB_DFFNSR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 30 SB_DFFNR D Flip-Flop – Negative Edge Clock with Asynchronous Reset Data: D is loaded into the flip-flop when R is low during the falling clock edge transition. Reset: R input is active high, overrides all other inputs and asynchronously resets the Q output. D SB_DFFNRQ C R Inputs Output R D CLK Q Key 1 0 0 Power on State X 0 1 X X 0 0 1 0 1 0 X ? X Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Verilog Instantiation // SB_DFFNR - D Flip-Flop – Negative Edge Clock, Reset is asynchronous to the clock. SB_DFFNR SB_DFFNR_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data ICE Technology Library - SiliconBlue Technologies Confidential 31 .R(R) ); // Asynchronously Reset // End of SB_DFFNR instantiation VHDL Instantiation -- SB_DFFNR - D Flip-Flop – Negative Edge Clock, Reset is asynchronous to the clock. SB_DFFNR_inst : SB_DFFNR port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data R => R -- Asynchronously Reset ); -- End of SB_DFFNR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 32 SB_DFFNSS D Flip-Flop – Negative Edge Clock with Synchronous Set Data: D is loaded into the flip-flop when S is low during the falling clock edge transition. Set: S input is active high, overrides all other inputs and synchronously sets the Q output. D SB_DFFNSSQ C S Inputs S D 1 0 0 Power on State X 0 1 X Output C Q Key X 1 0 1 0 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Verilog Instantiation // SB_DFFNSS - D Flip-Flop – Negative Edge Clock, Set is synchronous with the falling clock edge, SB_DFFNSS SB_DFFNSS_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data ICE Technology Library - SiliconBlue Technologies Confidential 33 .S(S) ); // Synchronous Set // End of SB_DFFNSS instantiation VHDL Instantiation -- SB_DFFNSS - D Flip-Flop – Negative Edge Clock, Set is synchronous with the falling clock edge, -- with . SB_DFFNSS_inst : SB_DFFNSS port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data S => S -- Synchronous Set ); -- End of SB_DFFNSS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 34 SB_DFFNS D Flip-Flop – Negative Edge Clock with Asynchronous Set Data: D is loaded into the flip-flop when S is low during the falling clock edge transition. Set: S input is active high, overrides all other inputs and asynchronously sets the Q output. D SB_DFFNSQ C S Inputs Output S D C Q Key 1 0 0 Power on State X 0 1 X X 1 0 1 0 1 0 X ? X Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Verilog Instantiation // SB_DFFNS - D Flip-Flop – Negative Edge Clock, Set is asynchronous to the falling clock edge, SB_DFFNS SB_DFFNS_inst ( .Q(Q), // Registered Output .C(C), // Clock .D(D), // Data .S(S) // Asynchronous Set ICE Technology Library - SiliconBlue Technologies Confidential 35 ); // End of SB_DFFNS instantiation VHDL Instantiation -- SB_DFFNS - D Flip-Flop – Negative Edge Clock, Set is asynchronous to the falling clock edge SB_DFFNS_inst : SB_DFFNS port map ( Q => Q, -- Registered Output C => C, -- Clock D => D, -- Data S => S -- Asynchronous Set ); -- End of SB_DFFNS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 36 SB_DFFNESR D Flip-Flop – Negative Edge Clock, Enable and Synchronous Reset Data: D is loaded into the flip-flop when R is low and E is high during the falling clock edge transition. Reset: Asserting R when the Clock Enable E is high, synchronously resets the Q output during the falling clock edge. SB_DFFNESR D Q E C R Inputs Output R E D 1 X 0 0 Power on State 1 0 1 1 X X X 0 1 X C Q Key 0 X Previous Q X 0 1 0 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. ICE Technology Library - SiliconBlue Technologies Confidential 37 Verilog Instantiation // SB_DFFNESR - D Flip-Flop – Negative Edge Clock, Reset is synchronous with falling clock edge Clock Enable. SB_DFFNESR SB_DFFNESR_inst ( .Q(Q), // Registered Output .C(C), // Clock .E(E), // Clock Enable .D(D), // Data .R(R) // Synchronous Reset ); // End of SB_DFFNESR instantiation VHDL Instantiation -- SB_DFFNESR - D Flip-Flop – Negative Edge Clock, Reset is synchronous with falling clock edge Clock Enable. SB_DFFNESR_inst : SB_DFFNESR port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data R => R -- Synchronous Reset ); -- End of SB_DFFNESR instantiation ICE Technology Library - SiliconBlue Technologies Confidential 38 SB_DFFNER D Flip-Flop – Negative Edge Clock, Enable and Asynchronous Reset Data: D is loaded into the flip-flop when R is low and E is high during the falling clock edge transition. Reset: R input is active high, and it overrides all other inputs and asynchronously resets the Q output. SB_DFFNER D Q E C R Inputs Output R E D C Q 1 0 0 0 Power on State X 0 1 1 X X X 0 1 X X X 0 Previous Q X 0 1 0 Key 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input R: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. Verilog Instantiation ICE Technology Library - SiliconBlue Technologies Confidential 39 // SB_DFFNER - D Flip-Flop – Negative Edge Clock, Reset is asynchronously // on falling clock edge and Clock Enable. SB_DFFNER SB_DFFNER_inst ( .Q(Q), // Registered Output .C(C), // Clock .E(E), // Clock Enable .D(D), // Data .R(R) // Asynchronously Reset ); // End of SB_DFFNER instantiation VHDL Instantiation -- SB_DFFNER - D Flip-Flop – Negative Edge Clock, Reset is asynchronously -- on falling clock edge and Clock Enable. SB_DFFNER_inst : SB_DFFNER port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data R => R -- Asynchronously Reset ); -- End of SB_DFFNER instantiation ICE Technology Library - SiliconBlue Technologies Confidential 40 SB_DFFNESS D Flip-Flop – Negative Edge Clock, Enable and Synchronous Set Data: D is loaded into the flip-flop when S is low and E is high during the falling clock edge transition. Set: S and E inputs high, synchronously sets the Q output on the falling clock edge transition. SB_DFFNESS D Q E C S Inputs Output S E D 1 X 0 0 Power on State 1 0 1 1 X X X 0 1 X C Q 1 X Previous Q X 0 1 0 Key 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. ICE Technology Library - SiliconBlue Technologies Confidential 41 Verilog Instantiation // SB_DFFNESS - D Flip-Flop – Negative Edge Clock, Set is synchronous with falling clock edge, // and Clock Enable. SB_DFFNESS SB_DFFNESS_inst ( .Q(Q), // Registered Output .C(C), // Clock .E(E), // Clock Enable .D(D), // Data .S(S) // Synchronously Set ); // End of SB_DFFNESS instantiation VHDL Instantiation -- SB_DFFNESS - D Flip-Flop – Negative Edge Clock, Set is synchronous with falling clock edge, -- and Clock Enable. SB_DFFNESS_inst : SB_DFFNESS port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data S => S -- Synchronously Set ); -- End of SB_DFFNESS instantiation ICE Technology Library - SiliconBlue Technologies Confidential 42 SB_DFFNES D Flip-Flop – Negative Edge Clock, Enable and Asynchronous Set Data: D is loaded into the flip-flop when S is low and E is high during the falling clock edge transition. Set: S input is active high, and it overrides all other inputs and asynchronously sets the Q output. SB_DFFNES D Q E C S Inputs Output S E D CLK Q 1 0 0 0 Power on State X 0 1 1 X X X 0 1 X X X 1 Previous Q X 0 1 0 Key 1 0 X ? Falling Edge High logic level Low logic level Don’t care Unknown HDL Usage This register is inferred during synthesis and can also be explicitly instantiated. Default Signal Values The iCEcube2 software assigns the following signal values to unconnected input ports: Input D: Logic „0‟ Input C: Logic „0‟ Input S: Logic „0‟ Input E: Logic „1‟ Note that explicitly connecting a Logic „1‟ value to port E will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the FF always enabled, it is recommended that either port E be left unconnected, or the corresponding FF without a Clock Enable port be used. ICE Technology Library - SiliconBlue Technologies Confidential 43 Verilog Instantiation // SB_DFFNES - D Flip-Flop – Negative Edge Clock, Set is asynchronous on falling clock edge with clock // Enable. SB_DFFNES SB_DFFNES_inst ( .Q(Q), // Registered Output .C(C), // Clock .E(E), // Clock Enable .D(D), // Data .S(S) // Asynchronously Set ); // End of SB_DFFNES instantiation VHDL Instantiation -- SB_DFFNES - D Flip-Flop – Negative Edge Clock, Set is asynchronous -- on falling clock edge and Clock Enable. SB_DFFNES_inst : SB_DFFNES port map ( Q => Q, -- Registered Output C => C, -- Clock E => E, -- Clock Enable D => D, -- Data S => S -- Asynchronously Set ); -- End of SB_DFFNES instantiation ICE Technology Library - SiliconBlue Technologies Confidential 44 Combinational Logic Primitives SB_LUT4 The LUT unit is a simple ROM 4 input look-up function table. I0 I1 I2 I3 O 4 input LUT Initialization values LUT state initialization parameter LUT_INIT = 16'hxxxx; Inputs Output I3 I2 I1 I0 O 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LUT_INIT[0] LUT_INIT[1] LUT_INIT[2] LUT_INIT[3] LUT_INIT[4] LUT_INIT[5] LUT_INIT[6] LUT_INIT[7] LUT_INIT[8] LUT_INIT[9] LUT_INIT[10] LUT_INIT[11] LUT_INIT[12] LUT_INIT[13] LUT_INIT[14] LUT_INIT[15] HDL Usage This primitive is inferred during synthesis and can also be explicitly instantiated. Default Signal Values ICE Technology Library - SiliconBlue Technologies Confidential 45 The iCEcube2 software assigns logic value „0‟ to unconnected input ports. Verilog Instantiation // SB_LUT4 : 4-input Look-Up Table SB_LUT4 SB_LUT4_inst ( .O (O), // output .I0 (I0), // data input 0 .I1 (I1), // data input 1 .I2 (I2), // data input 2 .I3 (I3) // data input 3 ); defparam SB_LUT4_inst.LUT_INIT=16'hxxxx; //LUT state initialization parameter, 16 bits. //End of SB_LUT4 instantiation VHDL Instantiation -- SB_LUT4 : 4-input Look-Up Table SB_LUT4_inst: SB_LUT4 generic map( LUT_INIT => X"0001" -- LUT state initialization parameter, 16 bits ) port map ( I0 => I0, I1 => I1, I2 => I2, I3 => I3, O => O ); ICE Technology Library - SiliconBlue Technologies Confidential 46 SB_CARRY Carry Logic The dedicated Carry Logic within each Logic Cell primarily accelerates and improves the efficiency of arithmetic logic such as adders, accumulators, subtracters, incrementers, decrementers, counters, ALUs, and comparators. The Carry Logic also supports a limited number of wide combinational logic functions. The figure below illustrates the Carry Logic structure within a Logic Cell. The Carry Logic shares inputs with the associated Look-Up Table (LUT). The I1 and I2 inputs of the LUT directly feed the Carry Logic.. The carry input from the previous adjacent Logic Cell optionally provides an alternate input to the LUT4 function, supplanting the I3 input. Carry Logic Structure within a Logic Cell Inputs Output I0 I1 CI CO 0 0 X X 1 1 0 X 1 0 X 1 X 0 1 0 1 X 0 0 1 0 1 1 HDL Usage This primitive is inferred during synthesis and can also be explicitly instantiated. ICE Technology Library - SiliconBlue Technologies Confidential 47 Default Signal Values The iCEcube2 software assigns logic value „0‟ to unconnected input ports. Verilog Instantiation SB_CARRY my_carry_inst ( .CO(CO), .I0(I0), .I1(I1), .CI(CI)); VHDL Instantiation my_carry_inst : SB_CARRY port map ( CO => CO, CI => CI, I0 => I0, I1 => I1 ); ICE Technology Library - SiliconBlue Technologies Confidential 48 Block RAM Primitives The iCE architecture supports dual ported synchronous RAM, with 4096 bits, and a fixed 16 bit datawidth. The block is arranged as 256 x 16 bit words. The RAM block may be configured to be used as a RAM with data between 1-16 bits. iCE65 Block RAM Each iCE65 device includes multiple high-speed synchronous RAM blocks (RAM4K), each 4Kbit in size. A RAM4K block has separate write and read ports, each with independent control signals. Additionally, the write port has an Active-Low bit-line write-enable control; each write-port data bit has an individual write-enable control. By default, input and output data is 16 bits wide, although the data width is configurable using programmable logic and, if needed, multiple RAM4K blocks. The data contents of the RAM4K block are optionally pre-loaded during ICE device configuration. RAM4K Naming Convention Rules The SiliconBlue Technologies convention for the RAM4K primitives with negedge Read or Write clock is that the base primitive name is post fixed with N and R or W according to the clock that is affected, as displayed in the table below. RAM Primitive Name SB_RAM4K SB_RAM4KNR SB_RAM4KNW SB_RAM4KNRNW WCLKE Description Posedge Read clock, Posedge Write clock Negedge Read clock, Posedge Write clock Posedge Read clock, Negedge Write clock Negedge Read clock, Negedge Write clock RCLKE RAM4K blocks have separate write and read ports, each with independent control signals. ICE Technology Library - SiliconBlue Technologies Confidential 49 The data contents of the RAM4K block are optionally pre-loaded during ICE device configuration. If the RAM4K blocks are not pre-loaded during configuration, then the resulting configuration bitstream image is smaller. If an unitialized RAM4K block is used in the application, then the application must initialize the RAM contents to guarantee the data value. The following table lists the signals for both ports. Additionally, the write port has an active-Low bit-line write-enable control: RAM4K Block RAM Signals Signal Name WDATA[15:0] MASK[15:0] WADDR[7:0] WE WCLK WCLKE RDATA[15:0] RADDR[7:0] RE RCLK RCLKE INIT_0, … …,INIT_F Direction Description Input Input Input Input Input Input Output Input Input Input Input Verilog parameter Write Data input Bit-line Write Enable input, active low Write Address input. Selects up to 256 possible locations Write Enable input, active high Write Clock input, rising-edge active Write Clock Enable input Read Data output Read Address input. Selects one of 256 possible locations Read Enable input, active high Read Clock input, rising-edge active Read Clock Enable input RAM Initialization Data. Passed using 16 parameter strings, each comprising 256 bits. (16x256=4096 total bits) ICE Technology Library - SiliconBlue Technologies Confidential 50 Write Operation 1. Supply a valid address on the WADDR[7:0] address input port 2. Supply valid data on the WDATA[15:0] data input port To write or mask selected data bits, set the associated bit write MASK accordingly. For example, write operations on data bit Data[i] is controlled by the associated MASK[i] input: MASK[i] = 0: Enable write operations for data line Data[i] 3. MASK[i] = 1: Mask write operations for data line Data[i] Enable the RAM4K write port (WE = 1) Apply a rising clock edge on WCLK Operation Disabled Disabled Write Data Masked Write WDATA[15:0] Data X X MASK[15:0] Bit Enable X X WADDR[7:0] Address X X WE Enable X 0 WCLK Clock 0 X D[i] MASK[i]=0 WADDR 1 ↑ X MASK[i]=1 WADDR 1 ↑ RAM Location No Change No Change RAM[WADDR[i]] = D[i] RAM[WADDR[i]] = No Change Read Operation The following table describes various read operations for a RAM4K block. All RAM4K read operations are synchronized to the rising edge of RCLK. Operation RADDR[7:0] Address RE Enable RCLK Clock RDATA[15:0] X X X Undefined X 0 X No Change RA 1 ↑ RAM[RADDR] After configuration, before first valid Read Data operation Disabled Read Data To read data from the RAM4K block 1. Supply a valid address on the RADDR[7:0] address input port 2. Enable the RAM4K read port (RE = 1) 3. Apply a rising clock edge on RCLK ICE Technology Library - SiliconBlue Technologies Confidential 51 Default Signal Values The iCEcube2 software assigns logic value „0‟ to all unconnected input ports, with the exception of the RCLKE and WCLKE ports. The RCLKE and WCLKE ports are always enabled by default i.e. if left unconnected the software will automatically assign a logic value „1‟ to these ports. Note that explicitly connecting a logic „1‟ value to ports RCLKE and WCLKE will result in a non-optimal implementation, since an extra LUT will be used to generate the logic „1‟. If the user‟s intention is to always maintain the clocks in an enabled state, it is recommended that these ports be left unconnected. Note that the Read Enable (RE) and Write Enable (WE) ports are always disabled by default, since they are tied-off to logic „0‟ by the software, unless explicitly enabled by the user. Verilog Instantiation The following instantiation is for the base SB_RAM4K, all other RAM4K based primitives share the same format with the only difference being the port name changes. All primitives share the same parameter for data initialization after power on reset. // SB_RAM4K with data initialization after power on reset SB_RAM4K SB_RAM4K_with_INIT (.RDATA(RDATA), .RCLK(RCLK), .RCLKE(RCLKE), .RE(RE), .RADDRRADDR), .WCLK(WCLK), .WCLKE(WCLKE), .WE(WE), .WADDR(WADDR), .MASK(MASK), .WDATA(WDATA)); defparam SB_RAM4K_with_INIT.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; ICE Technology Library - SiliconBlue Technologies Confidential 52 defparam SB_RAM4K_with_INIT.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam SB_RAM4K_with_INIT.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; VHDL Instantiation - - SB_RAM4K with data initialization after power on reset SB_RAM4K_with_INIT : SB_RAM4K generic map ( INIT_0 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_8 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_9 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( RDATA => RDATA, RADDR => RADDR, RCLK => RCLK, RCLKE => RCLKE, RE => RE, WADDR => WADDR, WCLK => WCLK, WCLKE => WCLKE, WDATA => WDATA, MASK => MASK, WE => WE ); ICE Technology Library - SiliconBlue Technologies Confidential 53 The following are the complete list of RAM4K based primitives SB_RAM4K SB_RAM4K //Posedge clock RCLK WCLK (RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM4KNR SB_RAM4KNR // Negative edged Read Clock – i.e. RCLKN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM4KNW SB_RAM4KNW // Negative edged Write Clock – i.e. WCLKN (RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM4KNRW SB_RAM4KNRNW // Negative edged Read and Write – i.e. RCLKN WRCKLN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); ICE Technology Library - SiliconBlue Technologies Confidential 54 iCE40 Block RAM Each iCE40 device includes multiple high-speed synchronous RAM blocks, each 4Kbit in size. The RAM block has separate write and read ports, each with independent control signals. Each RAM block can be configured into a RAM block of size 256x16, 512x8, 1024x4 or 2048x2. The data contents of the RAM block are optionally pre-loaded during ICE device configuration. The following table lists the supported dual port synchronous RAM configurations, each of 4Kbits in size. The RAM blocks can be directly instantiated in the top module and taken through iCube2 flow. Block RAM Configuration SB_RAM256x16 SB_RAM256x16NR SB_RAM256x16NW SB_RAM256x16NRNW SB_RAM512x8 SB_RAM512x8NR SB_RAM512x8NW SB_RAM512x8NRNW WADDR Port Size (Bits) WDATA Port Size (Bits) RADDR Port Size (Bits) RDATA Port Size (Bits) 256x16 (4K) 8 [7:0] 16 [15:0] 8 [7:0] 16 [15:0] 16 [15:0] 512x8 (4K) 9 [8:0] 8 [7:0] 8 [8:0] 8 [7:0] No Mask Port Block RAM Size MASK Port Size (Bits) SB_RAM1024x4 SB_RAM1024x4NR SB_RAM1024x4NW SB_RAM1024x4NRNW 1024x4 (4K) 10 [9:0] 4 [3:0] 10 [9:0] 4 [3:0] No Mask Port SB_RAM2048x2 SB_RAM2048x2NR SB_RAM2048x2NW SB_RAM2048x2NRNW 2048x2 (4K) 11 [10:0] 2 [1:0] 10 [9:0] 2 [1:0] No Mask Port The SiliconBlue Technologies convention for the iCE40 RAM primitives with negedge Read or Write clock is that the base primitive name is post fixed with N and R or W according to the clock that is affected, as displayed in the table below for 256x16 RAM block configuration. RAM Primitive Name SB_RAM256x16 SB_RAM4256x16NR SB_RAM256x16NW SB_RAM256x16NRNW Description Posedge Read clock, Posedge Write clock Negedge Read clock, Posedge Write clock Posedge Read clock, Negedge Write clock Negedge Read clock, Negedge Write clock ICE Technology Library - SiliconBlue Technologies Confidential 55 SB_RAM256x16 Verilog Instantiation: SB_RAM256x16 ram256X16_inst ( .RDATA(RDATA_c[15:0]), .RADDR(RADDR_c[7:0]), .RCLK(RCLK_c), .RCLKE(RCLKE_c), .RE(RE_c), .WADDR(WADDR_c[7:0]), .WCLK(WCLK_c), .WCLKE(WCLKE_c), .WDATA(WDATA_c[15:0]), .WE(WE_c), .MASK(MASK_c[15:0]) ); defparam ram256x16_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; ICE Technology Library - SiliconBlue Technologies Confidential 56 defparam ram256x16_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram256x16_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; VHDL Instantiation: ram256X16_inst : SB_RAM256x16 generic map ( INIT_0 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_8 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_9 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( RDATA => RDATA_c, RADDR => RADDR_c, RCLK => RCLK_c, RCLKE => RCLKE_c, RE => RE_c, WADDR => WADDR_c, WCLK=> WCLK_c, WCLKE => WCLKE_c, WDATA => WDATA_c, MASK => MASK_c, ICE Technology Library - SiliconBlue Technologies Confidential 57 WE => WE_c ); The following modules are the complete list of SB_RAM256x16 based primitives SB_RAM256x16 SB_RAM256x16 //Posedge clock RCLK WCLK (RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM256x16NR SB_RAM256x16NR // Negative edged Read Clock – i.e. RCLKN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM256x16NW SB_RAM256x16NW // Negative edged Write Clock – i.e. WCLKN (RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM256x16NRNW SB_RAM256x16NRNW // Negative edged Read and Write – i.e. RCLKN WRCKLN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); ICE Technology Library - SiliconBlue Technologies Confidential 58 SB_RAM512x8 Verilog Instantiation: SB_RAM512x8 ram512X8_inst ( .RDATA(RDATA_c[7:0]), .RADDR(RADDR_c[8:0]), .RCLK(RCLK_c), .RCLKE(RCLKE_c), .RE(RE_c), .WADDR(WADDR_c[8:0]), .WCLK(WCLK_c), .WCLKE(WCLKE_c), .WDATA(WDATA_c[7:0]), .WE(WE_c) ); defparam ram512x8_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; ICE Technology Library - SiliconBlue Technologies Confidential 59 defparam ram512x8_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram512x8_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; VHDL Instantiation: ram512X8_inst : SB_RAM512x8 generic map ( INIT_0 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_8 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_9 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( RDATA => RDATA_c, RADDR => RADDR_c, RCLK => RCLK_c, RCLKE => RCLKE_c, RE => RE_c, WADDR => WADDR_c, WCLK=> WCLK_c, WCLKE => WCLKE_c, WDATA => WDATA_c, WE => WE_c ); ICE Technology Library - SiliconBlue Technologies Confidential 60 The following modules are the complete list of SB_RAM512x8 based primitives SB_RAM512x8 SB_RAM512x8 //Posedge clock RCLK WCLK (RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM512x8NR SB_RAM512x8NR // Negative edged Read Clock – i.e. RCLKN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM512x8NW SB_RAM512x8NW // Negative edged Write Clock – i.e. WCLKN (RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM512x8NRNW SB_RAM512x8NRNW // Negative edged Read and Write – i.e. RCLKN WRCKLN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); ICE Technology Library - SiliconBlue Technologies Confidential 61 SB_RAM1024x4 Verilog Instantiation: SB_RAM1024x4 ram1024x4_inst ( .RDATA(RDATA_c[3:0]), .RADDR(RADDR_c[9:0]), .RCLK(RCLK_c), .RCLKE(RCLKE_c), .RE(RE_c), .WADDR(WADDR_c[3:0]), .WCLK(WCLK_c), .WCLKE(WCLKE_c), .WDATA(WDATA_c[9:0]), .WE(WE_c) ); defparam ram1024x4_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; ICE Technology Library - SiliconBlue Technologies Confidential 62 defparam ram1024x4_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram1024x4_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; VHDL Instantiation: Ram1024X4_inst : SB_RAM1024x4 generic map ( INIT_0 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_8 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_9 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( RDATA => RDATA_c, RADDR => RADDR_c, RCLK => RCLK_c, RCLKE => RCLKE_c, RE => RE_c, WADDR => WADDR_c, WCLK=> WCLK_c, WCLKE => WCLKE_c, ICE Technology Library - SiliconBlue Technologies Confidential 63 WDATA => WDATA_c, WE => WE_c ); The following modules are the complete list of SB_RAM1024x4 based primitives SB_RAM1024x4 SB_RAM1024x4 //Posedge clock RCLK WCLK (RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM1024x4NR SB_RAM1024x4NR // Negative edged Read Clock – i.e. RCLKN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM1024x4NW SB_RAM1024x4NW // Negative edged Write Clock – i.e. WCLKN (RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM1024x4NRNW SB_RAM1024x4NRNW // Negative edged Read and Write – i.e. RCLKN WRCKLN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); ICE Technology Library - SiliconBlue Technologies Confidential 64 SB_RAM2048x2 Verilog Instantiation: SB_RAM2048x2 ram2048x2_inst ( .RDATA(RDATA_c[2:0]), .RADDR(RADDR_c[10:0]), .RCLK(RCLK_c), .RCLKE(RCLKE_c), .RE(RE_c), .WADDR(WADDR_c[2:0]), .WCLK(WCLK_c), .WCLKE(WCLKE_c), .WDATA(WDATA_c[10:0]), .WE(WE_c) ); defparam ram2048x2_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; ICE Technology Library - SiliconBlue Technologies Confidential 65 defparam ram2048x2_inst .INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; defparam ram2048x2_inst .INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; VHDL Instantiation: Ram2048x2_inst : SB_RAM2048x2 generic map ( INIT_0 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_8 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_9 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( RDATA => RDATA_c, RADDR => RADDR_c, RCLK => RCLK_c, RCLKE => RCLKE_c, RE => RE_c, WADDR => WADDR_c, WCLK=> WCLK_c, WCLKE => WCLKE_c, WDATA => WDATA_c, WE => WE_c ); ICE Technology Library - SiliconBlue Technologies Confidential 66 The following modules are the complete list of SB_RAM2048x2 based primitives SB_RAM2048x2 SB_RAM2048x2 //Posedge clock RCLK WCLK (RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM2048x2NR SB_RAM2048x2NR // Negative edged Read Clock – i.e. RCLKN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM2048x2NW SB_RAM2048x2NW // Negative edged Write Clock – i.e. WCLKN (RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); SB_RAM2048x2NRNW SB_RAM2048x2NRNW // Negative edged Read and Write – i.e. RCLKN WRCKLN (RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA); ICE Technology Library - SiliconBlue Technologies Confidential 67 SB_RAM40_4K SB_RAM40_4K is the basic physical RAM primitive which can be instantiated and configured to different depth and dataports. The SB_RAM40_4K block has a size of 4K bits with separate write and read ports, each with independent control signals. By default, input and output data is 16 bits wide, although the data width is configurable using the READ_MODE and WRITE_MODE parameters. The data contents of the SB_RAM40_4K block are optionally pre-loaded during ICE device configuration. SB_RAM40_4K Naming Convention Rules RAM Primitive Name SB_RAM40_4K SB_RAM40_4KNR SB_RAM40_4KNW SB_RAM40_4KNRNW Description Posedge Read clock, Posedge Write clock Negedge Read clock, Posedge Write clock Posedge Read clock, Negedge Write clock Negedge Read clock, Negedge Write clock The following table lists the signals for both ports. SB_RAM40_4K RAM Port Signals Signal Name Direction WDATA[15:0] MASK[15:0]* Input Input WADDR[7:0] WE WCLK WCLKE RDATA[15:0] RADDR[7:0] RE Input Input Input Input Output Input Input Description Write Data input Bit-line Write Enable input, active low. Applicable only when WRITE_MODE parameter is set to 0. Write Address input. Selects up to 256 possible locations Write Enable input, active high Write Clock input, rising-edge active Write Clock Enable input Read Data output Read Address input. Selects one of 256 possible locations Read Enable input, active high ICE Technology Library - SiliconBlue Technologies Confidential 68 RCLK RCLKE Input Input Read Clock input, rising-edge active Read Clock Enable input Parameter Name Description Parameter Value INIT_0, … …,INIT_F RAM Initialization Data. Passed using 16 parameter strings, each comprising 256 bits. (16x256=4096 total bits) Sets the RAM block write port configuration INIT_0 to INIT_F WRITE_MODE READ_MODE Sets the RAM block read port configuration Configuration Initialize the RAM with predefined value 0 1 2 3 0 1 2 3 256x16 512x8 1024x4 2048x2 256x16 512x8 1024x4 2048x2 Verilog Instantiation: // Physical RAM Instance without Pre Initialization SB_RAM40_4K ram40_4kinst_physical ( .RDATA(RDATA), .RADDR(RADDR), .WADDR(WADDR), .MASK(MASK), .WDATA(WDATA) .RCLKE(RCLKE), .RCLK(RCLK), .RE(RE), .WCLKE(WCLKE), .WCLK(WCLK), .WE(WE) ); defparam ram40_4kinst_physical.READ_MODE=0; defparam ram40_4kinst_physical.WRITE_MODE=0; VHDL Instantiation: -- Physical RAM Instance without Pre Initialization ram40_4kinst_physical : SB_RAM40_4K generic map ( READ_MODE => 0, WRITE_MODE= >0 ) port map ( RDATA=>RDATA, ICE Technology Library - SiliconBlue Technologies Confidential 69 RADDR=>RADDR, WADDR=>WADDR, MASK=>MASK, WDATA=>WDATA, RCLKE=>RCLKE, RCLK=>RCLK, RE=>RE, WCLKE=>WCLKE, WCLK=>WCLK, WE=>WE ); IO Primitives ICE Technology Library - SiliconBlue Technologies Confidential 70 SB_IO The SB_IO block contains five registers. The following figure and Verilog template illustrate the complete user accessible logic diagram, and its Verilog instantiation. Default Signal Values The iCEcube2 software assigns the logic „0‟ value to all unconnected input ports except for CLOCK_ENABLE. Note that explicitly connecting a logic „1‟ value to port CLOCK_ENABLE will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the Input and Output registers always enabled, it is recommended that port CLOCK_ENABLE be left unconnected. ICE Technology Library - SiliconBlue Technologies Confidential 71 Verilog Instantiation SB_IO IO_PIN_INST ( .PACKAGE_PIN (Package_Pin), .LATCH_INPUT_VALUE (latch_input_value), .CLOCK_ENABLE (clock_enable), clock .INPUT_CLK (input_clk), .OUTPUT_CLK (output_clk), .OUTPUT_ENABLE (output_enable), .D_OUT_0 (d_out_0), .D_OUT_1 (d_out_1), .D_IN_0 (d_in_0), .D_IN_1 (d_in_1) ); defparam IO_PIN_INST.PIN_TYPE = 6'b000000; // User‟s Pin signal name // Latches/holds the Input value // Clock Enable common to input and output // Clock for the input registers // Clock for the output registers // Output Pin Tristate/Enable control // Data 0 – out to Pin/Rising clk edge // Data 1 - out to Pin/Falling clk edge // Data 0 - Pin input/Rising clk edge // Data 1 – Pin input/Falling clk edge // See Input and Output Pin Function Tables. // Default value of PIN_TYPE = 6‟000000 // i.e. an input pad, with the input signal // registered. defparam IO_PIN_INST.PULLUP = 1'b0; // By default, the IO will have NO pull up. This // parameter is used only on bank 0, 1, and 2. //Ignored when it is placed at bank 3 defparam IO_PIN_INST.NEG_TRIGGER = 1'b0; // Specify the polarity of all FFs in the IO to be // falling edge when NEG_TRIGGER = 1. // Default is rising edge defparam IO_PIN_INST.IO_STANDARD = "SB_LVCMOS"; // Other IO standards are supported in bank 3 // only: SB_SSTL2_CLASS_2, SB_SSTL2_CLASS_1, // SB_SSTL18_FULL, SB_SSTL18_HALF, SB_MDDR10, // SB_MDDR8, SB_MDDR4, SB_MDDR2 etc. Input and Output Pin Function Tables Input and Output functions are independently selectable via PIN_TYPE [1:0] and PIN_TYPE [5:2] respectively. Specific IO functions are defined by the combination of both attributes. This means that the complete number of combinations is 64, although some combinations are not valid and not defined below. Note that the selection of IO Standards such as SSTL and LVCMOS are not defined by these tables. ICE Technology Library - SiliconBlue Technologies Confidential 72 Input Pin Function Table # Pin Function Mnemonic Functional Description of Package Pin Input Operation PIN_TYPE[1:0] 1 2 PIN_INPUT PIN_INPUT_LATCH 0 1 1 1 3 4 PIN_INPUT_REGISTERED PIN_INPUT_REGISTERED_LATCH 0 1 0 0 5 PIN_INPUT_DDR 0 0 Simple input pin (D_IN_0) Disables internal data changes on the physical input pin by latching the value. Input data is registered in input cell Disables internal data changes on the physical input pin by latching the value on the input register Input 'DDR' data is clocked out on rising and falling clock edges. Use the D_IN_0 and D_IN_1 pins for DDR operation. Output Pin Function table # Pin Function Mnemonic PIN_TYPE[5:2] 1 2 3 PIN_NO_OUTPUT PIN_OUTPUT PIN_OUTPUT_TRISTATE 0 0 1 0 1 0 0 1 1 0 0 0 4 PIN_OUTPUT_ENABLE_REGISTERED 1 1 1 0 5 6 PIN_OUTPUT_REGISTERED PIN_OUTPUT_REGISTERED_ENABLE 0 1 1 0 0 0 1 1 7 1 1 0 1 8 PIN_OUTPUT_REGISTERED_ENABLE_REGI STERED PIN_OUTPUT_DDR 0 1 0 0 9 PIN_OUTPUT_DDR_ENABLE 1 0 0 0 10 PIN_OUTPUT_DDR_ENABLE_REGISTERED 1 1 0 0 11 12 PIN_OUTPUT_REGISTERED_INVERTED PIN_OUTPUT_REGISTERED_ENABLE__INV ERTED PIN_OUTPUT_REGISTERED_ENABLE_REGI STERED_INVERTED 0 1 1 0 1 1 1 1 1 1 1 1 13 Functional Description of Package Pin Output Operation Disables the output function Simple output pin, (no enable) The output pin may be tristated using the enable The output pin may be tristated using a registered enable signal Output registered, (no enable) Output registered with enable (enable is not registered) Output registered and enable registered Output 'DDR' data is clocked out on rising and falling clock edges Output data is clocked out on rising and falling clock edges Output 'DDR' data with registered enable signal Output registered signal is inverted Output signal is registered and inverted, (no enable function) Output signal is registered and inverted, the enable/tristate control is also registered. ICE Technology Library - SiliconBlue Technologies Confidential 73 Syntax Verilog Use defparam my_generic_IO.PIN_TYPE = 6‟b{Output Pin Function, Input Pin Function}; Output Pin Function is the bit vector associated with PIN_TYPE[5:2] and Input Pin Function is the bit vector associated with PIN_TYPE[1:0], resulting in a 6 bit value PIN_TYPE[5:0] Example defparam my_DDR_IO.PIN_TYPE = 6‟b110000; //PIN_TYPE[5:2] = 1100, PIN_TYPE[1:0] = 00 This creates a DDR IO pin whereby the input data is clocked in on both the rising and falling clock edges. The output 'DDR' data is clocked out on rising and falling clock edges, and the output may be tri-stated, using the enable port of the SB_IO. ICE Technology Library - SiliconBlue Technologies Confidential 74 Global Buffer Primitives SB_GB_IO Default Signal Values The iCEcube2 software assigns the logic „0‟ value to all unconnected input ports except for CLOCK_ENABLE. Note that explicitly connecting a logic „1‟ value to port CLOCK_ENABLE will result in a non-optimal implementation, since an extra LUT will be used to generate the Logic „1‟. If the user‟s intention is to keep the Input and Output registers always enabled, it is recommended that port CLOCK_ENABLE be left unconnected. Verilog Instantiation SB_GB_IO My_Clock_Buffer_Package_Pin ( .PACKAGE_PIN (Package_Pin), .LATCH_INPUT_VALUE (latch_input_value), .CLOCK_ENABLE (clock_enable), .INPUT_CLK (input_clk), // A users external Clock reference pin // Users Pin signal name // Latches/holds the Input value // Four independent clock enables/bank // common to input and output clock // The clock for the input registers ICE Technology Library - SiliconBlue Technologies Confidential 75 .OUTPUT_CLK (output_clk), // The clock for the output registers .OUTPUT_ENABLE (output_enable), // Output Pin Tristate/Enable control .D_OUT_0 (d_out_0), // Data 0 – out to Pin/Rising clk edge .D_OUT_1 (d_out_1), // Data 1 - out to Pin/Falling clk edge .D_IN_1 (d_in_0), // Data 0 - Pin input/Rising clk edge .D_IN_0 (d_in_1) // Data 1 – Pin input/Falling clk edge .GLOBAL_BUFFER_OUTPUT (Global_Buffered_User_Clock) // Example use – clock buffer driven from the input pin ); defparam My_Clock_Buffer_Package_Pin.PIN_TYPE = Various; //For details on PIN_TYPE and Pin Function Tables, refer to section on SB_IO Note that this primitive is a superset of the SB_IO primitive, and includes the connectivity to drive a Global Buffer. For example SB_GB_IO pins are likely to be used for external Clocks. SB_GB Primitive Verilog Instantiation SB_GB My_Global_Buffer_i ( // Required for a user‟s internally generated FPGA signal that is heavily loaded //and requires global buffering. For example, a user‟s logic-generated clock. .USER_SIGNAL_TO_GLOBAL_BUFFER (Users_internal_Clk), .GLOBAL_BUFFER_OUTPUT ( Global_Buffered_User_Signal) ); ICE Technology Library - SiliconBlue Technologies Confidential 76 PLL Primitives The Phase Lock Loop (PLL) function is offered as a feature in certain devices of the iCE65 and iCE40 device family. . It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. iCE65 PLL Primitives There are 3 primitives that represent the PLL function in the iCEcube2 software viz. SB_PLL_CORE, SB_PLL_PAD, and SB_PLL_2_PAD. A short description of each primitive and its ports/parameters is provided in the following sections. SB_PLL_CORE The SB_PLL_CORE primitive should be used when the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA or is driven by an input pad that is not in the bottom IO bank (IO Bank 2). Ports REFERENCECLK: PLL source clock that serves as the input to the SB_PLL_CORE primitive. PLLOUTGLOBAL: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCORE: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBAL/PLLOUTCORE is locked to the PLL source on REFERENCECLK. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. ICE Technology Library - SiliconBlue Technologies Confidential 77 DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESET: Active low input that asynchronously resets the PLL. BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBAL/PLLOUTCORE pins are held static at their last value. This function is enabled when the parameter ENABLE_ICEGATE is set to „1‟. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL_CORE primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 78 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE Selects the mode for the Fine Delay Adjust block. FIXED DYNAMIC FIXED_DELAY_ADJUSTMENT Sets a constant value for the Fine Delay Adjust Block. 0, 1,…,15 PLL_OUT_PHASE Controls the phase alignment of the PLLOUTCORE & PLLOUTGLOBAL signals relative to REFERENCECLK NONE DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL power-down control 0deg 90deg 180deg 270deg 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified 0 1 Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FIXED_DELAY_ADJUSTMENT parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FIXED_DELAY_ADJUSTMENT, only if the setting of the DELAY_ADJUSTMENT_MODE is FIXED. No phase alignment. No duty cycle correction 0o phase shift 90o phase shift 180o phase shift 270o phase shift These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a userimplemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 79 SB_PLL_PAD The SB_PLL_PAD primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2), and the source clock is not required inside the FPGA. Ports PACKAGEPIN: PLL source clock that serves as the input to the SB_PLL_PAD primitive. PLLOUTGLOBAL: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCORE: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBAL/PLLOUTCORE is locked to the PLL source on PACKAGEPIN. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESET: Active low input that asynchronously resets the PLL. BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBAL/PLLOUTCORE pins are held static at their last value. This function is enabled when the parameter ENABLE_ICEGATE is set to „1‟. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. ICE Technology Library - SiliconBlue Technologies Confidential 80 Parameters The SB_PLL_PAD primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 81 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE Selects the mode for the Fine Delay Adjust block. FIXED DYNAMIC FIXED_DELAY_ADJUSTMENT Sets a constant value for the Fine Delay Adjust Block. 0, 1,…,15 PLL_OUT_PHASE Controls the phase alignment of the PLLOUTCORE & PLLOUTGLOBAL signals relative to REFERENCECLK NONE DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL power-down control 0deg 90deg 180deg 270deg 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified 0 1 Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FIXED_DELAY_ADJUSTMENT parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FIXED_DELAY_ADJUSTMENT, only if the setting of the DELAY_ADJUSTMENT_MODE is FIXED. No phase alignment. No duty cycle correction 0o phase shift 90o phase shift 180o phase shift 270o phase shift These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a userimplemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 82 SB_PLL_2_PAD The SB_PLL_2_PAD primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2), and in addition to the PLL output, the source clock is also required inside the FPGA. Port A (Source Clock) Port B (Generated Clock) Ports PACKAGEPIN: PLL source clock that serves as the input to the SB_PLL_PAD primitive. PLLOUTGLOBALA: The signal on PACKAGEPIN appears on the FPGA at this pin, and drives a global clock network on the FPGA. Do not use this pin in an external feedback path to the PLL. PLLOUTCOREA: The signal on PACKAGEPIN appears on the FPGA at this pin, which drives regular FPGA routing. Do not use this pin in an external feedback path to the PLL. PLLOUTGLOBALB: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCOREB: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBALB/PLLOUTCOREB is locked to the PLL source on PACKAGEPIN. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESET: Active low input that asynchronously resets the PLL. ICE Technology Library - SiliconBlue Technologies Confidential 83 BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBALA/PLLOUTCOREA pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTA is set to „1‟, and the LATCHINPUTVALUE signal is asserted. The PLLOUTGLOBALB/PLLOUTCOREB pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTB is set to „1‟, and the LATCHINPUTVALUE signal is asserted. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL_2_PAD primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 84 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE Selects the mode for the Fine Delay Adjust block. FIXED DYNAMIC FIXED_DELAY_ADJUSTMENT Sets a constant value for the Fine Delay Adjust Block. PLL_OUT_PHASE Controls the phase alignment of the PLLOUTCORE & PLLOUTGLOBAL signals relative to REFERENCECLK DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE_PORTA/ ENABLE_ICEGATE_PORTB REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Separate powerdown controls for Port A and Port B outputs 0, 1,…,15 NONE 0deg 90deg 180deg 270deg 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified 0 1 Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FIXED_DELAY_ADJUSTMENT parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FIXED_DELAY_ADJUSTMENT, only if the setting of the DELAY_ADJUSTMENT_MODE is FIXED. No phase alignment. No duty cycle correction 0o phase shift 90o phase shift 180o phase shift 270o phase shift These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a userimplemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 85 iCE40 PLL Primitives There are 5 primitives that represent the PLL function in the iCEcube2 software viz. SB_PLL40_CORE, SB_PLL40_PAD, SB_PLL40_2_PAD, SB_PLL40_2F_CORE and SB_PLL40_2F_PAD for the ice40 device family. A short description of each primitive and its ports/parameters is provided in the following sections. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. SB_PLL40_CORE The SB_PLL40_CORE primitive should be used when the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA or is driven by an input pad that is not in the bottom IO bank (IO Bank 2). Ports REFERENCECLK: PLL source clock that serves as the input to the SB_PLL40_CORE primitive. PLLOUTGLOBAL: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCORE: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBAL/PLLOUTCORE is locked to the PLL source on REFERENCECLK. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 7 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The ICE Technology Library - SiliconBlue Technologies Confidential 86 DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESETB: Active low input that asynchronously resets the PLL. BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBAL/PLLOUTCORE pins are held static at their last value. This function is enabled when the parameter ENABLE_ICEGATE is set to „1‟. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL40_CORE primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 87 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_M ODE_FEEDBACK Selects the mode for the Fine Delay Adjust block in the feedback path FIXED DYNAMIC FDA_FEEDBACK Sets a constant value for the Fine Delay Adjust Block in the feedback path DELAY_ADJUSTMENT_M ODE_RELATIVE Selects the mode for the Fine Delay Adjust block 0, 1,…,15 FIXED DYNAMIC FDA_RELATIVE Sets a constant value for the Fine Delay Adjust Block SHIFTREG_DIV_MODE Selects shift register configuration PLLOUT_SELECT Selects the signal to be output at the PLLOUTCORE and PLLOUTGLOBAL ports 0, 1,…,15 0,1 SHIFTREG_0deg SHIFTREG_90deg GENCLK Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_FEEDBACK parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FDA_FEEDBACK only if the setting of the DELAY_ADJUSTMENT_MODE_ FEEDBACK is FIXED. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_RELATIVE parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[7:4] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are additionally delayed by (n+1)*150 ps, where n = FDA_RELATIVE. Used if DELAY_ADJUSTMENT_MODE_ RELATIVE is “FIXED”. Used when FEEDBACK_PATH is “PHASE_AND_DELAY”. 0Divide by 4 1Divide by 7 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output without any phase shift. ICE Technology Library - SiliconBlue Technologies Confidential 88 GENCLK_HALF DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACT OR ENABLE_ICEGATE REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL powerdown control 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified value. Default 1 0 1 The internally generated PLL frequency will be divided by 2 and then output. No phase shift. These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a user-implemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 89 SB_PLL40_PAD The SB_PLL40_PAD primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2) or the top IO bank (IO Bank 0), and the source clock is not required inside the FPGA. Ports PACKAGEPIN: PLL source clock that serves as the input to the SB_PLL40_PAD primitive. PLLOUTGLOBAL: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCORE: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBAL/PLLOUTCORE is locked to the PLL source on REFERENCECLK. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 7 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESETB: Active low input that asynchronously resets the PLL. BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBAL/PLLOUTCORE pins are held static at their last value. This function is enabled when the parameter ENABLE_ICEGATE is set to „1‟. ICE Technology Library - SiliconBlue Technologies Confidential 90 SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL40_PAD primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 91 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_M ODE_FEEDBACK Selects the mode for the Fine Delay Adjust block in the feedback path FIXED DYNAMIC FDA_FEEDBACK Sets a constant value for the Fine Delay Adjust Block in the feedback path DELAY_ADJUSTMENT_M ODE_RELATIVE Selects the mode for the Fine Delay Adjust block 0, 1,…,15 FIXED DYNAMIC FDA_RELATIVE Sets a constant value for the Fine Delay Adjust Block SHIFTREG_DIV_MODE Selects shift register configuration PLLOUT_SELECT Selects the signal to be output at the PLLOUTCORE and PLLOUTGLOBAL ports 0, 1,…,15 0,1 SHIFTREG_0deg SHIFTREG_90deg GENCLK Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_FEEDBACK parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FDA_FEEDBACK only if the setting of the DELAY_ADJUSTMENT_MODE_ FEEDBACK is FIXED. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_RELATIVE parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[7:4] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are additionally delayed by (n+1)*150 ps, where n = FDA_RELATIVE. Used if DELAY_ADJUSTMENT_MODE_ RELATIVE is “FIXED”. Used when FEEDBACK_PATH is “PHASE_AND_DELAY”. 0Divide by 4 1Divide by 7 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output without any phase shift. ICE Technology Library - SiliconBlue Technologies Confidential 92 GENCLK_HALF DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACT OR ENABLE_ICEGATE REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL powerdown control 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified value. Default 1 0 1 The internally generated PLL frequency will be divided by 2 and then output. No phase shift. These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a user-implemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 93 SB_PLL40_2_PAD The SB_PLL40_2_PAD primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2) or the top IO bank (IO Bank 0), and in addition to the PLL output, the source clock is also required inside the FPGA. Port A (Source Clock) Port B (Generated Clock) Ports PACKAGEPIN: PLL source clock that serves as the input to the SB_PLL_PAD primitive. PLLOUTGLOBALA: The signal on PACKAGEPIN appears on the FPGA at this pin, and drives a global clock network on the FPGA. Do not use this pin in an external feedback path to the PLL. PLLOUTCOREA: The signal on PACKAGEPIN appears on the FPGA at this pin, which drives regular FPGA routing. Do not use this pin in an external feedback path to the PLL. PLLOUTGLOBALB: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCOREB: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBAL port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBALB/PLLOUTCOREB is locked to the PLL source on PACKAGEPIN. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESET: Active low input that asynchronously resets the PLL. ICE Technology Library - SiliconBlue Technologies Confidential 94 BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBALA/PLLOUTCOREA pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTA is set to „1‟, and the LATCHINPUTVALUE signal is asserted. The PLLOUTGLOBALB/PLLOUTCOREB pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTB is set to „1‟, and the LATCHINPUTVALUE signal is asserted. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL40_2_PAD primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 95 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE _FEEDBACK Selects the mode for the Fine Delay Adjust block in the feedback path FIXED DYNAMIC FDA_FEEDBACK Sets a constant value for the Fine Delay Adjust Block in the feedback path DELAY_ADJUSTMENT_MODE _RELATIVE Selects the mode for the Fine Delay Adjust block 0, 1,…,15 FIXED DYNAMIC FDA_RELATIVE Sets a constant value for the Fine Delay Adjust Block SHIFTREG_DIV_MODE Selects shift register configuration PLLOUT_SELECT_PORTB Selects the signal to be output at the PLLOUTCOREB and PLLOUTGLOBALB ports 0, 1,…,15 0,1 SHIFTREG_0deg SHIFTREG_90deg Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_FEEDBACK parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBAL & PLLOUTCORE signals are delay compensated by (n+1)*150 ps, where n = FDA_FEEDBACK only if the setting of the DELAY_ADJUSTMENT_MODE _FEEDBACK is FIXED. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_RELATIVE parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[7:4] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are delayed w.r.t. the Port B signals, by (n+1)*150 ps, where n = FDA_RELATIVE. Used if DELAY_ADJUSTMENT_MODE _RELATIVE is “FIXED”. Used when FEEDBACK_PATH is “PHASE_AND_DELAY”. 0Divide by 4 1Divide by 7 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 ICE Technology Library - SiliconBlue Technologies Confidential 96 GENCLK GENCLK_HALF DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE_PORTA ENABLE_ICEGATE_PORTB REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL powerdown control Enables the PLL powerdown control 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified value. Default 1 0 1 0 1 The internally generated PLL frequency will be output to PortB. No phase shift. The internally generated PLL frequency will be divided by 2 and then output to PORTB. No phase shift. These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a user-implemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input Power-down control disabled Power-down controlled by LATCHINPUTVALUE input SB_PLL40_2F_CORE The SB_PLL40_2F_CORE primitive should be used when PLL is used to generate 2 different output frequencies, and the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA. Port A (Generated Clock) Generated Clock) Port B (Generated Clock) Ports REFERENCECLK: PLL source clock that serves as the input to the SB_PLL40_2F_CORE primitive. PLLOUTGLOBALA: Output clock generated by the PLL, drives a global clock network on the FPGA. ICE Technology Library - SiliconBlue Technologies Confidential 97 PLLOUTCOREA: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBALA port. PLLOUTGLOBALB: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCOREB: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBALB port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBALB/PLLOUTCOREB is locked to the PLL source on PACKAGEPIN. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESETB: Active low input that asynchronously resets the PLL. BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBALA/PLLOUTCOREA pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTA is set to „1‟, and the LATCHINPUTVALUE signal is asserted. The PLLOUTGLOBALB/PLLOUTCOREB pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTB is set to „1‟, and the LATCHINPUTVALUE signal is asserted. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL40_2F_CORE primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 98 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE _FEEDBACK Selects the mode for the Fine Delay Adjust block in the feedback path FIXED DYNAMIC FDA_FEEDBACK Sets a constant value for the Fine Delay Adjust Block in the feedback path DELAY_ADJUSTMENT_MODE _RELATIVE Selects the mode for the Fine Delay Adjust block 0, 1,…,15 FIXED DYNAMIC FDA_RELATIVE Sets a constant value for the Fine Delay Adjust Block SHIFTREG_DIV_MODE Selects shift register configuration PLLOUT_SELECT_PORTA Selects the signal to be output at the PLLOUTCOREA and PLLOUTGLOBALA ports 0, 1,…,15 0,1 SHIFTREG_0deg SHIFTREG_90deg Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_FEEDBACK parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are delay compensated by (n+1)*150 ps, where n = FDA_FEEDBACK only if the setting of the DELAY_ADJUSTMENT_MODE _FEEDBACK is FIXED. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_RELATIVE parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[7:4] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are delayed w.r.t. the Port B signals, by (n+1)*150 ps, where n = FDA_RELATIVE. Used if DELAY_ADJUSTMENT_MODE _RELATIVE is “FIXED”. Used when FEEDBACK_PATH is “PHASE_AND_DELAY”. 0Divide by 4 1Divide by 7 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is ICE Technology Library - SiliconBlue Technologies Confidential 99 GENCLK GENCLK_HALF PLLOUT_SELECT_PORTB Selects the signal to be output at the PLLOUTCOREB and PLLOUTGLOBALB ports SHIFTREG_0deg SHIFTREG_90deg GENCLK GENCLK_HALF DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE_PORTA ENABLE_ICEGATE_PORTB REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL powerdown control Enables the PLL powerdown control 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified value. Default 1 0 1 0 1 “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output to PortA. No phase shift. The internally generated PLL frequency will be divided by 2 and then output to PORTA. No phase shift. 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output to PortB. No phase shift. The internally generated PLL frequency will be divided by 2 and then output to PORTB. No phase shift. These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a user-implemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 100 SB_PLL40_2F_PAD The SB_PLL40_2F_PAD primitive should be used when the PLL is used to generated 2 different output frequencies, and the source clock of the PLL is driven by an input pad located in the bottom IO bank (IO Bank 2) or the top IO bank (IO Bank 0). Port A (Generated Clock) Port B (Generated Clock) Ports PACKAGEPIN: PLL source clock that serves as the input to the SB_PLL40_2F_PAD primitive. PLLOUTGLOBALA: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCOREA: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBALA port. PLLOUTGLOBALB: Output clock generated by the PLL, drives a global clock network on the FPGA. PLLOUTCOREB: Output clock generated by the PLL, drives regular FPGA routing. The frequency generated on this output is the same as the frequency of the clock signal generated on the PLLOUTLGOBALB port. LOCK: Output port, when HIGH, indicates that the signal on PLLOUTGLOBALB/PLLOUTCOREB is locked to the PLL source on PACKAGEPIN. EXTFEEDBACK: External feedback input to PLL. Enabled when the FEEDBACK_PATH parameter is set to EXTERNAL. DYNAMICDELAY: 4 bit input bus that enables dynamic control of the delay contributed by the Fine Delay Adjust Block. The Fine Delay Adjust Block is used when there is a need to adjust the phase alignment of PLLOUTGLOBAL/PLLOUTCORE with respect to REFERENCECLK. The DYNAMICDELAY port controls are enabled when the DELAY_ADJUSTMENT_MODE parameter is set to DYNAMIC. RESETB: Active low input that asynchronously resets the PLL. ICE Technology Library - SiliconBlue Technologies Confidential 101 BYPASS: Input signal, when asserted, connects the signal on REFERENCECLK to PLLOUTCORE/PLLOUTGLOBAL pins. LATCHINPUTVALUE: Active high input, when enabled, forces the PLL into low-power mode. The PLLOUTGLOBALA/PLLOUTCOREA pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTA is set to „1‟, and the LATCHINPUTVALUE signal is asserted. The PLLOUTGLOBALB/PLLOUTCOREB pins are held static at their last value only when the parameter ENABLE_ICEGATE_PORTB is set to „1‟, and the LATCHINPUTVALUE signal is asserted. SCLK, SDI, SDO: These pins are used only for internal testing purposes, and need not be instantiated by users. Parameters The SB_PLL40_2F_PAD primitive requires configuration through the specification of the following parameters. It is strongly recommended that the configuration of the PLL primitives be accomplished through the use of the PLL Configuration tool that is offered as part of the iCEcube2 software. ICE Technology Library - SiliconBlue Technologies Confidential 102 Parameter Name FEEDBACK_PATH Description Selects the feedback path to the PLL Parameter Value SIMPLE DELAY PHASE_AND_DELAY EXTERNAL DELAY_ADJUSTMENT_MODE _FEEDBACK Selects the mode for the Fine Delay Adjust block in the feedback path FIXED DYNAMIC FDA_FEEDBACK Sets a constant value for the Fine Delay Adjust Block in the feedback path DELAY_ADJUSTMENT_MODE _RELATIVE Selects the mode for the Fine Delay Adjust block 0, 1,…,15 FIXED DYNAMIC FDA_RELATIVE Sets a constant value for the Fine Delay Adjust Block SHIFTREG_DIV_MODE Selects shift register configuration PLLOUT_SELECT_PORTA Selects the signal to be output at the PLLOUTCOREA and PLLOUTGLOBALA ports 0, 1,…,15 0,1 SHIFTREG_0deg SHIFTREG_90deg GENCLK Description Feedback is internal to the PLL, directly from VCO Feedback is internal to the PLL, through the Fine Delay Adjust Block Feedback is internal to the PLL, through the Phase Shifter and the Fine Delay Adjust Block Feedback path is external to the PLL, and connects to EXTFEEDBACK pin. Also uses the Fine Delay Adjust Block. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_FEEDBACK parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[3:0] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are delay compensated by (n+1)*150 ps, where n = FDA_FEEDBACK only if the setting of the DELAY_ADJUSTMENT_MODE_ FEEDBACK is FIXED. Delay of the Fine Delay Adjust Block is fixed, the value is specified by the FDA_RELATIVE parameter setting Delay of Fine Delay Adjust Block is determined by the signal value at the DYNAMICDELAY[7:4] pins The PLLOUTGLOBALA & PLLOUTCOREA signals are delayed w.r.t. the Port B signals, by (n+1)*150 ps, where n = FDA_RELATIVE. Used if DELAY_ADJUSTMENT_MODE_ RELATIVE is “FIXED”. Used when FEEDBACK_PATH is “PHASE_AND_DELAY”. 0Divide by 4 1Divide by 7 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output to PortA. No phase shift. ICE Technology Library - SiliconBlue Technologies Confidential 103 GENCLK_HALF PLLOUT_SELECT_PORTB Selects the signal to be output at the PLLOUTCOREB and PLLOUTGLOBALB ports SHIFTREG_0deg SHIFTREG_90deg GENCLK GENCLK_HALF DIVR DIVF DIVQ FILTER_RANGE EXTERNAL_DIVIDE_FACTOR ENABLE_ICEGATE_PORTA ENABLE_ICEGATE_PORTB REFERENCECLK divider Feedback divider VCO Divider PLL Filter Range Divide-by factor of a divider in external feedback path Enables the PLL powerdown control Enables the PLL powerdown control 0,1,2,…,15 0,1,..,63 0,1,…,7 0,1,…,7 User specified value. Default 1 0 1 0 1 The internally generated PLL frequency will be divided by 2 and then output to PORTA. No phase shift. 0o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” 90o phase shift only if the setting of FEEDBACK_PATH is “PHASE_AND_DELAY” and SHIFTREG_DIV_MODE=0 The internally generated PLL frequency will be output to PortB. No phase shift. The internally generated PLL frequency will be divided by 2 and then output to PORTB. No phase shift. These parameters are used to control the output frequency, depending on the FEEDBACK_PATH setting. Specified only when there is a user-implemented divider in the external feedback path. Power-down control disabled Power-down controlled by LATCHINPUTVALUE input Power-down control disabled Power-down controlled by LATCHINPUTVALUE input ICE Technology Library - SiliconBlue Technologies Confidential 104 ICE Technology Library - SiliconBlue Technologies Confidential 105 Device Configuration Primitives SB_WARMBOOT iCE FPGA devices permit the user to load a different configuration image during regular operation. Through the use of the Warm Boot Primitive, the user can load one of 4 pre-defined configuration images into the iCE FPGA device. Note that this Warm Boot mode is different from the Cold Boot operation, which is executed during the initial device boot-up sequence. BOOT S1 S0 The selection of one of these 4 images is accomplished through 2 input signals, S1 and S0. In order to trigger the selection of a new image, an additional signal, BOOT, is provided. It should be noted that this signal is level-triggered, and should be used for every Warm Boot operation i.e. every time the user wishes to load a new image into the device. The successful instantiation of this primitive also requires the user to specify the address locations of the 4 images. These addresses should be specified in the iCEcube2 software as per the Warm Boot Application Note. Verilog Instantiation SB_WARMBOOT my_warmboot_i ( .BOOT (my_boot), .S1 (my_sel1), .S0 (my_sel0) ); //Level-sensitive trigger signal //S1, S0 specify selection of the configuration image ICE Technology Library - SiliconBlue Technologies Confidential 106