FIN324C 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Features Description Ultra-Low Operating Power: ~4mA at 5.44MHz No External Timing Reference Needed Direct Support for Motorola®-Style R/W Microcontroller Interface Direct Support for Intel®-Style /WE, /RE Microcontroller Interface The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system. The dual strobe inputs allow implementation of dual-display systems with a single pair of µSerDes. The FIN324C can accommodate RGB, microcontroller, or SPI mode interfaces. Read and write transactions are supported when operating with a Motorola-style microcontroller interface for one or both displays. Unlike other SerDes solutions, no external timing reference is required for operation. 15MHz Maximum Strobe Frequency Available in BGA and MLP packages High ESD protection: >14.5kV HBM Supports Dual-Display Implementations with RGB or Microcontroller Interface SPI Mode Support Single Device Operates as a Serializer or Deserializer Utilizes Fairchild’s Proprietary CTL Serial I/O Technology Wide Parallel Supply Voltage Range: 1.60 to 3.0V Low Power Core Operation: VDDS/A=2.5 to 3.0V Voltage Translation Capability Across Pair with No External Components Power-Saving Burst-Mode Operation Applications The FIN324C is designed for ultra-low power operation. Reset (/RES) and standby (/STBY) signals put the device in an ultra-low power state. In standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. The device utilizes Fairchild’s proprietary ultra-low power, low-EMI Current Transfer Logic™ (CTL) technology. The serial interface disables between transactions to minimize EMI at the fundamental serial interface and to conserve power. LV-CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. The serialization bit clock is generated internally to the FIN324C. The minimum bit clock frequency is always great enough to handle the maximum strobe frequency. Single or Dual 16/18-Bit RGB Cell Phone Displays Related Application Notes Single or Dual 16/18-Bit Cell Phone Displays with Microcontroller Interface AN-5058 µSerDes™ Family Frequently Asked Questions Single or Dual Mobile Display at QVGA or HVGA Resolution AN-5061 µSerDes™ Layout Guidelines © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 AN-6047 FIN324C Reset and Standby www.fairchildsemi.com µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays March 2007 Order Number Operating Temperature Package Pb-Free Range Package Description Packing Method FIN324CMLX MLP040A Yes -30 C to 70 C 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Tape & Reel FIN324CGFX BGA42A Yes -30 C to 70 C 42-Ball, Ultra Small Scale Ball Grid Array (USSBGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch Tape & Reel Typical Application Diagram LCD ‘A’ WE/PCLK WE/PCLK CKS Baseband / Microprocessor Data/Control 2 Data/Control FIN324 FIN324 DS 24 24 WE/PCLK LCD ‘B’ Supports optional seconda ry display Figure 1. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 Typical Application Diagram µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Ordering Information www.fairchildsemi.com 2 Pin I/O Type # Pins Description of Signals Chip-Level Control Signals M/S IN 1 LV-CMOS Master/Slave Control Input: M/S=1 MASTER, M/S =0 SLAVE /RES IN 1 LV_CMOS RESET signal and power-down signal /RES=0: Resets and powers down all circuitry /RES=1: Device enabled 1 LV-CMOS standby signal or output slew rate signal: M/S=1: /STBY M/S=0: RSLEW /STBY=0: Device powered down RSLEW=1: Fast edge rate RSLEW=0: Slow edge rate /STBY(SLEW) IN LV-CMOS parallel / SPI display interface PAR/SPI IN 1 Tells the SerDes it is interfacing with a sub-display with a SPI interface PAR/SPI=1: Parallel Interface PAR/SPI=0: SPI Interface using STRB0(WCLK0) LV-CMOS Input: Master clock source select input. CKSEL(H) IN 1 When M/S=1: CKSEL (passed in serial stream) CKSEL=1: STRB1(WCLK1) Active CKSEL=0: STRB0(WCLK0) Active When M/S=0: This pin must be tied to VDDP. Parallel Interface Signals Master Functionality (Slave Functionality) DP[17:0] DP[6]({SCLK}) DP[7]({SDAT}) I/O 18 CNTL[5:0] {SCLK}CNTL[5] {SDAT}CNTL[4] R/W I/O 6 LV-CMOS data I/O. I/O direction controlled by M/S pin and R/W internal state. DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only) DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only) LV-CMOS data I/O. I/O direction controlled by M/S pin M/S=1: Inputs M/S=0: Outputs In SPI mode, CNTL[5] is SCLK; CNTL[4] is SDAT for master and slave LV-CMOS data I/O. I/O direction controlled by M/S pin. M/S=1: Input M/S=0: Output I/O 1 STRB0(WCLK0) I/O 1 LV-CMOS data I/O. Function controlled by M/S pin. M/S=1: STRB0 Input M/S=0: WCLK0 Output STRB1(WCLK1) I/O 1 LV-CMOS Data I/O. Function controlled by M/S pin. M/S=1: STRB1 Input M/S=0: WCLK1 Output © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 Functional operation: R/W=1: Read R/W=0: Write µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Pin Definitions www.fairchildsemi.com 3 CKS+(DS+) CKS-(DS-) Diff Serial I/O 2 Bi-directional serial I/O CKS+/CKS- when M/S=1 DS+/DS- when M/S=0 DS+(CKS+) DS-(CKS-) Diff Serial I/O 2 Bi-directional serial I/O DS+/DS- when M/S=1 CKS+/CKS- when M/S=0 Supply 1 Power supply for parallel I/O and internal circuitry. Supply Signals VDDP VDDS Supply 1 Power supply for serial I/O. VDDA Supply 1 Power supply for internal bit clock generator. GND Supply 2 Ground Pins: BGA - C1, D2, E3; MLP - center pad, 12 Notes: 1. () Indicate the operation of the pin when operating as a slave device. {} Indicate SPI Mode functionality. ({}) Slave Mode and SPI mode functionality except as noted. 2. Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Serial I/O Signals Normal Functionality www.fairchildsemi.com 4 42 FBGA Package 3.5mm x 4.5mm (.5mm Pitch) Pin Assignments (Top View) 1 2 3 4 5 6 A 6 A R/W {SDAT} CNTL[4] CNTL[2] STRB0 (WCLK0) DP[17] DP[16] B B CKSEL (H) {SCLK} CNTL[5] CNTL[3] STRB1 (WCLK1) DP[15] DP[14] C C GND VDDP CNTL[1] CNTL[0] DP[13] DP[12] D D CKS+ (DS+) GND M/S DP[11] DP[9] DP[10] E E CKS(DS-) VDDS GND DP[2] DP[7] ({SDAT}) DP[8] F F DS(CKS-) VDDA PAR/SPI DP[0] DP[4] DP[6] ({SCLK}) G G DS+ (CKS+) /RES /STBY (SLEW) DP[1] DP[3] DP[5] 31 DP[17] 32 STRB1(WCLK1) 33 STRB0(WCLK0) 34 CNTL[0] 35 CNTL[1] 38 {SDAT}CNTL[4] BGA Pin Assignments 1 30 DP[16] 2 29 DP[15] 3 28 DP[14] 4 27 DP[13] 5 26 DP[12] Ground Pad 6 25 VDDP 20 /STBY(SLEW) GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] DP[6]{SCLK} DP[7]{SDAT} 19 21 DP[8] 18 22 DP[9] 10 17 23 DP[10] 9 13 24 DP[11] 8 12 7 11 CKSEL(H) CKS+(DS+) CKS-(DS-) VDDS VDDA DS-(CKS-) DS+(CKS+) /RES PAR/SPI M/S 39 {SCLK}CNTL[5] 40 R/W Figure 2. 36 CNTL[2] 5 16 4 37 CNTL[3] 3 15 2 14 1 Figure 3. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Pin Assignments MLP Pin Assignments (40 Pins, 6x6mm, .5mm Pitch, Top View) www.fairchildsemi.com 5 (M/S) Master / Slave Selection: A given device can be configured as a master or slave device based on the state of the M/S pin. (/RES, /STBY) Reset and Standby Mode Functionality: Reset and standby mode functionality is determined by the state of the /RES and /STBY signals for the master device and the /RES and internal standby-detect signal for the slave device. The /RES control signal has a filter that rejects spurious pulses on /RES. Table 1. Master/Slave M/S Configuration 0 Slave Mode 1 Master Mode Table 4. Reset and Standby Modes (PAR/SPI) SPI Mode Selection: The PAR/SPI signal configures STRB0(WCLK0) for SPI mode write operation. STRB1(WCLK1) always operates in parallel mode. Control signals CNTL[5:0] all pass in SPI mode. In SPI mode, the SCLK signal is used to strobe the serializer. SPI mode supports SPI writes only. M/S=1 MASTER M/S=0 SLAVE 0 SDAT=CNTL[4] SCLK=CNTL[5] /CS=STRB0 SDAT=DP[7] & CNTL[4] SCLK=DP[6] & CNTL[5] /CS=WCLK0 1 Parallel Mode Parallel Mode /STBY(3) Master Slave 0 X Reset Mode Reset Mode 1 0 Standby Mode Standby Mode(3) 1 1 Operating Mode Operating Mode Note: 3. The slave device is put into standby mode through control signals sent from the master device. Table 2. Channel 0 PAR/SPI Configuration PAR /SPI /RES Table 5. Reset and Standby Mode States Pin (CKSEL) Strobe Selection Signal: The CKSEL signal exists only on the master device and determines which strobe signal is active. The active strobe signal is selected by CKSEL and PAR/SPI inputs. Master Reset / Standby Slave Reset Slave Standby DP[17:0] Disabled Low Last data CNTL[5:0] Disabled Low Last data STRB[0:1] (WCLK[0:1]) Disabled High High (SLEW) Slew Control: The slew control operates only when in slave mode. This signal changes the edge rate of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0 signals to optimize edge rate for the load being driven. Master read mode outputs have “slow” edge rates. Table 3. PAR/SPI PAR /SPI CKSEL Master Strobe Source Slave Strobe Source 0 0 CNTL[5] DP[6] & CNTL[5] /STBY (SLEW) Slave M/S=0 0 1 STRB1 WCLK1 0 “Slow” 1 0 STRB0 WCLK0 1 “Fast” 1 1 STRB1 WCLK1 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 Table 6. Slew Rate Control µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays System Control Pins www.fairchildsemi.com 6 System Control Signals Parallel I/O Signals The system control signals consist of M/S, /RES, /STBY(SLEW), PAR/SPI, and CKSEL. For connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. This allows these signals to be tied HIGH to either a VDDS or VDDP supply without static current consumption. These signals are all LV-CMOS inputs and should never be allowed to float. The parallel data port signals consist of the DP[17:0], CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals. These signals have built-in voltage translation, allowing the signals of the master and slave to be connected to different VDDP supply voltages. Serial I/O Signals CTL I/O Technology Serial I/O Orientation Logic The serial I/O is implemented using Fairchild’s proprietary differential CTL I/O technology. During data transfers, the serial I/O are powered up to a normal operating mode around .5V. Upon completion of a data transfer, the serial I/O goes to a lower power mode around VDDS. The serial I/O signal traces should not cross between the master and the slave. The pin locations have been designed to eliminate the need to cross traces. See Table 7, Figure 4 and Figure 5. Table 7. Serial Pin Orientation Master (M/S=1) (Pad/Pin #) Package CKS+ CKS- Slave (M/S=0) (Pad/Pin #) DS- DS+ CKS+ CKS- DS- DS+ MLP 2 3 6 7 7 6 3 2 BGA D1 E1 F1 G1 G1 F1 E1 D1 5 11 12 VDD A 26 28 CKS- 3 6 (CKS-) 25 29 CKS+ 2 7 (CKS+) 24 30 CKSEL(H) 1 8 /RES 23 9 PAR/SPI 22 10 M/S 21 6 BGA Master A Figure 4. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 BGA Pair Figure 5. 31 5 32 4 33 VDDS 34 27 27 35 VDD S 36 4 37 5 38 VDDA 39 26 40 (DS-) MLP Pair 29 28 20 4 13 3 19 3 14 6 18 2 15 DS- 17 1 16 25 30 MLP Slave 16 G <CKS+> 17 (DS+) 15 F 18 CKSEL(H) 2 14 BGA Slave 19 1 7 11 B <DS-> E <CKS-> CKS+ C 8 DS+ 24 13 D D 12 CKS- <DS+> 40 E 9 39 DS- 10 /RES 38 F M/S PAR/SPI MLP Master 22 23 DS+ G 21 37 1 36 2 35 3 34 4 33 5 31 6 32 B C 20 A µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays LV-CMOS I/O Signals www.fairchildsemi.com 7 3. 4. 5. During a write data transfer, DP[17:0], CNTL[5:0], R/W, and CKSEL are serialized and transmitted by the master to the slave. The slave receives the signals, outputs the data and control signals, and generates either a WCLK0 or WCLK1 pulse based on the value of CKSEL. The CKSEL signal must remain stable throughout the transaction. 6. 7. Captures data from serial transfer. Turns around serial I/O. Internally decodes that this is a READ transaction and the WCLK to use. Outputs control signals, 3-state DP data bus. Outputs falling edge of WCLK pulse. Slave Serializer Read Operation (Read-Data Phase) The slave serializer is enabled on the tail end of the Read-Control Phase of operation. The operation of the serializer is identical to the master serialization except that the strobe signal is generated internally and only the data bits DP[17:0] are captured. Read transactions have two phases: The ReadControl Phase, where CNTL[5:0], R/W, CKSEL are transmitted to the deserializer; and the Read-Data Phase, where the DP[17:0] signals of the slave are read and transmitted back to the master device. The slave device generates its own strobe signal for latching in the data. Slave data must be valid prior to the WCLKn signal going HIGH. Microcontroller Read Sequence (Read-Data Phase): 1. Display device outputs data onto DP bus on falling edge of WCLK. 2. Captures parallel data on generated rising edge of WCLK signal. 3. Serializes data stream. 4. DP signals are sent. 5. CNTL signals are sent as 0. 6. Turns serial I/O around, awaiting next transaction. Master Serializer Operation (Read Control Phase) When the R/W signal is asserted HIGH and the STROBE signal transitions LOW, the Read-Control Phase of the read cycle is initiated. The R/W signal must not transition until the READ cycle completes. For a READ transaction, only eight control signals are captured. The 18 DP bits are ignored during the READ operation. The following sequence must occur for data to be serialized properly: Master Deserializer Read Operation (Read-Data Phase): Initially the deserializer is in low-power operation. The deserializer wakes up when it detects CKSO+ and CKSO- transition from LOW to normal operating range. Microcontroller Read Sequence (Read-Control Phase): 1. Selects input strobe source (CKSEL= 0 or 1). 2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]). 3. STROBE Signal transitions LOW. 4. Captures control bits. 5. Device leaves burst standby mode. 6. Serializes and sends control bits. 7. Serializer turns around serial I/O waiting for data. Microcontroller Read Sequence (Read-Data Phase): 1. Master deserializer wakes up when the CKSI+ and CKSI- signals reach valid levels. 2. Begins receiving valid serial stream. 3. Outputs data DP[17:0]. 4. Turns serial I/O around and goes to burst standby mode. 5. Processor asserts rising edge of strobe signal to capture data. Slave Deserializer Operation (Read-Control Phase) Microcontroller Read Sequence (Read-Control Phase): 1. Deserializer leaves burst standby mode. 2. Begins receiving valid serial stream. SPI WRITE transaction As shown in Table 2, SDAT and SCLK are output on multiple pins. The DP[7] and DP[6] connections can be used for displays with dual-mode operation and the data pins are multiplexed with the SPI signals. CNTL[5] and CNTL[4] signals can be used when the signals are not multiplexed. SPI mode is activated by asserting the PAR/SPI signal low on both the master and slave device. A SPI write is only performed when CKSEL=0. During a SPI transaction, SCLK must be connected to CNTL[5] and is the strobe source for serialization. SDAT is assumed to be on CNTL[4] and all of the remaining control signals and STRB0 are serialized. STRB0 should be connected to the SPI mode chip select. On the rising edge of SCLK, all eight control signals (CNTL[5:0], R/W, CKSEL) are captured and serialized. The data signals are not sent. The /CS signal on STRB0 is captured in bit position CNTL[5]. The deserializer captures the serial stream and outputs it to the parallel port. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Master/Slave READ/WRITE transactions www.fairchildsemi.com 8 Baseband Processor VDDP1 VDDP2 VDDS/A C2 E2 C2 F2 /CS PCLK B4 DP[17:0] C4 CNTL[0] C3 CNTL[1] D1 A3 CNTL[2] CKS+ E1 B3 CKSCNTL[3] A2 CNTL[4] G1 DS+ B2 F1 CNTL[5] DSA1 R/W D3 M/S VDDP1 GPIO F3 G3 /STBY G2 /RES CKSEL B1 PAR/SPI /STBY /RES CKSEL Notes: 1. 2. 3. 4. 5. Figure 6. WCLK0 A4 WCLK1 B4 STRB0 STRB1 D4:G6 R,G,B[5:0] Hsync_D/C Vsync SD OE RESET E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 C4 C3 A3 B3 OE A2 B2 NC A1 NC D3 F3 VDDP2 G3 Edge Rate Control Option SLEW must be connected to VDDS or GND for low power. G2 B1 Write-only Interface. Assumes BGA die on display. /CS used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display Baseband Processor VDDP1 VDDS/A VDDP2 VDDS/A C2 E2 C2 E2 F2 VDDP VDDS/A A4 /WE PCLK B4 D4:G6 R,G,B[5:0] Hsync_ADDR Vsync SD OE RESET /CS GPIO F2 VDDP VDDS/A VDDP VDDS/A A4 Sub-Display Data [7:0] D/C /CS RESET P/S R/W VDDS/A E2 C4 C3 A3 B3 A2 B2 VDDP1 A1 D3 F3 /STBY /RES CKSEL G3 G2 B1 Notes: 1. 2. 3. 4. 5. Figure 7. WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CNTL[3] CKSCNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S /RES CKSEL F2 VDDP VDDS/A STRB0 STRB1 PAR/SPI /STBY Sub-Display Data [7:0] ADDR /WE RESET P/S /CS E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 C4 C3 A3 B3 OE A2 B2 A1 NC D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDS or GND for low power. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Application Diagrams Write-only Interface. Assumes BGA die on display. /WE used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 www.fairchildsemi.com 9 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Application Diagrams (Continued) Module 1 Baseband Processor VDDP1 C2 VDDS/A E2 F2 VDDP VDDS/A A4 /CS PCLK B4 D4:G6 R,G,B[5:0] Hsync Vsync SD D/C SDAT SCLK C4 C3 A3 B3 A2 B2 A1 GPIO VDDP1 D3 F3 G3 /STBY G2 /RES CKSEL B1 Notes: 1. 2. 3. 4. 5. 6. Figure 8. VDDP2 VDDS/A F6 SCLK DP[6] C2 E2 E5 SDAT DP[7] F2 VDDP VDDS/A WCLK0 A4 WCLK1 B4 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY E3 D2 C1 /RES CKSEL DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H Sub-Display SCLK SDAT /CS D/C RESET P/S Main Display PCLK R,G,B [5:0] Hsync Vsync SD D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 NC D3 F3 VDDP2 G3 Edge Rate Control Option SLEW must be connected to VDDS or GND for low power. G2 B1 Write-only interface (R/W hardwaired LOW). SPI sub-display interface PAR/SPI=LOW for both . master and slave. SCLK connected to CNTL[5]; SDAT connected to CNTL[4]. Shared data pin SDAT; SCLK connections on sub-display. Assumes BGA die on display. Pin numbers for BGA package. Dual Display with RGB Main Display and SPI Sub-Display Interface Module 1 Baseband Processor VDDP1 C2 VDDS/A VDDP2 E2 C2 F2 VDDP VDDS/A A4 /CS0 /CS1 DATA[17:0] D/C RESET 0 RESET 1 B4 D4:G6 C4 C3 A3 B3 A2 B2 R/W A1 VDDP1 D3 GPIO F3 G3 /STBY G2 /RES CKSEL B1 Notes: 1. 2. 3. 4. Figure 9. WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S /RES CKSEL F2 VDDP VDDS/A STRB0 STRB1 PAR/SPI /STBY Sub-Display DATA [17:0] D/C /CS0 RESET 0 P/S R/W VDDS/A E2 E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H Main Display /CS1 DATA[17:0] D/C D4:G6 C4 C3 A3 B3 A2 B2 RESET 1 R/W NC NC NC A1 D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDS or GND for low power. R/W interface. R/W signal connected to baseband . microprocessor. Assumes BGA die on display. PAR/SPI connected HIGH to indicate parallel operation. . Pin numbers for BGA package. R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 www.fairchildsemi.com 10 Module 1 Baseband Processor VDDP1 VDDS/A C2 E2 F2 A4 DATA[17:0] ADDR B4 D4:G6 C4 C3 A3 /CS0 /CS1 B3 A2 B2 A1 VDDP1 D3 GPIO F3 G3 /STBY G2 /RES CKSEL0 CKSEL1 B1 VDDS/A C2 E2 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ CNTL[5] DS- F1 R/W M/S /RES CKSEL Notes: 1. 2. 3. 4. 5. Figure 10. F2 WCLK0 A4 WCLK1 B4 STRB0 STRB1 PAR/SPI /STBY Sub-Display /RE /WE DATA[7:0] ADDR /CS0 Main Display /RE /WE DATA[17:0] ADDR VDDP VDDS/A VDDP VDDS/A /RE /WE VDDP2 E3 D2 C1 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H D4:G6 C4 C3 A3 B3 /CS1 A2 NC B2 NC A1 D3 F3 G3 G2 B1 VDDP2 Edge Rate Control Option SLEW must be connected to VDDS or GND for low power. Dual display R/W Intel® interface. Assumes BGA die on display. GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W. . selects. Displays selected via the chip Pin numbers for BGA package. Dual R/W x86-Style Microcontroller Display Interface Additional Application Information Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not allow noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential serial wires. Design goal of 100-ohms differential characteristic impedance. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Application Diagrams (Continued) Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales rep or contact Fairchild directly. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 www.fairchildsemi.com 11 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VDD TSTG Min. Max. Unit Supply Voltage -0.5 +3.6 V All Input/Output Voltage -0.5 VDDP+0.5 V Storage Temperature Range -65 150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature (soldering, 4 seconds) +260 °C IEC 61000 Board Level 15 kV HBM, 1.5kΩ, 100pF 8.5 kV HBM, 1.5kΩ, 100pF, Serial I/0 pins 14.5 kV MM, 0Ω, 200pF 400 V ESD Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VDDA, VDDS VDDP TA (4) Parameter Min. Max. Unit 2.5 3.0 V Supply Voltage 1.6 VDDA/S V Operating Temperature -30 +70 °C Supply Voltage Note: 4. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to VDDA/VDDS. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Absolute Maximum Ratings www.fairchildsemi.com 12 Values are provided for over-supply voltage and operating temperature ranges unless otherwise specified. Symbol Parameter Test Conditions Min. Max. Units VIH Input High Voltage 0.7 x VDDP VDDP V VIL Input Low Voltage GND 0.3 x VDDP V VOH Output High Voltage VOL Output High Voltage IIN SLEW=0 IOH = -250µA SLEW=1 IOH = -1mA V 0.8 x VDDP SLEW=0 IOL = 250µA SLEW=1 IOL = 1mA Input Current 0.2 x VDDP V 5 µA -5 DC Serial I/O Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Units IODH1 Active Output HIGH Source Current M/S=1, R/W=0,VOS=0.7V 1.5 mA IODL1 Active Output LOW Sink Current M/S=1, R/W=0, VOS=0.7V 0.8 mA IODSTBY Standby Burst Output HIGH Source Current M/S=1, R/W=0, VOS=1.0V 130 µA VSTBY Output Voltage in Standby or Reset M/S=1, /RST=1, /STBY=0 IOH=-100µA VDDS V Input Voltage Ground Offset Relative to Driver 0 V VGO M/S=0, /RST=0 RTERM Termination Resistor Internal RTERM CKS+(DS+)=0.9V CKS-(DS-)=0.8V Note: 5. Actual application cable is terminated with 150Ω on both sides. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 125 150 175 Ω µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual DC Electrical Characteristics – LV CMOS I/Os www.fairchildsemi.com 13 Symbol Parameter VDDA/S=2.75V, M/S=1, VDDP=1.8V, /STBY=1, /RES=1 5.44MHz 4 IDYN_SER Dynamic Current of Master Device 12.00MHz 7 15.00MHz 8 Dynamic Current of Slave Device VDDA/S=2.75V, M/S=0 VDDP=1.8V, /STBY=1, /RES=1, CL= 0pF 5.44MHz 5 12.00MHz 8 15.00MHz 10 IBRST_M Burst Standby Current of Master VDDA/S=2.75V, VDDP=1.8V, M/S=1, /STBY=1, /RST=1, No STROBE Signal, CL=0pF 1.1 mA IBRST_S Burst Standby Current of Slave VDDA/S=2.75V, VDDP=1.8V, M/S=0, /STBY=1, /RST=1, No STROBE Signal, CL=0pF 1.8 mA Standby Current Serializer or Deserializer VDDS/A=VDDP=3.0V, /STBY=0, /RST=1, STRB1=5.44MHz, CL=0pF IDYN_DES ISTBY Test Conditions Min. Typ. Max. Units mA mA 10 µA AC Operating Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter fWSTRB0 Write Strobe Frequency CKSEL=0 STRB0 (PRS1) fWSTRB1 Write Strobe Frequency CKSEL=1 STRB1 fRSTRB Read Strobe Frequency tR, tF Test Conditions Min. Typ. Max. Units 0 8 MHz 0 15 MHz 0 2 MHz 40 ns (6) Input Edge Rates tS1 Write Mode Setup Time DP before STRBn ↑, See Figure 11 5 ns tH1 Write Mode Hold Time DP after STRBn ↑, See Figure 11 15 ns tS2 READ Mode Setup Time R/W, CNTL before STRBn ↓ See Figure 12 0 ns tH2 READ Mode Hold Time R/W, CNTL after STRBn ↓ See Figure 12 16 ns tS-STRB CKSEL to STRBn Setup Time CKSEL before active edge STRBn See Figure 13, Figure 14 50 ns Allowed DS-CKS Input Signal Skew Deserializer Mode Max. Internal Oscillator Frequency See Figure 18 -150 tSKEW_DS-CKS (7) 0 150 ps µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Power Characteristics Notes: 6. Characterized, but not production tested. 7. Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 www.fairchildsemi.com 14 Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol tR0, tF0 Parameter Output Edge Rates of WCLK0,WCLK1 Test Conditions Min. SLEW=0, CL=5pF 20% to 80%(8) Typ. 8 SLEW=0; CL=10pF 30% to 70% 12 (8) SLEW=1, CL=5pF 20% to 80% tR1, tF1 Output Edge Rates of R/W, DP[17:0] CNTL[5:0] SLEW=0, CL=5pF 20% to 80% 8 22 (8) SLEW=0; CL=10pF 30% to 70% 12 SLEW=1, CL=5pF 20% to 80% tPDV-WR0 tPDV-WR1 tPDV-RD tPDV-SPI ns 10 (8) tCS Units 17 (8) (8) Max. ns 17 CNTL[5:0],R/W to Falling Edge of WCLKn M/S=0(9), See Figure 15 0 4 ns DP, CNTL to WCLK0 ↑ PAR/SPI=1(9), See Figure 15 DP, CNTL to WCLK1 ↑ CNTL to WCLKn ↑ Data, CNTL to SCLK ↑ 50 60 ns (9) 18 24 ns (9) 200 224 ns 40 60 ns 50 56 ns 18 20 ns 200 220 ns 40 56 ns PAR/SPI=1 , See Figure 15 PAR/SPI=1 , See Figure 17 (9) PAR/SPI=0 , See Figure 16 (9,10) tPWL-WR0 WCLK0 Pulse Width Low Write Mode M/S=0, R/W=0, PAR/SPI=1 See Figure 15 tPWL-WR1 WCLK1 Pulse Width Low Write Mode M/S=0, R/W=0, PAR/SPI=1 See Figure 15 tPWL-RD Pulse Width Low of WCLK Read Mode M/S=0, R/W=1, PAR/SPI=1 See Figure 17 tPWL-SPI Pulse Width Low of WCLK SPI Mode M/S=0, R/W=0, PAR/SPI=0 See Figure 16 (9,10) (9,10) (9, 10) Notes: 8. Characterized, but not production tested. 9. Indirectly tested through serial clock frequency and serial data bit tests. 10. Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or SLEW=1. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual AC Deserializer Specifications www.fairchildsemi.com 15 Symbol Parameter Test Conditions Typ.(13) Max. Units (11,12) tPD-WR0 Write Latency WRITE Mode, CKSEL=0 See Figure 15 147 ns 111 ns (11,12) tPD-WR1 Write Latency WRITE Mode, CKSEL=1 See Figure 15 tPD-RD Total Read Latency READ Mode See Figure 17 tPD-RDC Read Control Latency READ Mode See Figure 17 tPD-RDD Read Data Latency READ Mode See Figure 17 tPD-SPI SPI Write Latency SPI-WRITE Mode See Figure 16 (11,14) 340 480 ns (11,15) 276 ns 84 ns 115 ns (11,16) (11,17) Notes: 11. Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator frequency. 12. Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 13. Assumes propagation delay across the flex cable and through the I/Os of 20ns. 14. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase latency (tPD-RDD). tPD-RD = tPD-RDC+ tPD-RDD. 15. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable flight times and I/O propagation delays. 16. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable flight times and I/O propagation delays. 17. SPI–Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. AC Oscillator Specifications Symbol fOSC Parameter Test Conditions Serial Operating Frequency Min. Typ. Max. Units 240 275 310 MHz tOSC-STBY Oscillator Stabilization Time After Standby VDDA=VDDS=2.75V /RES=1, /STBY ↑ Transition 15 30 µs tOSC-RES Oscillator Stabilization Time After Reset VDDA=VDDS=2.75V /STBY=1, /RES ↑ Transition 30 50 µs © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual AC Data Latencies www.fairchildsemi.com 16 Symbol Parameter tVDD-OFF Power Down Relative (18) to /RES Test Conditions Min. See Figure 20 Typ. Max. Units 20 µs 0 ns 200 ns (19) tSTRB-RES /RES after last STRBn ↑ M/S=0 or 1, /STBY=1, R/W=0 See Figure 20 tSTRB-STBY Standby time after last strobe M/S=0 or 1, /STBY=1 See Figure 20 Master/Slave Reset Disable Time M/S=1 /STBY=1, /RES=↓ See Figure 20 Allowed Skew between VDDP and VDDA/S(21) Figure 19 tVDD-RES Minimum Reset Low Time After VDD Stable M/S=0 /STBY=1, /RES=↑ See Figure 19 20 µs tRES-STBY /STBY Wait Time After /RES ↑ M/S=1 /RES=1, /STBY=↓ See Figure 19 20 µs 30 µs tRES-OFF tVDD-SKEW tDVALID /STBY to Active Edge of Strobe (20) 15 -∞ (22) M/S=0 /RES=1 See Figure 19 20 µs +∞ ms (23) Notes: 18. Timing allows the device to completely reset prior to powering down. 19. Internal reset on the filter allows assertion prior to completion of read or write date transfer. 20. Timing ensures that last write transaction is complete prior to going into standby. 21. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being consumed. Guaranteed by characterization. 22. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that /RES be held low during the power supply ramp. 23. STRBn must be held off until internal oscillator has stabilized. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual AC Reset and Standby Timing www.fairchildsemi.com 17 Setup Time Setup Time tS1 STROBE tS2 STRBn DP,CNTL Data Hold Time CNTL,R/W Control Hold Time tH1 STROBE tH2 STRBn DP,CNTL Data CNTL,R/W Setup: CKSEL=0 or 1, R/W=0 Figure 11. Setup: CKSEL=0 or 1, R/W=1 Master Write Setup and Hold Time Figure 12. tS-STRB tS-STRB STRB0 STRB1 STRB1 CKSEL CKSEL Data tS-STRB CNTL Setup: CKSEL=0 or 1, R/W=0 Figure 13. Master Read Setup and Hold Time tS-STRB STRB0 DP,CNTL Control Data Setup: CKSEL=0 or 1, R/W=1 CKSEL Write Setup Time Figure 14. CKSEL Read Setup Time STRBn STRBn CKS CKS DS DS tPD-WRn tPD-SPI DP CNTL WCLKn tCSn tPWL-WRn SDAT tPDV-WRn SCLK tCS µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Typical Performance Characteristics tPWL-SPI tPDV-SPI Setup: CKSEL=0 or 1, R/W=0, PAR/SPI=1 Setup: CKSEL=0, R/W=0, PAR/SPI=0 Figure 15. Slave Write Mode Timing © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 Figure 16. Slave SPI Mode Timing www.fairchildsemi.com 18 tPD-RD STRBn CKS DS tPD-RD C tPD-RD D CNTL SLV tPW L-RD n tCSn WCLKn] tPDV-RD n DPSLV DPMSTR Setup: CKSEL=0 or 1, R/W=1, PAR/SPI=1 Figure 17. Slave Read Mode Timing CKS+ CKS- VDIFF=0 DS+ VDIFF=0 DS- VID/2 tSKEW_DS-CKS Figure 18. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 Allowed Differential Input Signal Skew µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Typical Performance Characteristics (Continued) www.fairchildsemi.com 19 VDDP tVDD-SKEW VDDS/A tVDD-RES /RES tRES-STBY Standby Mode /STBY Dynamic Mode Valid Data DP[23:0],R/W STRBn tDVALID CKS DS OFF Deserializer Figure 19. ON Power-Up Timing VDDP VDDS/A /RES /STBY tVDDOFF tSTRB-RES Dynamic Mode Standby Mode tSTRB-STBY STROBE tRES-OFF µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Typical Performance Characteristics (Continued) Deserializer ON Figure 20. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 OFF Power-Down Timing www.fairchildsemi.com 20 Dimensions are in millimeters unless otherwise noted. (DATUM A) Figure 21. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Physical Dimensions 40-Lead, Molded Leadless Package (MLP) www.fairchildsemi.com 21 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 22. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 42-Ball, Ball Grid Array (BGA) Package www.fairchildsemi.com 22 ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ ® The Power Franchise HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ TinyBoost™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ μSerDes™ ® UHC UniFET™ VCX™ Wire™ ™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support, which, (a) are intended for surgical implant into the body or device, or system whose failure to perform can be (b) support or sustain life, and (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in a significant injury of the user. 3 PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. Rev. I24 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5 www.fairchildsemi.com 23