ispMACH® 4000ZE Evaluation Board User’s Guide February 2009 Revision: EB35_01.2 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Introduction The ispMACH 4000ZE Evaluation Board is a convenient platform for evaluation, testing and development with the Lattice ispMACH 4000ZE CPLD. The board features an ispMACH 4064ZE or ispMACH 4256ZE CPLD in a spacesaving 144-ball csBGA package. A variety of interfaces are provided for device programming, logical input, output/display, and I/O connection. A USB microcontroller and Lattice MachXO™ device implement the logic required for easy programming of the ultra low-power ispMACH 4000ZE CPLD. A USB connection provides ample power for operation of the ispMACH 4000ZE and all other components on the board. On-board regulators provide the voltages necessary for all components. Key Features • 7-segment LCD • 8 LEDs • 8-bit DIP switch • 2 non-debounced input buttons • General prototype area • General test point area • 24 MHz oscillator • Jumpers between regulators for power measurement Also included with this board: • USB cable for programming 2 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Figure 1. ispMACH 4000ZE Evaluation Board General Test Area Unconnected USB Connector for Programming & Power 24 MHz Oscillator 7-Segment LED USB µC & MachXO for Programming Support General Test Area Connected ispMACH 4000ZE Power Control & Measurement 2 Non-Debounced Buttons 8-Bit Input Switch and LED Bank Additional Resources Additional resources for this board can be downloaded from the Lattice website at www.latticesemi.com/boards. Navigate to the appropriate evaluation board to find updated documentation, software, sample designs, demos and more. We will continue to add resources to this web page. If you wish to be notified when additional resources are available, click the “Subscribe to Page Update” icon at the top-right side of the screen. Functional Description ispMACH 4000ZE CPLD At the heart of the board is the ispMACH 4000ZE device in a 144-ball csBGA package. Boards are available with either a ispMACH 4064ZE or ispMACH 4256ZE populated CPLD. Table 1 is a summary of all the I/O locations on the device and their connections. 3 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Table 1. ispMACH 4000ZE I/O Locations and Connections Functional Area 7 Segment Display 8-bit Input Switch 8-bit LED Clock Input Device Programming Non-Debounced Push-Button ispMACH 4064ZE ispMACH 4256ZE Board Connection Function Pin Name Function Pin Name Ball Number Bank Number 7SEG_01 I/O A7 I/O B8 A3 0 7SEG_02 I/O A4 I/O B2 A4 0 7SEG_03 I/O A2 I/O A6 A6 0 7SEG_04 I/O A10 I/O C4 C1 0 7SEG_05 I/O A9 I/O C6 C2 0 7SEG_06 I/O A8 I/O C8 C3 0 7SEG_07 I/O A11 I/O C2 D1 0 7SEG_08 I/O A14 I/O D4 D4 0 7SEG_09 I/O D2 I/O P6 A8 1 7SEG_10 I/O D4 I/O O0 A10 1 7SEG_11 I/O D8 I/O N8 C12 1 7SEG_12 I/O D6 I/O O4 B9 1 7SEG_13 I/O D3 I/O P8 C8 1 7SEG_14 I/O D5 I/O O2 C9 1 7SEG_15 I/O D7 I/O O6 D9 1 SW1 I/O B9 I/O F6 J2 0 SW2 I/O A6 I/O B6 C5 0 SW3 I/O B8 I/O F8 K1 0 SW4 Input Only I I/O F10 K2 0 SW5 I/O A5 I/O B4 B4 0 SW6 I/O B3 I/O H8 K5 0 SW7 I/O B1 I/O H4 M5 0 SW8 I/O D13 I/O M4 E11 1 LED1 I/O C1 I/O I4 M7 1 LED2 I/O C2 I/O I6 L7 1 LED3 I/O D15 I/O M0 F12 1 LED4 I/O D14 I/O M2 F11 1 LED5 I/O D12 I/O M6 E12 1 LED6 I/O C5 I/O J4 L9 1 LED7 I/O C6 I/O J6 K8 1 LED8 I/O C7 I/O J8 M10 1 CPLD_CLK CLK0/I CLK0/I CLK0/I CLK0/I A7 0 JTAG - JP2 TDI TDI TDI TDI A1 - JTAG - JP2 TDO TDO TDO TDO B11 - JTAG - JP2 TCK TCK TCK TCK L2 - JTAG - JP2 TMS TMS TMS TMS M12 - Button 1 I/O B11 I/O F2 J1 0 Button 2 I/O B10 I/O F4 J3 0 4 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Table 1. ispMACH 4000ZE I/O Locations and Connections (Continued) Functional Area Test Points ispMACH 4064ZE ispMACH 4256ZE Board Connection Function Pin Name Function Pin Name Ball Number Bank Number TP01 Not Connected - I/O C12 B2 0 TP02 Not Connected - I/O C10 B1 0 TP03 Not Connected - I/O D14 D2 0 TP04 Not Connected - I/O D12 D3 0 TP05 Not Connected - I/O D10 E1 0 TP06 I/O A12 I/O D8 E2 0 TP07 I/O A13 I/O D6 F2 0 TP08 I/O A15 I/O D2 F1 0 TP09 Input Only I I/O D0 F3 0 TP10 I/O B15 I/O E0 G1 0 TP11 I/O B14 I/O E2 E3 0 TP12 I/O B13 I/O E4 G2 0 TP13 I/O B12 I/O E6 G3 0 TP14 Not Connected - E8 E8 H1 0 TP15 Not Connected - E10 E10 H3 0 TP16 Not Connected - E12 E12 H2 0 TP17 Not Connected - I/O F12 L1 0 TP18 Not Connected - I/O G14 M1 0 TP19 Not Connected - I/O G12 K3 0 TP20 Not Connected - I/O G10 M2 0 TP21 Input Only I I/O G8 L3 0 TP22 I/O B7 I/O G6 J4 0 TP23 I/O B6 I/O G4 K4 0 TP24 I/O B5 I/O G2 M3 0 TP25 I/O B4 I/O G0 L4 0 TP26 Not Connected - I/O H12 M4 0 TP27 Not Connected - H10 H10 L5 0 TP28 CLK1/I CLK1/I CLK1/I CLK1/I L6 0 TP29 A0/GOE0 A0/GOE0 A2/GOE0 A2/GOE0 D6 0 TP30 I/O A1 I/O A4 B6 0 TP31 I/O A3 I/O A8 C6 0 TP32 Not Connected - I/O A10 B5 0 TP33 Not Connected - I/O A12 A5 0 TP34 Not Connected - I/O B10 C4 0 TP35 Not Connected - I/O B12 B3 0 TP36 Not Connected - I/O B14 A2 0 TP37 CLK2/I CLK2/I CLK2/I CLK2/I M6 1 TP38 Not Connected - I/O I10 L8 1 TP39 Not Connected - I/O I12 M8 1 TP40 I/O C4 I/O J2 M9 1 TP41 Not Connected - I/O J10 L10 1 TP42 Not Connected - I/O J12 K9 1 TP43 Not Connected - I/O J14 M11 1 5 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Table 1. ispMACH 4000ZE I/O Locations and Connections (Continued) Functional Area Test Points (Cont.) Unconnected Pins ispMACH 4064ZE ispMACH 4256ZE Board Connection Function Pin Name Function Pin Name Ball Number Bank Number TP44 Not Connected - I/O K12 L12 1 TP45 Not Connected - I/O K10 L11 1 TP46 I/O C8 I/O K8 K10 1 TP47 I/O C9 I/O K6 K12 1 TP48 I/O C10 I/O K4 J10 1 TP49 I/O C11 I/O K2 K11 1 TP50 Not Connected - I/O L14 J12 1 TP51 Not Connected - I/O L12 J11 1 TP52 Not Connected - I/O L10 H10 1 TP53 I/O C12 I/O L8 H12 1 TP54 I/O C13 I/O L6 G11 1 TP55 I/O C14 I/O L4 H11 1 TP56 I/O C15 I/O L2 G12 1 TP57 Input Only I I/O L0 G10 1 TP58 Not Connected - I/O M8 D10 1 TP59 Not Connected - I/O M12 D12 1 TP60 Not Connected - I/O M10 F10 1 TP61 I/O D11 I/O N2 E10 1 TP62 I/O D10 I/O N4 D11 1 TP63 I/O D9 I/O N6 E9 1 TP64 Input Only I I/O O8 A11 1 TP65 Input Only I I/O N10 C11 1 TP66 Not Connected - I/O N12 B12 1 TP67 Not Connected - I/O O14 A12 1 TP68 Not Connected - I/O O12 C10 1 TP69 Not Connected - I/O O10 B10 1 TP70 Not Connected - I/O P12 A9 1 TP71 Not Connected - I/O P10 B8 1 TP72 D0/GOE1 D0/GOE1 P2/GOE1 P2/GOE1 B7 1 TP73 CLK3/I CLK3/I CLK3/I CLK3/I C7 1 Not Connected I/O D1 I/O P4 D7 1 Not Connected I/O B2 I/O H6 J6 0 Not Connected I/O C3 I/O I8 J7 1 Not Connected I/O B0 I/O H2 K6 0 Not Connected I/O C0 I/O I2 K7 1 2 Buttons (Non-Debounced) Two non-debounced buttons are provided at SW1 and SW2. These are inputs to the ispMACH 4000ZE, on ball locations J1 and J3 respectively. When the buttons are in the default (unpressed) state, they supply a logic 1 to the ispMACH 4000ZE device. When depressed, they provide a logical 0. 6 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor 8-Bit DIP Switch An 8-bit input DIP switch is provided for convenient user input at location SW3. Refer to Table 1 for the connection listing. When the switches are in the down position (switched toward the bottom of the board), they provide a logical 0 input to the ispMACH 4000ZE. When switched in the up position, they provide a logical 1. Please note that the “ON” label on the silkscreen on the PCB may not correspond with the “ON” arrow label on the component itself. Naturally, the definition of “ON” may depend on the application. 8 LEDs 8 LEDs are provided near the bottom of the board for output indication. Refer to Table 1 for the connection listing. LEDs are lit when a logical 0 is applied. General Test Area - Connected At the left of the board, a general test area is provided. These test points are connected to the ispMACH 4000ZE device at the ball locations indicated on the board silkscreen. Pull-up resistors can be populated on the top of the board, and pull-down resistors can be populated on the bottom of the board. Note that not all of the test points are connected to the ispMACH 4000ZE device. For the smaller ispMACH 4000ZE device, some pins are no-connects. See Table 1 for a summary of these connections. General Prototype Area - Unconnected At the top of the board, a generic prototype area is provided. These are throughholes unconnected to the device. VCC and GND pin areas are also provided for convenience. The VCC areas are connected to 3.3V. 7-Segment LCD Display in 188 Configuration The 7-segment LCD display is connected as indicated in Figure 2. Connections to the display are as indicated in Figure 2, board silkscreen, and Table 1. Application of a logical 0 at 0V will cause the corresponding segment of the display to be illuminated in black. A bank of jumpers at J1 is provided to completely remove the 7-segment display from the board circuit. This can be useful for obtaining accurate power measurements of the ispMACH 4000ZE device. Additionally, these jumper locations provide generic access to the ispMACH 4000ZE I/O. Figure 2. 7-Segment LCD Display 24 MHz Oscillator and Clocking The 24 MHz oscillator near the top of the board is required for operation of the USB interface. However, it is also possible to use this oscillator as a clock input for the ispMACH 4000ZE. It is connected to ball location A7 as indicated in Table 1. The ispMACH 4000ZE also features a user-programmable internal oscillator. For more details on this feature, see the ispMACH 4000ZE Family Data Sheet. The ispMACH 4000ZE device can also be driven by an external clock source provided by the user. 7 ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Programming Programming for the ispMACH 4000ZE device is controlled using the ispVM® System software, available for download from the Lattice website at www.latticesemi.com/ispvm. Refer to the ispVM System software for help regarding operation of this software. The ispMACH 4000ZE Evaluation Board is equipped with a built-in USB-based programming circuit. This consists of a USB microcontroller, a MachXO programmable device, and a USB connector. The MachXO is pre-programmed to act as the interface between the USB microcontroller and ispMACH 4000ZE device. When the board is connected to a PC via the inlcuded USB cable, it is recognized by the ispVM System software as a “USB Download Cable”. The ispMACH 4000ZE can then be scanned and programmed using the ispVM System software. Alternatively, the ispMACH 4000ZE device can be programmed with a Lattice ispDOWNLOAD® Cable (available separately), via the JTAG port at JP1. Refer to the board silkscreen for the correct connections for the ispDOWNLOAD cable. Remember that the board is powered via the USB connection, so even if you are programming the ispMACH 4000ZE via an ispDOWNLOAD Cable, the USB plug must be connected. Note: If you are programming via an ispDOWNLOAD Cable, a jumper must be applied at J3 to disable the MachXO device and prevent a programming conflict situation. For more information on the ispDOWNLOAD Cable, see the Lattice website at www.latticesemi.com/hardware. The MachXO device can also be programmed via JTAG port JP2. However, it is not recommended to reprogram this device, as you will risk disabling the USB programming capability. JP2 is primarily used during manufacturing and initial setup of the board. Power and Power Measurement The board is powered via a 5V USB connection. On-board regulators are included on the board to provide 1.8V and 3.3V required by the components on the board. See Figure 3 for a block diagram of the default jumper settings and locations in relation to the ispMACH 4000ZE, on-board regulators and other components. Jumpers J8 and J7 are positioned in-series with the power to the ispMACH 4000ZE. To measure the power consumed by the ispMACH 4000ZE I/O, remove J8 and J7 and apply an ammeter across either of them. This is a 3.3V rail, so multiply current measured by 3.3V to get wattage. To measure power consumed by the ispMACH 4000ZE device core, remove J5 and apply an ammeter across it. This is a 1.8V rail, so multiply current by 1.8V to get wattage. See Figure 4 for a diagram of these measurements. For more the most accurate Icc power measurements, remove jumpers J6 and J9 to disable everything on board except the ispMACH 4000ZE device and the I/Os. Figure 3. Default Jumper Settings and Locations J8 5V ispMACH 4000ZE VCCIO J6 All Other Devices 3.3V J7 J9 J5 VCCIO 1.8V VCC 8 ispMACH 4000ZE ispMACH 4000ZE Evaluation Board User’s Guide Lattice Semiconductor Figure 4. Power Measurement ispMACH 4000ZE I/O Current 5V 3.3V ispMACH 4000ZE VCCIO All Other Devices A VCCIO A 1.8V ispMACH 4000ZE VCC ispMACH 4000ZE Core Current Ordering Information Ordering Part Number Description ispMACH 4064ZE Evaluation Board LC4064ZE-EVN ispMACH 4256ZE Evaluation Board LC4256ZE-EVN China RoHS Environment-Friendly Use Period (EFUP) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version May 2008 01.0 Initial release. May 2008 01.1 Updated board photo. February 2009 01.2 Updated Power and Power Measurement text section. Change Summary © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 9 10 A B C C12 0.01uF CC0603 + + 5 CSBGA144 Bank 0 A1 B2 B1 C3 C2 C1 D1 D2 D3 E1 E2 F2 D4 F1 F3 G1 E3 G2 G3 H1 H3 H2 J1 J3 J2 K1 K2 L1 L2 M1 K3 M2 L3 J4 K4 M3 L4 M4 L5 K5 J6 M5 K6 L6 A7 D6 B6 A6 C6 B5 A5 A4 B4 C5 A3 C4 B3 A2 C11 0.1uF CC0603 TDI NC / IOB0 / IOC6 NC / IOB1 / IOC5 IOA8 / IOB2 / IOC4 IOA9 / IOB3 / IOC3 IOA10 / IOB4 / IOC2 IOA11 / IOB5 / IOC1 NC / NC / IOD7 NC / NC / IOD6 NC / IOB6 / IOD5 IOA12 / IOB7 / IOD4 IOA13 / IOB8 / IOD3 IOA14 / IOB9 / IOD2 IOA15 / IOB10 / IOD1 DI0 / IOB11 / IOD0 IOB15 / IOC11 / IOE0 IOB14 / IOC10 / IOE1 IOB13 / IOC9 / IOE2 IOB12 / IOC8 / IOE3 NC / IOC7 / IOE4 NC / IOC6 / IOE5 NC / NC / IOE6 IOB11 / IOC5 / IOF1 IOB10 / IOC4 / IOF2 ispMACH4000ZE IOB9 / IOC3 / IOF3 144 csBGA Pin name sequence IOB8 / IOC2 / IOF4 DI1 / IOC1 / IOF5 (64,128,256) NC / IOC0 / IOF6 TCK NC / NC / IOG7 NC / NC / IOG6 NC / IOD11 / IOG5 DI2 / IOD10 / IOG4 IOB7 / IOD9 / IOG3 IOB6 / IOD8 / IOG2 IOB5 / IOD7 / IOG1 IOB4 / IOD6 / IOG0 NC / IOD5 / IOH6 NC / IOD4 / IOH5 IOB3 / IOD3 / IOH4 IOB2 / IOD2 / IOH3 IOB1 / IOD1 / IOH2 IOB0 / IOD0 / IOH1 CLK1*I CLK0*I IOA0*OE0 / IOA0*OE0 / IOA1*OE0 IOA1 / IOA1 / IOA2 IOA2 / IOA2 / IOA3 IOA3 / IOA3 / IOA4 NC / IOA4 / IOA5 NC / IOA5 / IOA6 IOA4 / IOA6 / IOB1 IOA5 / IOA7 / IOB2 IOA6 / IOA8 / IOB3 IOA7 / IOA9 / IOB4 NC / IOA10 / IOB5 NC / IOA11 / IOB6 NC / NC / IOB7 U2A VCC33 E4 F4 G4 J5 D5 NC / VCCIO0 / VCCIO0 VCCIO0 NC / VCCIO0 / VCCIO0 VCCIO0 VCCIO0 TP17 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP3 TP4 TP5 TP6 TP7 7SEG_2 SW5 SW2 7SEG_1 7SEG_3 CPLD_CLK SW7 SW6 TP34 TP35 TP36 TP31 TP32 TP33 TP29 TP30 TP28 CPLD_TCK TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 Button1 Button2 SW1 SW3 SW4 7SEG_8 7SEG_6 7SEG_5 7SEG_4 7SEG_7 CPLD_TDI TP1 TP2 4 C8 0.01uF CC0603 + + CSBGA144 Bank 1 M6 K7 M7 L7 J7 L8 M8 M9 L9 K8 M10 L10 K9 M11 M12 L12 L11 K10 K12 J10 K11 J12 J11 H10 H12 G11 H11 G12 G10 F12 F11 E11 E12 D10 F10 D12 E10 D11 E9 C12 C11 B12 B11 A12 C10 B10 A11 D9 B9 C9 A10 A9 B8 C8 A8 D7 B7 C7 C7 0.1uF CC0603 CLK2*I IOC0 / IOE0 / IOI1 IOC1 / IOE1 / IOI2 IOC2 / IOE2 / IOI3 IOC3 / IOE3 / IOI4 NC / IOE4 / IOI5 NC / IOE5 / IOI6 IOC4 / IOE6 / IOJ1 IOC5 / IOE7 / IOJ2 IOC6 / IOE8 / IOJ3 IOC7 / IOE9 / IOJ4 NC / IOE10 / IOJ5 NC / IOE11 / IOJ6 NC / NC / IOJ7 TMS NC / IOF0 / IOK6 NC / IOF1 / IOK5 IOC8 / IOF2 / IOK4 IOC9 / IOF3 / IOK3 IOC10 / IOF4 / IOK2 IOC11 / IOF5 / IOK1 NC / NC / IOL7 NC / NC / IOL6 NC / IOF6 / IOL5 ispMACH4000ZE IOC12 / IOF7 / IOL4 144 csBGA Pin name sequence IOC13 / IOF8 / IOL3 IOC14 / IOF9 / IOL2 (64,128,256) IOC15 / IOF10 / IOL1 DI3 / IOF11 / IOL0 IOD15 / IOG11 / IOM0 IOD14 / IOG10 / IOM1 IOD13 / IOG9 / IOM2 IOD12 / IOG8 / IOM3 NC / IOG7 / IOM4 NC / IOG6 / IOM5 NC / NC / IOM6 IOD11 / IOG5 / ION1 IOD10 / IOG4 / ION2 IOD9 / IOG3 / ION3 IOD8 / IOG2 / ION4 DI4 / IOG1 / ION5 NC / IOG0 / ION6 TDO NC / NC / IOO7 NC / NC / IOO6 NC / IOH11 / IOO5 DI5 / IOH10 / IOO4 IOD7 / IOH9 / IOO3 IOD6 / IOH8 / IOO2 IOD5 / IOH7 / IOO1 IOD4 / IOH6 / IOO0 NC / IOH5 / IOP6 NC / IOH4 / IOP5 IOD3 / IOH3 / IOP4 IOD2 / IOH2 / IOP3 IOD1 / IOH1 / IOP2 IOD0*OE1 / IOH0*OE1 / IOP1*OE1 CLK3*I U2B VCC33 J8 H9 G9 F9 D8 VCCIO1 NC / VCCIO1 / VCCIO1 VCCIO1 NC / VCCIO1 / VCCIO1 VCCIO1 D 4 3 7SEG_13 7SEG_9 7SEG_15 7SEG_12 7SEG_14 7SEG_10 CPLD_TDO 7SEG_11 LED3 LED4 SW8 LED5 CPLD_TMS LED6 LED7 LED8 LED1 LED2 3 TP72 TP73 TP70 TP71 TP67 TP68 TP69 TP64 TP65 TP66 TP58 TP60 TP59 TP61 TP62 TP63 TP44 TP45 TP46 TP47 TP48 TP49 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP41 TP42 TP43 TP38 TP39 TP40 TP37 U2C VCC18 C9 0.01uF CC0603 H5 H8 E8 E5 ispMACH4000ZE 144 csBGA Pin name sequence (64,128,256) VCC VCC VCC VCC + GND GNDIO0 GNDIO0 GND GNDIO0 NC / GNDIO1 / GNDIO1 GNDIO1 GND GNDIO1 GNDIO1 GND GNDIO1 NC / GNDIO0 / GNDIO0 GNDIO0 Power / GND F6 G5 H4 G6 H6 H7 J9 G7 G8 F8 F7 E7 E6 F5 5 2 + 2 CSBGA144 C10 0.1uF CC0603 Monday, April 21, 2008 Date: ispMACH4000ZE Evaluation Board Document Number <Doc> Size B Title Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro, OR 97124 CPLD_CLK CPLD_TDO CPLD_TDI CPLD_TMS CPLD_TCK Button[1..2] 7SEG[1..15] SW[1..8] LED[1..8] TP[1..73] 1 Sheet 1 1 TP[1..73] of 4 CPLD_CLK CPLD_TDO CPLD_TDI CPLD_TMS CPLD_TCK Button[1..2] 7SEG[1..15] SW[1..8] LED[1..8] Re v B A B C D Lattice Semiconductor ispMACH 4000ZE Evaluation Board User’s Guide Appendix A. Schematic Figure 5. ispMACH 4000ZE 11 A B C D 5 VCC33_LDO LED LED LED LED LED LED LED LED A' R166 R164 R162 R160 R158 R156 R154 R153 B' 470 470 470 470 470 470 470 470 Button2 LED_GREEN D8 LED_GREEN D7 LED_GREEN D6 LED_GREEN D5 LED_GREEN D4 LED_GREEN D3 LED_GREEN D2 LED_GREEN D1 A' 4 SW2 R75 A SW1 VCC33_LDO R74 A 10K B VCC33_LDO LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 B' 10K B Button1 SW PUSHBUTTON Panasonic EVQ-PAD04M 4 7SEG_1 7SEG_2 7SEG_3 7SEG_4 7SEG_5 7SEG_6 7SEG_7 7SEG_8 7SEG_9 7SEG_10 7SEG_11 7SEG_12 7SEG_13 7SEG_14 7SEG_15 ON 3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 3 Shunts J1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 208-8 Dip Switch 2 SW7 SW6 SW5 SW3 SW2 SW1 8 7 6 5 4 3 2 1 3A 3B 3C 3D 3E 3G 3F 1BC 2 2C 2B 2A 2F 2G 2E 2D COM 9 10 11 12 13 14 15 16 LCD-S2X1C50TR (2.5 7-Segment LCD) LED[1..8] Button[1..2] 7SEG[1..15] SW[1..8] Document Number <Doc> Monday, April 21, 2008 Date: ispMACH4000ZE Evaluation Board Size B Title Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro, OR 97124 VCC50 2.5 Digit 7 Segment LCD SW8 SW4 R167 R165 R163 R161 R159 R157 R155 R152 10K 10K 10K 10K 10K 10K 10K 10K VCC33_LDO 8 Bit Switch 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 5 1 Sheet 1 2 of 4 Button[1..2] Rev B 7SEG[1..15] SW[1..8] LED[1..8] A B C D Lattice Semiconductor ispMACH 4000ZE Evaluation Board User’s Guide Figure 6. User I/O A B C TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 TP42 TP43 TP44 TP45 TP46 TP47 TP48 TP49 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP58 TP59 TP60 TP61 TP62 TP63 TP64 4 5 TP65 TP66 TP67 TP68 TP69 TP70 TP71 TP72 TP73 IO49 IO23 IO7 IO50 IO64 IO33 IO65 IO34 IO66 IO70 IO67 IO68 IO36 IO35 IO69 IO73 IO37 IO39 IO38 IO42 IO40 IO72 IO71 IO41 IO43 IO12 IO44 IO11 IO45 IO2 IO13 IO1 VCC33_LDO 4 GND_49 GND_23 GND_7 GND_50 GND_64 GND_33 GND_65 GND_34 GND_66 GND_70 GND_67 GND_68 GND_36 GND_35 GND_69 GND_73 GND_37 GND_39 GND_38 GND_42 GND_40 GND_72 GND_71 GND_41 GND_43 GND_12 GND_44 GND_11 GND_45 GND_2 GND_13 GND_1 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 VCC33_LDO General Purpose I/O test points 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k D 5 3 VCC33_LDO R49 R23 R7 R50 R64 R33 R65 R34 R66 R70 R67 R68 R36 R35 R69 R73 R37 R39 R38 R42 R40 R72 R71 R41 R43 R12 R44 R11 R45 R2 R13 R1 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k R3 R46 R14 R4 R47 R15 R5 R48 R16 10k 10k 10k 10k 10k 10k 10k 10k 10k R127 R101 R85 R128 R142 R111 R143 R112 R144 R148 R145 R146 R114 R113 R147 R151 R115 R117 R116 R120 R118 R150 R149 R119 R121 R90 R122 R89 R123 R80 R91 R79 R18 R8 R51 R56 R9 R19 R52 R20 R58 R53 R25 R10 R27 R55 R61 R21 R57 R26 R24 R28 R59 R30 R60 R29 R62 R31 R63 R32 R22 R6 R54 R17 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k R96 R86 R129 R134 R87 R97 R130 R98 R136 R131 R103 R88 R105 R133 R139 R99 R135 R104 R102 R106 R137 R108 R138 R107 R140 R109 R141 R110 R100 R84 R132 R95 IO3 IO46 IO14 IO4 IO47 IO15 IO5 IO48 IO16 GND_3 GND_46 GND_14 GND_4 GND_47 GND_15 GND_5 GND_48 GND_16 3 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 12 10k R81 10k R124 10k R92 10k R82 10k R125 10k R93 10k R83 10k R126 10k R94 IO18 IO8 IO51 IO56 IO9 IO19 IO52 IO20 IO58 IO53 IO25 IO10 IO27 IO55 IO61 IO21 IO57 IO26 IO24 IO28 IO59 IO30 IO60 IO29 IO62 IO31 IO63 IO32 IO22 IO6 IO54 IO17 GND_18 GND_8 GND_51 GND_56 GND_9 GND_19 GND_52 GND_20 GND_58 GND_53 GND_25 GND_10 GND_27 GND_55 GND_61 GND_21 GND_57 GND_26 GND_24 GND_28 GND_59 GND_30 GND_60 GND_29 GND_62 GND_31 GND_63 GND_32 GND_22 GND_6 GND_54 GND_17 2 2 AB58 AB3 AB7 AB11 AB55 AB59 AB4 AB8 AB12 AB56 AB54 AB1 AB5 AB9 AB53 AB57 AB10 AB2 AB60 AB6 BB1 BB2 BB3 BB4 BB5 BB6 BB7 BB8 BB9 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 CB16 CB17 CB18 CB19 CB20 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 Document Number <Doc> Monday, April 21, 2008 Date: ispMACH4000ZE Evaluation Board Size B Title Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro, OR 97124 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB28 AB30 AB32 AB34 AB36 AB38 AB40 AB42 AB44 AB46 AB48 AB50 AB52 Proto Area DB52 VCC33_LDO DB50 DB51 DB49 Mounting Feet TP[1..73] 1 Sheet 1 3 AB23 AB51 AB25 AB27 AB21 AB19 AB13 AB17 AB15 AB29 AB49 AB45 AB47 AB43 AB41 AB37 AB39 AB35 AB31 AB33 of TP[1..73] 4 Rev B A B C D Lattice Semiconductor ispMACH 4000ZE Evaluation Board User’s Guide Figure 7. Test Points and Prototype Area A B C 2 J3 1 5 XO_TCK XO_TMS GNDIO1 VCCIO1 PL9A PL8B PL8A PL7D PL7C PL7B PL7A PL6B/TSALL PL6A PL5D/GSR_N PL5C GNDIO1 PL5B VCCIO3 PL5A PL4B PL4A PL3D PL3C PL3B PL3A PL2B PL2A XO_TDO VCC33_XO 1 2 3 4 5 6 7 8 JP2 XO_TCK XO_TMS XO_TDI R77 4.7k VCC33_LDO XO_TDO XO_TDI MachXO JTAG VCC33_LDO HEADER1X8 USB_PD0 USB_PD1 J4 VCC33_LDO VCC33_XO 1 HEADER1x2 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 + C3 1uF CC0603 DI CR0603 PR9B PR9A PR8B PR8A PR7D PR7C PR7B PR7A PR6B VCCIO0 PR6A GNDIO0 PR5D PR5C PR5B PR5A PR4B PR4A PR3D PR3C PR3B PR3A PR2B VCCIO0 GNDIO0 1 2 3 4 5 6 7 8 JP1 4 CPLD_TCK CPLD_TMS R76 4.7k VCC33_LDO CPLD_TDO CPLD_TDI + C13 0.01uF CC0603 VCC33_XO C4 1uF CC0603 + + C16 0.1uF CC0603 VCC33_LDO VCC33_XO USB_SCL USB_SDA USB_WAKEUP USB_RESET USB_PD3 USB_PD2 LCMXO256-T100/TN100 U4 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 CPLD JTAG HEADER1X8 USB_PB3 VCC33_LDO VCC33_XO USB_PB0 MachXO CPLD_TDI PT2A PT2B PT2C PT2D PT2E PT2F PT3A GNDIO0 VCCIO0 PT3B VCC PT3C VCCAUX PT3D PCLKT0_0/PT4A PCLKT0_1/PT4B GND PT4C PT4D PT4E PT4F PT5A PT5B PT5C PR2A USB_PB2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 USB_PB5 D CPLD_TDO VCC33_XO CPLD_TCK TMS PL9B TCK PB2A PB2B TDO PB2C TDI PB2D VCC PB3A/PCLKT1_1 PB3B PB3C/PCLKT1_0 PB3D GND VCCIO1 GNDIO1 PB4A PB4B PB4C PB4D PB5A SLEEPN PB5C PB5D 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CPLD_TMS 4 1 2 3 4 VCC OUT 4.7K VCC50 3 + C2 10uF CC0603 VCC33_source + C6 10uF CC0603 VCC50 4 8 5 4 8 5 OUT SENSE NC IN ~SHDN OUT SENSE U5 LT1963_18 NC IN ~SHDN 4 3 USBUSB+ U6 LT1963_33 C14 0.01uF CC0603 + 1 2 1 2 WAKEUP RESET# RESERVED DMINUS DPLUS XTALOUT XTALIN CTL2/FLAGC CTL1/FLAGB CTL0/FLAGA RDY0/SLRD RDY1/SLWR + 1 1 C1 1uF CC0603 + 2 VCC18_source 1 1.8 Power C5 1uF CC0603 VCC33_source JUMPER J5 JUMPER J7 JUMPER J8 VCC18 VCC33 1 1 47 46 45 44 43 42 41 40 3 2 1 56 55 54 53 52 32 31 30 29 28 27 26 25 JUMPER J9 2 2 VCC33_LDO TP4 USB_PB0 JUMPER J6 TP3 TP1 TP2 USB_PB5 TP8 TP7 TP6 TP5 USB_PB3 USB_PB2 USB_PD3 USB_PD2 USB_PD1 USB_PD0 CPLD_CLK CPLD_TDO CPLD_TDI CPLD_TMS CPLD_TCK Document Number <Doc> Monday, April 21, 2008 Size B Date: ispMACH4000ZE Evaluation Board Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro, OR 97124 Title 2 2 2 FX2 PA7/FLAGD/SLCS# PA6/PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/WU2 PA2/SLOE PA1/INT1# PA0/INT0# PD7/FD15 PD6/FD14 PD5/FD13 PD4/FD12 PD3/FD11 PD2/FD10 PD1/FD9 PD0/FD8 PB7/FD7 PB6/FD6 PB5/FD5 PB4/FD4 PB3/FD3 PB2/FD2 PB1/FD1 PB0/FD0 IFCLK/T0OUT CLKOUT/T1OUT SCL SDA AVCC_3.3V Ferrite_Bead L1 3.3V Power 38 37 36 8 9 22 23 USB_SCL USB_SDA 16 15 11 12 20 5 U3 2 VCC33_LDO C15 0.1uF CC0603 51 49 21 + USB_WAKEUP USB_RESET 33 CPLD_CLK VCC33_LDO CMX-309FBC EN GND Y1 USB_CONN_B VCC DD+ GND J2 1 2 R78 USB / PHY USB connector from XO standard board 3 GND1 3 VCC33_LDO GND3 5 GND1 3 GND2 6 GND2 1Kohms 470 7 GND3 6 R169 D10 LED_RED R168 D9 13 7 6 18 24 34 39 50 10 14 VCC VCC VCC VCC VCC VCC AVCC AVCC USB_PHY GND GND GND GND GND GND AGND AGND 4 7 19 33 35 48 13 17 24MHz LED_RED 1 Sheet 1 4 of CPLD_TCK 4 Rev B CPLD_CLK CPLD_TDO CPLD_TDI CPLD_TMS A B C D Lattice Semiconductor ispMACH 4000ZE Evaluation Board User’s Guide Figure 8. Programming and Power