4-Bit Micro-controller With LCD Driver
Features
y Low power and low voltage operation
y Powerful instruction set (150 instructions)
y Memory capacity
Ϋʳ Instruction ROM capacity 4096 x 16 bits
Ϋʳ Index ROM capacity 256 x 8 bits
Ϋʳ Internal RAM capacity 384 or 256 x 4 bits
y Input/Output ports of up to 20 pins
y 8-level subroutine nesting
y Built-in LCD driver, 8 x 42 = 336 segments
y Built-in EL driver, frequency or melody generator
y Built-in Resistance-to-Frequency Converter
y Built-in 2-channel 6/8-bit PWM output
y Built-in key strobe function
(Shared with segment pin)
y Built-in voltage doubler, halver, tripler
quadrupler charge pump circuit
y Two 6-bit programmable timers with
programmable clock source
y Watchdog timer
y 4 external & 3 internal interrupt resources
Ϋʳ External: INT, RFC, IOA/IOC/S port,
keystrobe
Ϋʳ Internal: TM1, TM2, Predivider
y Dual clock operation
y HALT and STOP function
General Description
The APU429 is an embedded high performance
4-bit micro-computer with an on-chip LCD driver. It
contains all the necessary functions in a single chip:
4-bit parallel processing ALU, ROM, RAM, I/O ports,
timer, clock generator, dual clock, RFC, EL-light,
LCD driver, look-up table, watchdog timer and
keyboard scanning. The instruction set includes not
only 4-bit operation and manipulation instructions
but also various conditional branch instructions and
LCD driver data transfer instructions which are
powerful and easy to use.
The HALT function stops any internal operations
other than the oscillator, divider and LCD driver in
order to minimize the power dissipation.
The STOP function stops all the clocks in the chip.
Block Diagram
S E G 35 38
IO A P o rt
/R F C
S E G 31 34
S E G 39 42
S E G 27 30
IO B P o rt
/E L , B Z
IO C P o rt
/K E Y IN
IO D P o rt
/P W M
COM 1 8
S E G 1 S E G 26
VDD1 4
L C D D rive r
S egm entP LA
4 -B it D a ta B u s
CUP 1
CUP 2
CUP 3
P re -D ivid e r
T a b le R O M
256 x 8
SRAM
128 x 4
2 x 6 B its
P re se t T im e r
8 -L e ve ls S ta ck
In stru ctio n
D e co d e r
C o n tro l
C ircu it
1 2 -B it P ro g ra m
C o u n te r
M a sk R O M
4096 x 16
RESET
C F IN
C FO U T
X T IN
X TO U T
W a tch d o g
T im e r
O scilla to r
Preliminary
In d e x S R A M
256 x 4
A LU
IN T
F re q u e n cy
G e n e ra to r
S1 S4
1
Ver. 0.0
APU429
Pad Assignment
Chip size : 2620 x 2050 Pm
Pad size : 100 x 100 Pm
Pad window : 90 x 90 Pm
Pad pitch : min. 120 Pm
<
70
1
10
20
APU429
60
30
40
50
;
Note: The substrate of die must connect to GND.
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
Pad Name
CFIN
CFOUT
XTIN
XTOUT
BAK
TESTA
RESET
INT
S1
S2
S3
Preliminary
X
1971.50
1785.25
1665.25
1545.25
1425.25
1305.25
1185.25
1065.25
945.25
825.25
705.25
Y
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
2544.50
Pad No.
36
37
38
39
40
41
42
43
44
45
46
2
Pad Name
SEG13/KO3
SEG14/KO4
SEG15/KO5
SEG16/KO6
SEG17/KO7
SEG18/KO8
SEG19/KO9
SEG20/KO10
SEG21/KO11
SEG22/KO12
SEG23/KO13
X
75.25
225.25
345.25
465.25
585.25
705.25
825.25
945.25
1065.25
1185.25
1305.25
Y
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
Ver. 0.0
Pad No.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pad Name
S4
VDD1
VDD2
VDD3
VDD4
CUP1
CUP2
CUP3
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11/KO1
SEG12/KO2
X
585.25
465.25
345.25
225.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
Y
2544.50
2544.50
2544.50
2544.50
2544.50
2394.50
2274.50
2154.50
2034.50
1914.50
1785.25
1665.25
1545.25
1425.25
1305.25
1185.25
1065.25
945.25
825.25
705.25
585.25
465.25
345.25
225.25
Pad No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Pad Name
SEG24/KO14
SEG25/KO15
SEG26/KO16
SEG27/IOD1
SEG28/IOD2
SEH29/IOD3/PWM1
SEH30/IOD4/PWM2
SEG31/IOB1/ELC
SEG32/IOB2/ELP
SEG33/IOB3/BZB
SEG34/IOB4/BZ
SEG35/IOA1/CX
SEG36/IOA2/RR
SEG37/IOA3/RT
SEG38/IOA4/RH
SEG39/IOC1/KI1
SEG40/IOC2/KI2
SEG41/IOC3/KI3
SEG42/IOC4/KI4
COM5
COM6
COM7
COM8
GND
X
1425.25
1545.25
1665.25
1785.25
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
1971.50
Y
75.25
75.25
75.25
75.25
75.25
225.25
345.25
465.25
585.25
705.25
825.25
945.25
1065.25
1185.25
1305.25
1425.25
1545.25
1665.25
1785.25
1905.25
2034.50
2154.50
2274.50
2394.50
Chip size : 2620 x 2050 Pm
Pad Descriptions
Pad Name
I/O
Positive back-up voltage.
In Li mode, connects a 0.1P capacitance to GND.
LCD drive voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.
BAK
VDD1
VDD2
VDD3
VDD4
RESET
I
INT
I
TESTA
CUP1
CUP2
CUP3
I
Preliminary
Description
O
Input pin for LSI reset signal.
With Internal pull-down resistor.
Input pin for external INT request signal.
Falling edge or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or floatting to be selected by mask option.
TESTA I Test signal input pin, internal pull-down resistor.
Test signal input pin.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3, 4 pins.
Connects the CUP1, CUP2 and CUP3 pins with a nonpolarized electronic
capacitor if 1/2, 1/3 or 1/4 bias mode has been selected. In the STATIC mode,
these pins should be open.
3
Ver. 0.0
Pad Name
I/O
XTIN
XTOUT
I
O
CFIN
CFOUT
I
O
COM1~8
SEG1~10
O
O
SEG11~26/KO1~16
O
SEG27~42
O
IOA1~4
I/O
IOB1~4
I/O
IOC1~4
I/O
IOD1~4
I/O
S1~4
I
KI1~4
I
I
O
O
O
O
O
RFC
EL
CC
RR
RT
RH
ELC
ELP
ALM
BZB
BZ
PWM1, 2
GND
Preliminary
O
O
Description
Time based counter frequency (Clock specified. LCD alternating frequency.
Alarm signal frequency.) or system clock oscillation.
32KHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.
System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.
Output pins for supplying voltage to drive the common pins of the LCD panel.
Output pins for LCD panel segment.
Output pins for LCD panel segment.
Key strobe function, share pins as key scan output.
Output pins for LCD panel segment.
Input/Output port A, can use software to define the internal pull-low resistor
and chattering clock in order to reduce input bounce and generate an
interrupt.
This port shares pins with SEG35~38 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.
Input/Output port B.
IOB port shares pins with SEG31~34, and is set by mask option.
This port also shares pins with ELC, ELP, BZB and BZ, and is set by mask
option.
Input/Output port C, can use software to define internal pull-low/low-level hold
resistor and chattering clock in order to reduce input bounce and generate an
interrupt or keyboard scanning function with ELC, ELP, BZB and BZ, and is
set by mask option.
Input/Output port D.
This port shares pins with SEG27~30 and is set by mask option.
IOD3, 4 shares pins with PWM1, 2 and is set by mask option.
Input ports by mask option to internal pull-low/low-level hold resistor and
chattering clock in order to reduce input bounce and generate an interrupt or
HALT or STOP release.
Key scan input, this port shares pins with IOC1~4 and is set by mask option.
1 input pin and 3 output pins for RFC application.
This port shares pins with SEG35~38 and is set by mask option.
This port shares pins with IOA1~4 and is set by mask option.
Output port for EL-light.
This port shares pins with SEG31, 32 and is set by mask option.
This port shares pins with IOB1, 2 and is set by mask option.
Output port for alarm, frequency or melody generator.
This port shares pins with IOB3, 4 and is set by mask option.
6/8-Bit PWM output; set by mask option.
Negative supply voltage.
4
Ver. 0.0
Absolute Maximum Rating
Name
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
Maximum Storage Temperature
Ta = 0 to 70к GND=0V
Symbol
VDD1
VDD2
VDD3
VDD4
VIN
VOUT1
VOUT2
tOPG
Rating
-0.3 ~ +5.5
-0.3 ~ +5.5
-0.3 ~ +8.5
-0.3 ~ +8.5
-0.3 to VDD1/2+0.3
-0.3 to VDD1/2+0.3
-0.3 to VDD3+0.3
0 to +70
Unit
V
V
V
V
V
V
V
к
tSTG
-25 to +125
к
Allowable operating conditions
Name
Input sHs Voltage
Symbol
VDD1
VDD2
VDD3
VDD4
VDDB
VDDB
VDD1
VDD2
VIH1
Input sLs Voltage
VIL1
Supply Voltage
Oscillator Start-up Voltage
Oscillator Sustain Voltage
Supply Voltage
Supply Voltage
Input sHs Voltage
VIH2
Input sLs Voltage
VIL2
Input sHs Voltage
VIH3
Input sLs Voltage
VIL3
Input sHs Voltage
VIH4
Input sLs Voltage
VIL4
Input sHs Voltage
VIH5
Ta = 0 to 70к GND=0V
Condition
Crystal Mode
Crystal Mode
Ag Mode
EXT-V, Li Mode
Ag Battery Mode
Li Battery Mode
OSCIN at Ag Battery Mode
OSCIN at Li Battery Mode
CFIN at Li Battery or EXT-V Mode
Min.
1.2
2.4
2.4
2.4
1.3
1.2
1.2
2.4
VDD1-0.7
Max.
5.25
5.25
8.0
8.0
1.65
5.25
VDD1+0.7
Unit
V
V
V
V
V
V
V
V
V
-0.7
0.7
V
VDD2-0.7
VDD2+0.7
V
-0.7
0.7
V
0.8VDD1
VDD1
V
0
0.2VDD1
V
0.8VDD2
VDD2
V
0
0.2VDD2
V
0.8VDD2
VDD2
V
Input sLs Voltage
VIL5
0
0.2VDD2
V
Input sHs Voltage
VIH6
0.8VDDO
VDDO
V
Input sLs Voltage
VIL6
0
0.2VDDO
V
Operating Freq.
fOPG1
fOPG2
fOPG3
32
32
1000
3580
1000
3580
kHz
kHz
kHz
Preliminary
RC Mode
Crystal Mode
External RC Mode
CF Mode
5
Ver. 0.0
Electrical Characteristics
Input resistance
Name
Symbol
RIIH1
sLs-Level Hold tR (IOC)
IOC/IOA Pull-Down tR
INT Pull-Up tR
INT Pull-Down tR
RES Pull-Down tR
Condition
VI=0.2VDD1, #1
Min.
10
Typ.
40
Max.
100
Unit
k:
RIIH2
VI=0.2VDD2, #2
10
40
100
k:
RIIH3
VI=0.2VDD2, #3
5
20
50
k:
RMSD1
VI=VDD1, #1
200
500
1000
k:
RMSD2
VI=VDD2, #2
200
500
1000
k:
RMSD3
VI=VDD3, #3
100
250
500
k:
RINTU1
VI=VDD1, #1
200
500
1000
k:
RINTU2
VI=VDD2, #2
200
500
1000
k:
RINTU3
VI=VDD3, #3
100
250
500
k:
RINTD1
VI=GND, #1
200
500
1000
k:
RINTD2
VI=GND, #2
200
500
1000
k:
RINTD3
VI=GND, #3
100
250
500
k:
RRES1
VI=GND or VDD1, #1
5
20
50
k:
RRES2
VI=GND or VDD2, #2
5
20
50
k:
RRES3
VI=GND or VDD2, #3
5
20
50
k:
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
DC output characteristics
Name
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sLs Voltage
Symbol
VOH1a
VOH2 a
Condition
For
IOH=-10PA, #1
Min.
0.8
Typ.
0.9
Max.
1.0
Unit
V
IOH=-50PA, #2
1.5
1.8
2.1
V
VOH3 a
IOH=-200PA, #3
2.5
3
3.5
V
VOL1 a
IOL=20PA, #1
0.2
0.3
0.4
V
VOL2 a
IOL=100PA, #2
0.3
0.6
0.9
V
VOL3 a
IOL=400PA, #3
0.5
1
1.5
V
VOH1c
IOH=-200PA, #1
IOH=-1mA, #2
IOH=-3mA, #3
0.8
0.9
1.0
V
1.5
2.5
0.2
1.8
3
0.3
2.1
3.5
0.4
V
V
V
0.3
0.5
0.6
1
0.9
1.5
V
V
VOH2c
VOH3c
VOL1c
VOL2c
VOL3C
SEG1~26
SEG27~42
IOA, B, C, D
IOL=400PA, #1
IOL=2mA, #2
IOL=6mA, #3
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
Preliminary
6
Ver. 0.0
Segment driver output characteristics
Name
Static display mode
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sLs Voltage
Symbol
Condition
For
Min.
Typ.
Max.
Unit
VOH1d
IOH=-1PA, #1
1.0
V
VOH2d
IOH=-1PA, #2
2.2
V
VOH3d
IOH=-1PA, #3
3.8
V
VOL1d
IOL=1PA, #1
SEG-n
0.2
V
IOL=1PA, #2
0.2
V
VOL3d
IOL=1PA, #1
0.2
V
VOH1e
IOH=-10PA, #1
VOH2e
IOH=-10PA, #2
VOH3e
IOH=-10PA, #3
VOL2d
VOL1e
VOL2e
COM-n
1.0
V
2.2
V
3.8
V
IOL=10PA, #1
0.2
V
IOL=10PA, #2
0.2
V
VOL3e
IOL=10PA, #3
0.2
V
VOH12f
1/2 bias display mode
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sMs Voltage
Output sLs Voltage
IOH=-1PA, #1, #2
2.2
V
VOH3f
IOH=-1PA, #3
3.8
V
VOL12f
IOL=1PA, #1, #2
VOL3f
IOL=1PA, #3
SEG-n
VOH12g
IOH=-10PA, #1, #2
VOH3g
0.2
V
0.2
V
2.2
V
IOH=-10PA, #3
3.8
VOM12g
IOI/H=r10PA, #1, #2
1.0
1.4
V
VOM3g
IOI/H=r10PA, #3
1.8
2.2
V
VOL12g
IOL=10PA, #1, #2
0.2
V
VOL3g
IOL=10PA, #3
0.2
V
VOH12i
IOH=-1PA, #1, #2
3.4
V
VOH3i
IOH=-1PA, #3
5.8
V
VOM12i
IOI/H=r10PA, #1, #2
1.0
1.4
V
VOM13i
IOI/H=r10PA, #3
1.8
2.2
V
VOM22i
IOI/H=r10PA, #1, #2
2.2
2.6
V
3.8
4.2
V
COM-n
V
1/3 bias display mode
Output sHs Voltage
Output sM1s Voltage
Output sM2s Voltage
Output sLs Voltage
Output sHs Voltage
Output sM1s Voltage
Output sM2s Voltage
Output sLs Voltage
SEG-n
VOM23i
IOI/H=r10PA, #13
VOL12i
IOL=1PA, #1, #2
0.2
V
VOL3i
IOL=1PA, #3
0.2
V
VOH12j
IOH=-10PA, #1, #2
VOH3j
3.4
V
IOH=-10PA, #3
5.8
VOM12j
IOI/H=r10PA, #1, #2
1.0
1.4
V
VOM13j
IOI/H=r10PA, #3
1.8
2.2
V
VOM22j
IOI/H=r10PA, #1, #2
2.2
2.6
V
VOM23j
IOI/H=r10PA, #3
3.8
4.2
V
VOL12j
IOL=10PA, #1, #2
0.2
V
IOL=10PA, #3
0.2
V
VOL3j
COM-n
V
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
Preliminary
7
Ver. 0.0
Functional Description
SRAM
The 256 x 4 bits index SRAM and 128 x 4 bits data SRAM are 2 separate regions.
Index ROM
The 256 x 8 bits index ROM can be used as a 4-bit mode or an 8-bit mode.
I/O ports
The IOA port can be selected by software separately as input or output, and with/without internal pull-low and
different chattering clocks in order for HALT release/ interrupt trigger to reduce the bounce of key_scan:
PH6: 512Hz PH8:128Hz PH10: 32Hz
The pull-low of the IOA will be masked off for those pins defined as output pins.
The IOA port can be used as a pseudo serial output port.
The IOB port can be selected by software separately as input or output.
The IOC port can be selected by software separately as input or output, and with/without internal pull-low and
different chattering clocks in order for HALT release/ interrupt trigger to reduce the bounce of key_scan.
The IOD port can be selected by software separately as input or output.
The IOD port can be used as a pseudo serial output port.
The initial state of all I/O ports is standard input state and IOA, C have pull-low device.
Before setting some pins from input to output, you can execute the output function to ensure their output value.
The S ports are input pins that contain pull-low. The L_L_H resistor can be selected by mask option and
different chattering clocks in the same manner as the IOA, C ports.
Resistor to frequency converter
We use an RC oscillation circuit and a 16-bit counter to calculate the relative resistance of temperature and
humidity sensor. The diagram is shown below:
ELP
RTP
TMS
ENX
RT
EHM
RHM
PH9
Timer & R/F
Controller
MRF
RH
FIN
ERR
Rref
Freq.
CL
LD
Freq.
CL
LD
RR
ENX
CX
FIN
CX
16-Bit Counter
4-Bit Data Bus
There are two types of methodology for measuring the input frequency: first, set FIN (i.e. CX) as the clock
input, using timer 2 as interval control or using software to directly control the interval. Second, if the FIN (CX)
frequency is too low, either because of a poor resolution for a fixed interval or a longer interval for better
Preliminary
8
Ver. 0.0
resolution but with a longer read-out rate (for example: 10 seconds per read-out), you can switch the measure
mode in order to set FIN (CX) as interval control (it will enable the counter from first FIN rising edge to the next
rising edge, then will generate an interrupt) and use FREQ (internal frequency generator output) as clock
input, hence you can count the interval of CX.
To measure the resistor value of the temperature and humidity sensor, we must first measure the frequency
of Rref, then the frequency of sensor.
Fref= K/Rref CX and
Fsensor= K/Rsensor CX, hence
Rsensor= Rref * Freq/Fsensor.
Where K is a coefficient for RC-oscillation and will be a constant in a short time period.
Keyboard scanning function
SEG11~26 shares the keyboard scanning output, the output of the keyboard scanning is a P open-drain to
VDDO (positive power supply) and all other SEGs and COMs are in Hi-z state during this period. This will
minimize the effect of the LCD output.
The segment 11-26 also could be used as keyscan output and LCD still could be displayed with only slightly
affected.
SPK 00b5 b4 b3 b2 b1 b0.
b5: 1 will disable key-scan output.
b4: 1 will set all keyscan output as high, if b5=0.
b3~b0: will set the corresponding segment output as 1, if b5=0 and b4=0.
During power on, LCD off, STOP condition. All the common & segment output will be the chips supply power.
EL-light
Set the ELC and ELP clock and duty cycle by ELC X instruction, then turn on and off the ELC and ELP output
by SF X and RF X instruction. With external transistor, diode, inductor and resistor, we can pump the Elpanel
to AC 100~250V.
L1
D1
R1
ELP
Q1
EL-plane
R2
Q2
ELC
LIT
ELP
ELC
While the light is turned on, the ELC will turn on before the ELP, but when the light is turned off, the ELP and
ELC will turn off after the next falling edge of the ELC to make sure no voltage is left on the EL- panel.
Preliminary
9
Ver. 0.0
Timer
The 6-bit programmable timer can select PH3/PH9/PH15/FREQ (timer 2 can also select PH5/PH7/PH11/
PH13 by TM2X instruction) as the clock source. When it underflows, the HALT release signal is generated.
Predivider
The predivider is a 15-stage counter that uses PH0 as the clock source. The output of T-F/F is changed when
the input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed, or
power-on or external reset is used. When PH14 is changed from H to L, the HALT release signal is generated.
Alarm/frequency/melody
There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output
from BZ/BZB.
The frequency counter can use software to select 1/2 duty, 1/3 duty or 1/4 duty drive mode.
Freq.
1/2 Duty Frequency
1/3 Duty Frequency
1/4 Duty Frequency
INT function
The INT pin can be selected by mask option as pull-high/pull-low or none, and rising edge/falling edge trigger.
Watchdog timer
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The
watchdog enable flag will be disabled by power-on reset or reset-pin reset condition, but cannot be disabled
by watchdog reset itself.
HALT function
The HALT instruction will disable all clocks except the predivider, timer, frequency counter, PWM, EL-light
generator and chattering clock to minimize the operating current.
STOP function
The STOP instruction will disable all clocks to minimize the standby current, so only two external factors (INT,
IOA/IOC/S port, keyscan) can release the STOP condition.
Instruction Table (Total 150 instructions)
Instruction
NOP
LCT Lz, Ry
Machine Code
0000 0000 0000 0000
0000 001Z ZZZZ YYYY
Function
No Operation
Lz Чʳ { 7SEG Чʳ Ry}
LCB Lz, Ry
0000 010Z ZZZZ YYYY
Lz Чʳ { 7SEG Чʳ Ry}
LCP Lz, Ry
0000 011Z ZZZZ YYYY
Lz Ч Ry , AC
LCD Lz, @HL
0000 100Z ZZZZ 0000
Lz Ч T@HL
LCT Lz, @HL
0000 100Z ZZZZ Z-01
Lz {7SEG @HL
Preliminary
10
Flag/Remark
Ver. 0.0
Instruction
LCB Lz, @HL
LCP Lz, @HL
OPA Rx
Machine Code
0000 100Z ZZZZ Z-10
0000 100Z ZZZZ Z-11
0000 1010 0XXX XXXX
Function
Lz {7SEG @HL
Lz @HL, AC
Port(A) Чʳ Rx
OPAS Rx, D
0000 1011 DXXX XXXX
A1, 2, 3, 4 Чʳ Rx0, Rx1, D, Pulse
OPB Rx
0000 1100 0XXX XXXX
Port(B) Чʳ Rx
OPC Rx
0000 1101 0XXX XXXX
Port(C) Чʳ Rx
OPD Rx
0000 1110 0XXX XXXX
Port(D) Чʳ Rx
OPDS Rx
0000 1111 DXXX XXXX
D1, 2, 3, 4 Чʳ Rx0, Rx1, D, Pulse
FRQ Rx, D
FRQ D,@HL
0001 00DD 0XXX XXXX
0001 01DD 0000 0000
Flag/Remark
FREQ Чʳ Rx, AC
DD=00: 1/4 Duty
DD=01: 1/3 Duty
DD=10: 1/2 Duty
DD=11: 1/1 Duty
FREQ Ч T@HL
FRQX D,X
0001 10DD XXXX XXXX
FREQ Ч X
MVL Rx
0001 1100 0XXX XXXX
L Ч Rx
MVH Rx
0001 1101 0XXX XXXX
H Ч Rx
MPW1 Rx
0001 1110 0XXX XXXX
PWM1 Ч Rx , AC
MPW2 Rx
0001 1111 0XXX XXXX
PWM2 Ч Rx , AC
ADC Rx
0010 0000 0XXX XXXX
AC Ч Rx+AC+CF
CF
AC Ч @HL+AC+CF
CF
AC, Rx Ч Rx+AC+CF
CF
AC, @HL Ч @HL+AC+CF
CF
AC Ч Rx+ACB+CF
CF
AC Ч @HL+ACB+CF
CF
AC, Rx Ч Rx+ACB+CF
CF
AC, @HL Ч @HL+ACB+CF
CF
AC Ч Rx+AC
CF
0010 0100 1000 0000
AC Ч @HL+AC
CF
0010 0101 0XXX XXXX
AC,Rx Ч Rx+AC
CF
AC, @HL Ч @HL+AC
CF
AC Ч Rx+ACB+1
CF
AC Ч @HL+ACB+1
CF
AC, Rx Ч Rx+ACB+1
CF
AC,@HL Ч @HL+ACB+1
CF
ADC @HL
ADC* Rx
ADC* @HL
SBC Rx
SBC @HL
SBC* Rx
SBC* @HL
ADD Rx
ADD @HL
ADD* Rx
ADD* @HL
SUB Rx
SUB @HL
SUB* Rx
SUB* @HL
ADN Rx
ADN @HL
ADN* Rx
ADN* @HL
AND Rx
AND @HL
Preliminary
0010 0000 1000 0000
0010 0001 0XXX XXXX
0010 0001 1000 0000
0010 0010 0XXX XXXX
0010 0010 1000 0000
0010 0011 0XXX XXXX
0010 0011 1000 0000
0010 0100 0XXX XXXX
0010 0101 1000 0000
0010 0110 0XXX XXXX
0010 0110 1000 0000
0010 0111 0XXX XXXX
0010 0111 1000 0000
0010 1000 0XXX XXXX
0010 1000 1000 0000
0010 1001 0XXX XXXX
0010 1001 1000 0000
0010 1010 0XXX XXXX
0010 1010 1000 0000
AC Ч Rx+AC
AC Ч @HL+AC
AC, Rx Ч Rx+AC
AC,@HL Ч @HL+AC
AC Ч Rx AND AC
AC Ч @HL AND AC
11
Ver. 0.0
Instruction
AND* Rx
AND* @HL
EOR Rx
EOR @HL
EOR* Rx
EOR* @HL
OR Rx
OR @HL
OR* Rx
Machine Code
0010 1011 0XXX XXXX
0010 1011 1000 0000
0010 1100 0XXX XXXX
0010 1100 1000 0000
0010 1101 0XXX XXXX
0010 1101 1000 0000
0010 1110 0XXX XXXX
0010 1110 1000 0000
0010 1111 0XXX XXXX
Function
AC, Rx Ч Rx AND AC
Flag/Remark
AC,@HL Ч @HL AND AC
AC Ч Rx EOR AC
AC Ч @HL EOR AC
AC, Rx Ч Rx EOR AC
AC,@HL Ч @HL EOR AC
AC Ч Rx OR AC
AC Ч @HL OR AC
AC, Rx Ч Rx OR AC
OR* @HL
0010 1111 1000 0000
ADCI Ry,D
0011 0000 DDDD YYYY
AC Ч Ry+D+CF CF
ADCI* Ry,D
0011 0001 DDDD YYYY
AC, Ry Ч Ry+D+CF
CF
SBCI Ry,D
0011 0010 DDDD YYYY
AC Ч Ry+DB+CF
CF
SBCI* Ry,D
0011 0011 DDDD YYYY
AC, Ry Ч Ry+DB+CF
CF
ADDI Ry,D
0011 0100 DDDD YYYY
AC Ч Ry+D
CF
ADDI* Ry,D
0011 0101 DDDD YYYY
AC, Ry Ч Ry+D
CF
SUBI Ry,D
0011 0110 DDDD YYYY
AC Ч Ry+DB+1
CF
SUBI* Ry,D
0011 0111 DDDD YYYY
AC, Ry Ч Ry+DB+1
CF
ADNI Ry,D
0011 1000 DDDD YYYY
AC Ч Ry+D
ADNI* Ry,D
0011 1001 DDDD YYYY
AC, Ry Ч Ry+D
ANDI Ry,D
0011 1010 DDDD YYYY
AC Ч Ry AND D
ANDI* Ry,D
0011 1011 DDDD YYYY
AC, Ry Ч Ry AND D
EORI Ry,D
0011 1100 DDDD YYYY
AC Ч Ry EOR D
EORI* Ry,D
0011 1101 DDDD YYYY
AC, Ry Ч Ry EOR D
ORI Ry,D
0011 1110 DDDD YYYY
AC Ч Ry OR D
ORI* Ry,D
0011 1111 DDDD YYYY
AC, Ry Ч Ry OR D
INC* Rx
0100 0000 0XXX XXXX
AC, Rx Ч Rx+1
CF
AC, @HL Ч @HL+1
CF
AC, Rx Ч Rx-1
CF
AC, @HL Ч @HL-1
CF
INC* @HL
DEC* Rx
DEC* @HL
0100 0000 1000 0000
0100 0001 0XXX XXXX
0100 0001 1000 0000
AC,@HL Ч @HL OR AC
IPA Rx
0100 0010 0XXX XXXX
AC, Rx Ч Port(A)
IPB Rx
0100 0100 0XXX XXXX
AC, Rx Ч Port(B)
IPS Rx
0100 0110 0XXX XXXX
AC, Rx Ч Port(S)
IPC Rx
0100 0111 0XXX XXXX
AC, Rx Ч Port(C)
IPD Rx
0100 1000 0XXX XXXX
AC, Rx Ч Port(D)
MAF Rx
0100 1010 0XXX XXXX
AC,Rx Ч STS1
Preliminary
12
B3: CF
B2: ZERO
B1: (No use)
B0: (No use)
Ver. 0.0
Instruction
Machine Code
Function
MSB Rx
0100 1011 0XXX XXXX
AC,Rx Ч STS2
MSC Rx
0100 1100 0XXX XXXX
AC,Rx Ч STS3
MCX Rx
0100 1101 0XXX XXXX
AC,Rx Ч STS3X
MSD Rx
0100 1110 0XXX XXXX
AC,Rx Ч STS4
SR0 Rx
0101 0000 0XXX XXXX
ACn, Rxn Ч Rx(n+1)
AC3, Rx3 Ч 0
SR1 Rx
0101 0001 0XXX XXXX
ACn, Rxn Ч Rx(n+1)
AC3, Rx3 Ч 1
SL0 Rx
0101 0010 0XXX XXXX
ACn, Rxn Ч Rx(n-1)
AC0, Rx0 Ч 0
SL1 Rx
0101 0011 0XXX XXXX
Can, Rxn Ч Rx(n-1)
AC0, Rx0 Ч 1
DAA
DAA* Rx
0101 0100 0000 0000
0101 0101 0XXX XXXX
Flag/Remark
B3: (No use)
B2: SCF2(HRx)
B1: SCF1(CPT)
B0: BCF
B3: SCF7(PDV)
B2: PH15
B1: SCF5(TMR1)
B0: SCF4(INT)
B3: SCF9(RFC)
B2: SCF0(APT)
B1: SCF6(TMR2)
B0: (No use)
B3: (No use)
B2: RFOVF
B1: WDF
B0: CSF
AC Ч BCD(AC)
CF
AC, Rx Ч BCD(AC)
CF
DAA* @HL
0101 0101 1000 0000
AC, @HL Ч BCD(AC)
CF
DAS
0101 0110 0000 0000
AC Ч BCD(AC)
CF
AC, Rx Ч BCD(AC)
CF
AC, @HL Ч BCD(AC)
CF
DAS* Rx
0101 0111 0XXX XXXX
DAS* @HL
0101 0111 1000 0000
LDS Rx,D
0101 1DDD DXXX XXXX
AC, Rx Ч D
LDH Rx,@HL
0110 0000 0XXX XXXX
AC, Rx Ч H(T@HL)
LDH* Rx,@HL
0110 0001 0XXX XXXX
AC, Rx Ч H(T@HL)
HL Ч HL + 1
LDL Rx,@HL
0110 0010 0XXX XXXX
AC, Rx Ч L(T@HL)
LDL* Rx,@HL
0110 0011 0XXX XXXX
AC, Rx Ч L(T@HL)
HL Ч @HL + 1
MRF1 Rx
0110 0100 0XXX XXXX
AC,Rx Ч RFC3-0
MRF2 Rx
0110 0101 0XXX XXXX
AC,Rx Ч RFC7-4
MRF3 Rx
0110 0110 0XXX XXXX
AC,Rx Ч RFC11-8
MRF4 Rx
0110 0111 0XXX XXXX
AC,Rx Ч RFC15-12
STA Rx
0110 1000 0XXX XXXX
Rx Ч AC
STA @HL
Preliminary
0110 1000 1000 0000
@HL Ч AC
13
Ver. 0.0
Instruction
LDA Rx
LDA @HL
Machine Code
0110 1100 0XXX XXXX
Function
Flag/Remark
AC Ч Rx
0100 1100 1000 0000
AC Ч @HL
MRA Rx
0110 1101 0XXX XXXX
CF Ч Rx3
MRW @HL,Rx
0110 1110 0XXX XXXX
AC,@HL Ч Rx
MWR Rx,@HL
0110 1111 0XXX XXXX
AC,Rx Ч @HL
MRW Ry,Rx
0111 0YYY YXXX XXXX
AC,Ry Ч Rx
MWR Rx,Ry
0111 1YYY YXXX XXXX
AC,RxҏЧҏRy
JB0 X
1000 0XXX XXXX XXXX
PC Ч X
if AC0 = 1
JB1 X
1000 1XXX XXXX XXXX
PC Ч X
if AC1 = 1
JB2 X
1001 0XXX XXXX XXXX
PC Ч X
if AC2 = 1
JB3 X
1001 1XXX XXXX XXXX
PC Ч X
if AC3 = 1
JNZ X
1010 0XXX XXXX XXXX
PC Ч X
if AC z 0
JNC X
1010 1XXX XXXX XXXX
PC Ч X
if CF = 0
JZ X
1011 0XXX XXXX XXXX
PC Ч X
if AC0 = 0
JC X
1011 1XXX XXXX XXXX
PC Ч X
if CF = 1
CALL X
1100 0XXX XXXX XXXX
STACK Ч PC+1
PC Ч X
JMP X
1101 0XXX XXXX XXXX
PC Ч X
RTS
1101 1000 0000 0000
SCC X
1101 1001 0XXX XXXX
SCA X
(SMS)
1101 1010 00XX XXXX
SPA X
1101 1100 000X XXXX
SPB X
1101 1101 0000 XXXX
SPC X
1101 1110 000X XXXX
SPD X
TMS Rx
1101 1111 0000 XXXX
1110 0000 0XXX XXXX
TMS @HL
Preliminary
1110 0001 0000 0000
PC Ч STACK
CALL Return
X6 = 1: Cfq = BCLK
X6 = 0: Cfq = PH0
X5 = 1: Cpw = BCLK
X5 = 1: Cpw = PH0
X4, 3 = 1X: Set P(A)
X4, 3 = 01: Set P(S)
X4, 3 = 00 Set P (C)
X2,1,0=001: Cch = PH10
X2,1,0=010: Cch = PH8
X2,1,0=1XX: Cch = PH6
X0~3: S1~4 Enable (SEF0~3)
X5: A1-4 Enable (SEF5)
X4: C1-4 Enable (SEF4)
X4: Set A4~1 Pull-Low
X3~0: Set A4~1 I/O
X3~0: Set D4~1 I/O
X4: Set C4-1 Pull-Low/
Low-Level-Hold
X3~0: Set C4-1 I/O
X3-0: Set D4~1 I/O
Timer1 Ч Rx, AC
Timer1 Ч T@HL
14
Ver. 0.0
Instruction
Machine Code
TMSX
1110 0010 XXXX XXXX
SPK Rx
1110 0011 00XX XXXX
TM2 Rx
1110 0100 0XXX XXXX
TM2 @HL
1110 0101 0000 0000
TM2X X
1110 011X XXXX XXXX
SHE X
1110 1000 0XXX XXX0
SIE* X
1110 1001 0XXX XXXX
PLC X
1110 101X 0XXX XXXX
SRF X
1110 1100 00XX XXXX
SRE X
1110 1101 X0XX 0000
FAST
SLOW
1110 1110 0000 0000
1110 1111 0000 0000
Preliminary
Function
X7,6=11: Ctm=FREQ
X7,6=10: Ctm=PH15
X7,6=01: Ctm=PH3
X7,6=00: Ctm=PH9
X5~0: Set Timer1 Value
X5 = 1: Set all Hi-Z
X4 = 1: Set all = 1
X3 = 0: Set n of 16
Timer2ҏЧҏRx, AC
Flag/Remark
IOC=Normal
IOC=Key_scan
IOC=Key_scan
Timer2ҏЧҏT@HL
X8,7,6=111 : Ctm=PH13
X8,7,6=110 : Ctm=PH11
X8,7,6=101 : Ctm=PH7
X8,7,6=000 : Ctm=PH5
X8,7,6=011 : Ctm=FREQ
X8,7,6=010 : Ctm=PH15
X8,7,6=001 : Ctm=PH3
X8,7,6=000 : Ctm=PH9
X5~0: Set Timer2 Value
X6: Enable HEF6(RFC)
X4: Enable HEF4(TMR2)
X3: Enable HEF3(PDV)
X2: Enable HEF2(INT)
X1: Enable HEF1(TMR1)
X6: Enable IEF6(RFC)
X5: Enable IEF5(KEY_S)
X4: Enable IEF4(TMR2)
X3: Enable IEF3(PDV)
X2: Enable IEF2(INT)
X1: Enable IEF1(TMR1)
X0: Enable IEF0(A,CPT)
X8: Reset PH15~11
X6, 4~0: Reset HRF6, 4~0
X5: Enable Cx Control
X4: Enable Timer2 Control
X3: Enable Counter
X2: Enable RH Output
X1: Enable RT Output
X0: Enable RR Output
X7: Enable SRF7
X6: Enable SRF6
X5: Enable SRF5
X4: Enable SRF4
X3~0: Enable SRF3~0
SCLK: High Speed Clock
SCLK: Low Speed Clock
15
ENX
EHM
ETP
ERR
SRF7 (KEY_S)
SRF6 (A Port)
SRF5 (INT)
SRF4 (C Port)
SRF3~0 (S Port)
Ver. 0.0
Instruction
SF X
RF X
Machine Code
1111 0000 X0XX XXXX
1111 0100 X00X 0XXX
SF2 X
1111 1000 0000 0XXX
RF2 X
1111 1001 0000 0XXX
ALM X
1111 101X XXXX XXXX
ELC X
HALT
STOP
Preliminary
1111 110X XXXX XXXX
1111 1110 0000 0000
1111 1111 0000 0000
Function
X7: Reload Set
X5: S-Port Pull-low
X4: WDT Enable
X3: HALT after EL LIGHT
X2: EL LIGHT On
X1: BCF Set
X0: CF Set
X7: Reload Reset
X5: S-port L_L H
X4: WDT Reset
X2: EL LIGHT Off
X1: BCF Reset
X0: CF Reset
X0: Reload Set
X1: Dis-ENX Set
X2: Close all segments
X3: Jump to next page
X0: Reload Reset
X1: Disable Dis-ENX Reset
X2: Release all Segments
X8,7,6=111: FREQ
X8,7,6=100: DC1
X8,7,6=011: PH3
X8,7,6=010: PH4
X8,7,6=001: PH5
X8,7,6=000: DC0
X5~0 Ч PH15~10
X8=1 BCLKX
X8=0 PH0
X7,6=11 BCLK/8
X7,6=10 BCLK/4
X7,6=01 BCLK/2
X7,6=00 BCLK
X5,4=11 1/1
X5,4=10 1/2
X5,4=01 1/3
X5,4=00 1/4
X3,2=11 PH5
X3,2=10 PH6
X3,2=01 PH7
X3,2=00 PH8
X1,0=11 1/1
X1,0=10 1/2
X1,0=01 1/3
X1,0=00 1/4
HALT operation
STOP operation
16
Flag/Remark
RL1
WDF
BCF
CF
RL1
WDF
BCF
CF
RL2
DED
RSOFF
RL2
DED
RSOFF
ELP – CLK
BCLKX
ELP – DUTY
ELC – CLK
ELC – DUTY
Ver. 0.0
Symbol description
AC
ACn
X
Rx
Rxn
Ry
BCF
@HL
HRFn
HEFn
Cfq
Ctm
Fout
PDV
Lz
T@HL
CSF
@L
RFOVF
L(T@HL)
: Accumulator
: Accumulator Bit N
: Address
: Memory of Address X
: Memory Bit N of Address X
: Memory of Working Register Y
: Backup Flag
: Addres s of Index
: HALT Release Flag
: HALT Release Enable Flag
: Clock Source of Frequency Generator
: Clock Source of Timer
: RFC Frequency
: Predivider
: LCD Latch
: Address of Index ROM
: Clock Source Flag
: Low Address of Index
: RFC Overflow Flag
: Low Nibble of Index ROM
D
PC
CF
ZERO
WDF
HL
BCLK
IEFn
SRFn
SCFn
Cch
TMR
()
SEFn
FREQ
ADF
DAC
@H
H(T@HL)
: Immediate Date
: Program Counter
: Carry Flag
: Zero Flag
: Watchdog Timer Enable Flag
: Index Register
: System clock stops only in STOP condition
: Interrupt Enable Flag
: STOP Release Enable Flag
: Start Condition Flag
: Clock Source of Chattering Detector
: Timer Overflow Release Flag
: Content of Register
: Switch Enable Flag
: Frequency Generator Setting Value
: ADC Flag
: Digital-to-Analog Converter Output Signal
: High Address of Index
: High Nibble of Index ROM
Appendix (Important Issue for APU429/428)
Chip’s internal vlotage V.S. power mode and external connection
VDD1
VDD2
VDD3
VDD4
AG
Vsupply
2 × VDD1
3 × VDD1
4 × VDD1
BAK
VDD1
LI
1/2 × Vsupply
Vsupply
3/2 × Vsupply
2 × Vsupply
BCF=0
BCF=1
VDD1
VDD2
EXT-V
1/2 × Vsupply
Vsupply
3/2 × Vsupply
2 × Vsupply
Note
VDD2
*3
*1
*2
Note: *1: VDD3 is only used for LCD operating in 1/3 bias and 1/4 bias. If 1/2 bias chosen, VDD3 need be
connected to VDD2 (VDD3 is equal to VDD2).
*2: VDD4 is only used for LCD operating in 1/4 bias. If 1/3 bias chosen, VDD4 need be connected to VDD3
(VDD4 is equal to VDD3). If 1/2 bias chosen, VDD4 need be connected to VDD2 (VDD4 is equal to VDD2).
*3: BAK is defined as chip’s internal power supply node, which is used only for internal logic circuitry.
A. Whatever the power mode used, all external VDD# pins must connect a capacitor (0.05PF or 0.1PF) to
GND for decoupling power noise using.
B. All VDD# pins other than Vsupply are from voltage charge pump, i.e. If no clock, then VDD# pins can
not supply out.
C. Vsupply is the power supply for Chip and depends on the power mode used, all the input and output
pins voltage range follow the Vsupply.
The capacitor connected between CUP2 and CUP3 is only when APU429 operating in 1/4 bias.
Some notes for BCF flag
BCF is always set to sHighs automatically after Power on, Reset and STOP mode.
A. For power saving use, BCF may be set to sLows which can reduce chip’s current consumption.
Preliminary
17
Ver. 0.0
B. Ag and Li battery mode applications:
After Power on, Reset or release from STOP mode. Need to wait 2 seconds long, then can set BCF to
sLows.
C. Larger current load and fast clock:
a. BCF should be set to sHighs for the case of fast clock or larger current load (such as RFC, ADC,
DAC, EL-light and Buzzer output) use.
b. After set BCF to shighs, need wait 2 ms long at least, then can enable larger current load. Or after
disable Larger current load, need wait 2ms long at least, then can set BCF to sLows
D. Li battery mode applications:
Especially for Li battery mode, BCF switching will cause a temporary current surge (or power noise) on
BAK. Furthermore if not necessary, don’t switch BCF too often as possible.
E. Improperly use of BCF will cause malfunction to chips.
F. Lower current consumption and reliability:
The chip’s reliability will greatly decrease if invalid use BCF, especially for Li-battery mode. Because
the chip’s internal power also switches between VDD1 and VDD2, which also cause a temporary power
noise.
Input pin
Any input pins floating will cause chips in malfunction and large current consumption.
32.768kHz Xctal oscillator
Always layout the Xctal as close the Chips as possible and donct place any signals across the layout routing.
Since Xctal oscillation circuit consumes current only 0.5PA to 1PA, any power noise will disturb the oscillation.
The proper external capacitors for XIN and XOUT are necessary for the accuracy and stability of oscillation.
1 / (Cin+Cpcb) + 1 / (Cout+Cpcb ) = 1/CL
The Chipcs XOUT pin has an internal capacitor around 10~20pF connected to BAK (chipcs internal
Node).
For example:
Epsoncs C-001R 20ppm, CL=12.5pF
CIN = 25pF
COUT = 15pF
The time accuracy will be around r 0.5 second/day
Note: The parasitic capacitors of Xctal pins in PCB layout need be considered in above calculation.
RFC/Event counter/IOA for APU429
If anyone uses RFC / Event counter function and IOAs in the same application, make sure the pin IOA1
(which is corresponding to CX by mask option) must set as IOAcs output mode by SPA instruction. Or the
signal changes on CX pin may cause HALT release or interrupt for IOAcs port. In this case the program
couldn’t function properly.
Preliminary
18
Ver. 0.0