LatticeXP™ Standard Evaluation Board User’s Guide June 2008 EB12_02.4 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP Standard Evaluation Board provides a convenient platform to evaluate, test and debug user designs. The board consists of a LatticeXP-10 FPGA in a 256 fpBGA package, power input jacks, a clock oscillator (33MHz) and I/O connections. The LatticeXP I/Os are connected to a rich variety of interfaces including switches (momentary and ON/OFF), LEDs, SMA pads, RJ45, 0.10” headers and PCB test points. The information in this document pertains to boards marked as ‘Rev. A’ and ‘Rev. B’. This marking is located on the front of the board, beneath the Lattice logo. Any information that only applies to either the ‘Rev. A’ or ‘Rev.B’ board will be explicitly stated as such. Features Included • LatticeXP FPGA: LFXP10C-5F256C or LFXP10E-5F256C • On-board power supply (rev. B only) • Prototyping area • 188 user I/Os, grouped in eight I/O banks • Independent voltage control for core, I/O and clock voltages • 33MHz on-board oscillator • Status LEDs, input switches • Lattice ispDOWNLOAD cable • AC adapter (rev. B only) Optional • Optional SMA connectors (up to 16) for high-speed clock and data interfacing. The board includes pads for these connectors. The SMA connectors must be procured and installed separately by the user. Software Support • To target your HDL design to the LatticeXP device, use the ispLEVER® design software. You can learn more about ispLEVER on the Lattice web site at: www.latticesemi.com/software. • To download your program to the LatticeXP device, use the ispVM® System software. ispVM System can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm. • ispTRACY™ in-system logic analysis support (ispTRACY is included with the ispLEVER design software) 2 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 1. LatticeXP Standard Evaluation Board Electrical, Mechanical and Environmental Specifications The nominal board dimensions are 7 inches by 3.9 inches. The environmental specifications are as follows: • Operating temperature: 0ºC to 55ºC • Storage temperature: -40ºC to 75ºC • Humidity: < 95% without condensation • VDC input (+/- 10%) up to 4A Additional Resources Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click on the appropriate evaluation board, then follow the appropriate links for items such as updated documentation, software, sample designs, IP evaluation bitstreams, and more. LatticeXP Device This board features a LatticeXP FPGA with either a 3.3V or a 1.2V DC core. The board is populated with a LatticeXP-10 device in plastic 256-ball fpBGA (1mm pitch) package. Density migration is possible for Lattice XP devices in the 256 fpBGA package. A complete description of this device can be found in the LatticeXP Family Data Sheet on the Lattice web site at www.latticesemi.com. Device Core and I/O Voltage Boards shipping with a 3.3V DC core device will allow operation of the core between 1.8V and 3.3V DC. Jumpers (JP4, JP5 and JP6) are available to switch between 3.3V, 1.2V and an adjustable supply between the other two voltages. Boards shipping with a 1.2V core device will not have headers installed for core voltage selection. JP4 will be shorted on the board. Figure 2 shows the core voltage selection jumpers. 3 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 2. Core Voltage Select Jumpers JP4 1.2V JP5 ADJ JP6 3.3V VCC_CORE The LatticeXP device has eight sysIO™ buffer banks; each is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO) and two voltage reference resources, VREF1 and VREF2, that allow each bank to be completely independent from the others. Please refer to the LatticeXP Family Data Sheet for additional information about supported I/O standards. This data sheet can be downloaded from www.latticesemi.com. The LatticeXP Standard Evaluation Board provides individual control of each I/O bank capable of supporting VCCIO between 1.2V and 3.3V. The board provides jumper blocks which allow the end user to select 1.2V, 3.3V or an adjustable voltage between these two voltages. Figure 3 shows a typical layout for a VCCIO select jumper block. Table 1 details the VCCIO bank selection connectors. 1.2V ADJ 3.3V Figure 3. VCCIO Jumper Block VCCIO Table 1. VCCIO Connectors VCCIO Bank Connector Number VCCIO0 JP1 VCCIO1 JP2 VCCIO2 JP3 VCCIO3 JP10 VCCIO4 JP11 VCCIO5 JP12 VCCIO6 JP13 VCCIO7 JP14 Device Clocks The LatticeXP Standard Evaluation Board provides a variety of ways to input clock signals to the LatticeXP device. These include an on-board crystal oscillator, SMA connectors and 0.1” header pins. Clock inputs connect to pri- 4 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor mary clock inputs and device PLL inputs. Clock outputs connect to PLL outputs and external feedback pins. Table describes the clock connections to the LatticeXP device. Table 2. Lattice XP-10 Clock Pins and Connections PCB Connection1 On-Board OSC. Resistor2 Buffered (Y/N)3 RLM0_PLLT_IN_A J23-15 R89 Y M16 RLM0_PLLC_IN_A J23-16 N/A N L13 RLM0_PLLT_OUT_A J23-9 N/A N XP-10 Pin Number N16 XP Pin Label M14 RLM0_PLLC_OUT_A J23-10 N/A N N15 RLM0_PLLT_FB_A J23-17 N/A N P15 RLM0_PLLC_FB_A J23-18 N/A N F16 RUM0_PLLT_IN_A J24-7 R90 Y G16 RUM0_PLLC_IN_A J24-8 N/A N F13 RUM0_PLLT_OUT_A J24-17 N/A N G12 RUM0_PLLC_OUT_A J24-18 N/A N C15 RUM0_PLLT_FB_A J24-3 N/A N D15 RUM0_PLLC_FB_A J-24-4 N/A N M1 LLM0_PLLT_IN_A SMA J12 N/A N M2 LLM0_PLLC_IN_A SMA J14 N/A N K4 LLM0_PLLT_OUT_A SMA J16 N/A N K5 LLM0_PLLC_OUT_A SMA J18 N/A N L5 LLM0_PLLT_FB_A SMA J20 N/A N M6 LLM0_PLLC_FB_A SMA J22 N/A N G3 LUM0_PLLT_IN_A SMA J19 N/A N G2 LUM0_PLLC_IN_A SMA J21 N/A N E3 LUM0_PLLT_OUT_A SMA J15 N/A N F4 LUM0_PLLC_OUT_A SMA J17 N/A N D2 LUM0_PLLT_FB_A SMA J7 N/A N D3 LUM0_PLLC_FB_A SMA J9 N/A N A7 PCLKT0_0 OSC R104 N A8 PCLKC0_0 Test Point N/A N H16 PCLKT2_0 J24-9 N/A N J16 PCLKC2_0 J24-10 N/A N T10 PCLKT4_0 Test Pad N/A N T11 PCLKC4_0 Test Pad N/A N K1 PCLKT6_0 SMA J8 N/A N K2 PCLKC6_0 SMA J10 N/A N 1. Check the schematic pages for termination resistors connected to these pins. 2. 0_ resistor connecting to on-board oscillator. 3. Indicates a non-inverting buffer between the oscillator and pin. The oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs, depending on installation of several 0Ω resistors. The oscillator has a 22Ω series termination resistor at the oscillator output. These inputs correspond with PCLKT0, RLM0_PLLT_IN_A and RUM0_PLLT_IN_A. The oscillator supply voltage is changeable, via the VCC_OSC header, located at JP9. The onboard oscillator operates at 3.3V. It is possible to power this socket from the following supplies: 3.3V, VCCIO0, VCCIO2 or VCCIO3, depending on the I/O bank being used and the operating conditions for the chosen oscillator. 5 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 4 shows the layout and connections for JP9. There is also an optional 10K pull-up (R91) connect to pins 1 and 4 of the oscillator socket, in the event a oscillator with enable is required. The oscillator is also connected to J24-26, for use as a clock input to a logic analyzer. VCCIO3 VCCIO2 VCCIO0 3.3V Figure 4. VCC_OSC Jumper Block JP9 VCC_OSC 6 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Device I/O Banks 0 and 1 I/O banks 0 and 1 represent general purpose I/O banks, which connect to a combination of test pads, switches, LEDs and an RJ45 connector. The switches consist of two user defined push-button switches and an 8-position DIP switch. Both types of switches are pulled up to the associated VCCIO voltage with 10KΩ resistors and connected to GND when activated (pushed or levered in the down position). LEDs are active (lit) when the device I/O is low. The RJ-45 connector is connected using paired I/O connections. Table 3 details the I/O banks 0 and 1 connections. Unlisted pins in banks 0 and 1are connected to test pads on the board. Table 3. Banks 0 and 1 I/O Connections I/O Bank XP-10 Pin Number Connection 0 C5 LED D8 0 F5 LED D9 0 B1 LED D10 0 A2 LED D11 0 B2 LED D12 0 B3 LED D13 0 A3 LED D14 0 D5 LED D15 0 D6 RJ-45 J25-1 0 E6 RJ-45 J25-2 0 B6 RJ-45 J25-3 0 A4 RJ-45 J25-4 0 B5 RJ-45 J25-5 0 A5 RJ-45 J25-6 0 D7 RJ-45 J25-7 0 E7 RJ-45 J25-8 0 C6 Switch SW7 1 0 A6 Switch SW7 2 0 D8 Switch SW7 3 0 E8 Switch SW7 4 0 C7 Switch SW7 5 0 B7 Switch SW7 6 0 B8 Switch SW7 7 0 E9 Switch SW7 8 1 C8 Pushbutton SW0 1 C9 Pushbutton SW1 7 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Device I/O Banks 2 and 3 I/O banks 2 and 3 contain general purpose I/Os with LVDS transmit/receive pairs. These I/O pairs are connected to two 0.1” headers suitable for connecting to a logic analyzer or ribbon cable. Table 4 details the I/O banks 2 and 3 connections. Table 4. Banks 2 and 3 I/O Connections LatticeXP-10 Pin Number Connection I/O Bank Positive Negative1 Positive Negative1 2 C15 D15 J24-3 J24-4 2 E14 F14 J24-1 J24-2 2 E15 F15 J24-19 J24-20 2 C16 B16 J24-5 J24-6 2 F13 G12 J24-17 J24-18 2 F16 G16 J24-7 J24-8 2 G14 G15 J24-13 J24-14 2 H14 H15 J24-21 J24-22 2 H12 H13 J24-15 J24-16 2 H16 J16 J24-9 J24-10 2 G13 3 J14 3 K16 L16 J23-3 J23-4 3 K13 K12 J23-13 J23-14 J24-25 J15 J23-1 J23-2 3 K15 K14 J23-5 J23-6 3 N16 M16 J23-15 J23-16 3 L14 L15 J23-7 J23-8 3 L13 M14 J23-9 J23-10 3 N14 M15 J23-21 J23-22 3 R16 P16 J23-19 J23-20 3 N15 P15 J23-17 J23-18 3 L12 SW4 1. Blank cell indicated pin with no negative paired pin. Each I/O pair is connected to a resistor termination network, and the trace lengths are matched. Figure 5 shows the termination network for these differential pairs. These resistors are not installed, and the series resistors use a trace between the resistor pads. This trace can be cut to allow the installation of a series termination resistor. The series resistors are 0805 size and the parallel resistors are 0603 size. Figure 5 shows this trace in relation to the resistor pads. Figure 5. Differential I/O Termination Network XP-10 A Pad Connector XP-10 B Pad 8 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 6. Close-up of Series/Passthrough Resistor Pads Cut trace to install resistor Device I/O Banks 4 and 5 I/O banks 4 and 5 consist of general purpose I/O pins. These pins connect to test pads on the board. The test pads are paired with a ground pad, which are spaced on 0.1” centers. In addition to the test pads, these I/O banks are connected to a pull-up, pull-down and series resistor network. The resistor network is not populated. The series resistors are 0805 size, and the pull-up/pull-down resistors are 0603 size. Figure 7 shows the schematic for the individual I/O termination network. Table 5. Banks 4 and 5 I/O Connections Position Pin Number GND Row Pin Number GND Row 1 T3 GND P5 GND 2 R3 GND R1 GND 3 N5 GND R2 GND 4 R4 GND T2 GND 5 T5 GND R5 GND 6 P6 GND T4 GND 7 N6 GND T6 GND 8 M7 GND R6 GND 9 N7 GND T8 GND 10 M8 GND P8 GND 11 R8 GND N8 GND 12 T9 GND P7 GND 13 T7 GND R9 GND 14 R7 GND P9 GND 15 T11 GND N9 GND 16 T10 GND M9 GND 17 P13 GND T13 GND 18 R13 GND P14 GND 19 M11 GND N10 GND 20 N11 GND M10 GND 21 R10 GND P11 GND 22 P10 GND N12 GND 23 R12 GND R11 GND 24 T12 GND P12 GND 25 T15 GND T14 GND 26 R15 GND R14 GND 9 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 7. Banks 4 and 5 I/O Termination Network VCCIO Test Points XP-10 A Pad Device I/O Banks 6 and 7 I/O banks 6 and 7 contain general purpose I/Os with LVDS transmit/receive pairs. The I/O pairs in these banks have been routed to test pads on the PCB and eight pairs have been routed to SMA connectors. Table 6 details the I/O bank 6 and 7 SMA connections. Unlisted pins are connected to test pads on the board. Table 6. Bank 6 and 7 I/O Connections LatticeXP-10 Pin Number 1 SMA Connection I/O Bank Positive Negative Positive Negative1 6 K1 K2 J8 J10 6 M1 M2 J12 J14 6 K4 K5 J16 J18 6 L5 M6 J20 J22 7 D2 D3 J7 J9 7 E1 F1 J11 J13 7 E3 F4 J15 J17 7 G3 G2 J19 J21 Pairs routed to SMA connectors are connected with series and parallel termination resistors, similar to the network shown in Figure 5 (see Bank 2 and 3 description). The SMA connectors are not included with the LatticeXP-Standard board, and must be procured and installed separately. AMP SMA connector 221780-1 or similar is recommended. 10 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor Programming Headers Two programming headers are provided on the evaluation board, providing access to the LatticeXP JTAG port. Both 1x10 and 2x5 formats are available for compatibility with all Lattice ispDOWNLOAD® cables. The pinouts for the headers are provided in Tables 6 and 7. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeXP FPGA device and render the board inoperable. Table 7. JTAG Programming Headers Function JP8 (2x5) JTAG Programming Function JP8 Pin Number (2x5) TCK 1 GND 2 TMS 3 GND 4 TDI 5 VCC (3.3V) 6 TDO 7 GND 8 TRST 9 PROGRAM 10 Table 8. JTAG Programming Headers Function JP7 (1x10) JTAG Programming Function JP7 Pin Number (1x10) VCC (3.3V) 1 TDO 2 TDI 3 PROGRAM 4 TRST 5 TMS 6 GND 7 TCK 8 DONE 9 INIT 10 Power Supply Power can be supplied to the LatticeXP Standard Evaluation Board via the banana jacks (J1, 2, 5, 6 – all PCB revisions), or a coaxial DC connector (J3 – Rev. B PCB only), which receive power from either a bench power supply or a brick style power supply. [Rev. B Only] The output from the DC system is controlled by switch SW1. This is a small surface mount switch that enables and disables the LTC1775 DC-DC conversion chip. The output voltages from the power supply are enabled when the switch is in the left position. [Rev. B Only] The 5.0V to 28.0V DC input voltage (input to either J2 or J3) is converted by DC-DC converters and switching power supplies to provide 3.3V, 1.2V, and an adjustable DC source on the board. The output from these 11 LatticeXP Standard Evaluation Board User’s Guide Lattice Semiconductor supplies travels through surface mounted fuse holders. Fuses are supplied and prevent over-current conditions from damaging the components on the board (vendor: Littlefuse, make: Nano SMF Very Fast Acting, 1.5A or 3A). Both Rev. A and Rev. B boards may be supplied with DC voltage through the banana plug connector. On both boards, J4 is the GROUND connection point, J1 is the +3.3V input, J6 is the +1.2V input and J5 is the input for the Adjustable rail. J2 connects to the VIN input of the on-board power supply of the Rev. B board. J2 is unconnected on the Rev. A board. To directly connect power to the banana jacks on the Rev. B board, the SMT fuses must be removed. SMT fuses are not installed on Rev. A boards. Ordering Information Description Ordering Part Number LatticeXP10C Evaluation Board - Standard (upper voltage) China RoHS EnvironmentFriendly Use Period (EFUP) LFXP10C-L-EV 10 LatticeXP10C Evaluation Board - Standard (lower voltage) LFXP10E-L-EV ispLEVER Base with LatticeXP10 Standard Development Kit LS-XP10-BASE-PC-N Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary — — August 2006 02.1 Changes to I/O Bank column of Bank 6 and 7 I/O Connections table. March 2007 02.2 Added Ordering Information section. April 2007 02.3 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. June 2008 02.4 Updated schematic. Previous Lattice releases. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 13 A B C D 5 Page 2 Programming Interfaces Page 6 SMAs for Testing Differential or Single Ended High-speed Signals 5 4 4 XP FPGA Bank 4 Bank 3 Bank 2 Bank 1 3 Page 5 Single Ended Signal Testing Bank 5 Bank 6 Bank 7 Bank 0 Page 4 Prototype Area 3 1 2 Wednesday, September 07, 2005 Document Number <Doc> Sheet LatticeXP Evaluation Board 1 1 of 8 Rev A Lattice Semiconductor Corporation Date: Size A Title Page 7 Power Supplies Page 3 Diffferential Signals and Logic Analyzer Headers 2 A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Appendix A. Schematic Figure 8. LatticeXP Evaluation Board A MT1 [7] MT2 MT3 VCC_CORE 1 B VCC_3.3V 1 [7] VCCM_3.3V MT4 5 1 [7] FD1 C31 10uF SizeC FD2 TCK TMS TDI TDO TRST C26 10uF SizeC 1 C 1 ispJTAG Download Cable Headers 1 2 3 4 5 6 7 8 9 10 JP7 JP8 FD3 2 4 6 8 10 FD4 C33 0.01uF CC0402 HEADER5X2 hdr5x2_100mil 1 3 5 7 9 HEADER1X10 C32 0.1uF CC0402 1 D 1 Download Cable Header TDO Input TDI Output PROGRAMN Output DONE Input TMS Output TCK Output INITN Input 1 5 FD5 FD6 C34 0.1uF CC0402 C35 0.01uF CC0402 VCC_3.3V PROGRAMN VCC_3.3V TCK DONE INITN VCC_3.3V TDO TDI PROGRAMN TRST TMS 1 14 1 4 4 C36 0.1uF CC0402 TP1 TRST 1 R41 C45 10uF SizeC 0 2 INDUCTOR 2 CR0603 C46 10uF SizeC C43 10uF SizeC C38 0.1uF CC0402 C27 0.1uF CC0402 INDUCTOR C42 10uF SizeC L5 1 L4 C37 0.01uF CC0402 C24 10uF SizeC R39 4.7K CR0603 TDO TDI TMS TCK C40 0.1uF CC0402 C29 0.1uF CC0402 C25 0.1uF CC0402 TDI TMS TCK TDO INITN PROGRAMN DONE C47 0.01uF CC0402 C44 0.01uF CC0402 C39 0.01uF CC0402 C28 0.1uF CC0402 C23 0.1uF CC0402 H4 J12 D4 D13 E5 E12 M5 M12 N4 N13 E4 E13 M4 M13 D16 D14 C14 B14 E16 3 R37 R36 LFXP10E-5F256C VCCP0 VCCP1 VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCJ TDI TMS TCK TDO CFG0 CFG1 GNDP0 GNDP1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H5 J13 2 2 TP2 CCLK DONE PROGRAMN INITN A1 A16 F6 F11 G7 G8 G9 G10 H7 H8 H9 H10 J7 J8 J9 J10 K7 K8 K9 K10 L6 L11 T1 T16 CFG0 CFG1 C3 C2 P3 C1 CFG1 CFG0 C4 B4 10K CR0603 10K CR0603 DONE PROGRAMN INITN CCLK (5 OF 5) LFXP10E (fpBGA256) U4E VCC_3.3V PLANES FOR VCC and GND should be seperate. These are to isolate / filter noise to PLL power C41 0.1uF CC0402 C30 0.1uF CC0402 3 1 2 3 4 SW DIP-2 261milX425mil SW2 Down = 0, Up = 1 VCC_3.3V Slave Serial, External Device Master Serial, External Device Slave Parallel, External Device Internal Flash 2 D ate : DONE Gate SOT-23 Q7 BSS138LT1 D7 GREEN_LED CR0603 R40 470 CR0603 Tuesday, June 17, 2008 1 S he e t 2 JTAG and FPGA Programming Silk Screened 8 pin SOIC package with X through it. Printing to say no PROM needed. 1 SW3 SW PUSHBUTTON 4.7mmX3.5mm D6 YELLOW_LED CR0603 R38 470 CR0603 0 1 0 1 S ize D o c um e nt Num b e r Custom<Doc> Title PROGRAMN 0 0 1 1 CFG1 CFG0 Description 1 of Source Drain 8 Rev A A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 9. JTAG and FPGA Programming 15 A B C D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 [7] [7] [7] VCCIO_2 VCCIO_3 VCC_3.3V HEADER 14x2 J23 5 5 C52 10uF SizeC C49 10uF SizeC DNS DNS R56 R62 DNS R87 0 R81 0 R83 0 R77 0 R75 0 R70 0 R269 0 R66 0 GSRN R64 0 R58 0 R60 0 R54 0 R52 0 R46 0 R48 0 OSC_CLK 3 2 1 Y 4 4 5 SN74AUP1G34 GND A NC VCC U6 Routing to Connector for pairs needs to be matched R85 DNS DNS R73 R79 DNS R68 [4] DNS DNS R44 R50 R42 0 4 C53 0.1uF CC0402 C50 0.1uF CC0402 R89 0 DNS GSRN C54 0.01uF CC0402 C51 0.01uF CC0402 J11 K11 N15 P15 R16 P16 N14 M15 L13 M14 L14 L15 L12 N16 M16 K15 K14 K13 K12 K16 L16 J14 J15 PR24A / RDQS24 PR24B LFXP10E-5F256C VCCIO3_J11 VCCIO3_K11 PR34A / RLM0_PLLT_FB_A PR34B / RLM0_PLLC_FB_A PR33A / RDQS33 PR33B PR31A / VREF0_3 PR32B / RLM0_PLL_RST PR29A / RLM0_PLLT_OUT_A PR29B / RLM0_PLLC_OUT_A PR28A PR28B PR26A PR25A / RLM0_PLLT_IN_A PR25B / RLM0_PLLC_IN_A BANK 2 3 3 2 1 Y 4 5 VCCIO_0 SN74AUP1G34 GND A NC VCC U7 VCCIO2_G11 VCCIO2_H11 PCLKT2_0 / PR17A PCLKC2_0 / PR17B RDQS16 / PR16A PR16B VREF0_2 / PR14A RUM0_PLL_RST / PR15B PR13A PR13B RUM0_PLLT_IN_A / PR12A RUM0_PLLC_IN_A / PR12B PR11B RUM0_PLLT_OUT_A / PR8A RUM0_PLLC_OUT_A / PR8B RDQS7 / PR7A PR7B VREF1_2 / PR5A PR6B PR4A PR4B RUM0_PLLT_FB_A / PR3A RUM0_PLLC_FB_A / PR3B (3 OF 5) LFXP10E (fpBGA256) PR22A / VREF1_3 PR23B PR21A PR21B PR19A PR19B BANK 3 U4C 3 G11 H11 H16 J16 H12 H13 H14 H15 G14 G15 F16 G16 G13 F13 G12 C16 B16 E15 F15 E14 F14 C15 D15 VCCIO_0 VCCIO_2 VCCIO_3 VCC_3.3V R90 0 DNS R86 R80 R74 R69 R63 R57 R51 R45 DNS DNS DNS DNS DNS DNS DNS DNS 2 4 6 8 2 HEADER4X2 1 3 5 7 JP9 Da te : Size B Title 10K CR0603 R91 14 13 12 11 10 9 8 33MHz DIP14 Y1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Tuesday, June 17, 2008 Do c ume nt Numbe r <Doc> Banks 3 and 4 Oscillator 1 2 3 4 5 6 7 Routing to Connector for pairs needs to be matched R88 0 R82 0 R84 0 R78 0 R76 0 R71 0 R72 0 R67 0 R65 0 R59 0 R61 0 R55 0 R53 0 R47 0 R49 0 R43 0 2 27 1 1 She e t R92 22 3 J24 of 28 2 8 Re v A C48 0.1uF CC0603 OSC_CLK [4] HEADER14x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14x2 Header Top View OSC_CLK 1 A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 10. Banks 3 and 4 A B C D VCCIO_0 [7] VCCIO_1 [7] TP_6 C58 0.01uF CC0402 E11 F12 B13 A14 TP_E11 TP_F12 TP_B13 TP_A14 C57 0.1uF CC0402 C13 A13 TP_C13 TP_A13 C60 10uF SizeC C56 10uF SizeC 5 TP_7 C61 0.1uF CC0402 C62 0.01uF CC0402 VCCIO_0 C55 0.1uF CC0402 (4 OF 5) TP_18 TP_17 TP_16 TP_15 4 C59 0.1uF CC0402 LFXP10E-5F256C VCCIO1_F9 VCCIO1_F10 PT35A PT35B PT34A / TDQS34 PT34B / VREF0_1 PT32A PT33B PT31A PT31B PT30A / D0 PT30B PT29A / VREF1_1 PT29B / D1 PT28A / D2 PT28B PT27A PT27B / D3 PT26A / TDQS26 PT26B PT24A / D4 PT25B PT23A / D5 PT23B 4 PT8A PT9B PT7A PT7B PT6A PT6B BANK 0 VCCIO0_F7 VCCIO0_F8 CS1N / PT20A BUSY / PT20B PCLKT0_0 / PT19A PCLKC0_0 / PT19B TDQS18 / PT18A PT18B PT16A PT17B WRITEN / PT15A DOUT / PT15B VREF0_0 / PT14A PT14B DI / PT13A PT13B CSN / PT12A PT12B PT11A PT11B TDQS10 / PT10A VREF1_0 / PT10B LFXP10E (fpBGA256) PT22A PT22B / D0 (MSB) PT21A PT21B/D7(LSB) BANK 1 U4D C63 0.1uF CC0402 F9 F10 B15 A15 E10 C10 TP_E10 TP_C10 TP_B15 TP_A15 B12 A12 TP_B12 TP_A12 C11 D12 A11 C12 TP_C11 TP_D12 D11 B11 D9 B9 TP_D9 TP_B9 TP_D11 TP_B11 B10 A10 TP_A11 TP_C12 A9 D10 C8 C9 TP_B10 TP_A10 SW0 SW1 TP_A9 TP_D10 TP_C8 TP_C9 5 F7 F8 B8 E9 A7 A8 C7 B7 D8 E8 C6 A6 D7 E7 B5 A5 B6 A4 D6 E6 A3 D5 B2 B3 B1 A2 C5 F5 RJ6 RJ7 RJ4 RJ5 RJ2 RJ3 RJ0 RJ1 TP_D7 TP_E7 TP_B5 TP_A5 TP_B6 TP_A4 TP_D6 TP_E6 TP_14 OSC_CLK [3] 3 3 D8 GREEN_LED CR0603 R93 220 CR0603 TP_A8 TP_8 VCCIO_0 VCCIO_0 TP_A7 R104 0 RJ0 RJ2 RJ4 RJ6 D9 GREEN_LED CR0603 R94 220 CR0603 2 4 6 8 D11 GREEN_LED CR0603 R96 220 CR0603 RJ1 RJ3 RJ5 RJ7 D12 GREEN_LED CR0603 R97 220 CR0603 D13 GREEN_LED CR0603 R98 220 CR0603 TP_13 TP_12 TP_11 TP_10 TP_9 2 R105 R106 R107 R108 R109 R110 R111 R112 10K 10K 10K 10K 10K 10K 10K 10K CR0603CR0603CR0603CR0603CR0603CR0603CR0603CR0603 RJ-45 1 3 5 7 J25 D10 GREEN_LED CR0603 R95 220 CR0603 2 Title Da te : Size B Tuesday, June 17, 2008 Do c ume nt Numbe r <Doc> Banks 0 and 1 SW7 SW DIP-8 861milX425mil SW1 1 1 SW4 1 She e t of 8 SW PUSHBUTTON 4.7mmX3.5mm 2 SW6 1 4 SW PUSHBUTTON 4.7mmX3.5mm 2 1 SW5 R102R103 10K 10K CR0603 CR0603 Re v A SW PUSHBUTTON 4.7mmX3.5mm 2 D16 RED_LED CR0603 R101 220 CR0603 Global Reset or User Defined VCCIO_1 [3] GSRN D15 GREEN_LED CR0603 R100 220 CR0603 GSRN SW0 D14 GREEN_LED CR0603 R99 220 CR0603 16 15 14 13 12 11 10 9 16 1 2 3 4 5 6 7 8 A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 11. Banks 0 and 1 17 A B C D R300 TP_TOE TOE TP_P5 TP_R1 TP_N6 TP_M7 TP_R2 TP_T2 TP_R3 TP_T3 TP_T4 TP_R5 TP_N7 TP_M8 TP_T5 TP_P6 TP_T6 TP_R6 TP_P7 TP_N8 TP_R7 TP_T7 TP_P8 TP_T8 TP_R8 TP_T9 TPP5G TPR1G TPN6G TPM7G TPR2G TPT2G TPR3G TPT3G TPT4G TPR5G TPN7G TPM8G TPT5G TPP6G TPT6G TPR6G TPP7G TPN8G TPR7G TPT7G TPP8G TPT8G TPR8G TPT9G R1250 R131 0 R1370 R139 0 R1450 R151 0 R1570 R159 0 R1650 R171 0 R1770 R179 0 R1850 R191 0 R1970 R199 0 R2050 R211 0 R2170 R219 0 R2250 R231 0 R2370 R239 0 R2450 R251 0 0 A1 A0 A3 A2 A5 A4 A7 A6 A9 A8 A11 A10 A13 A12 A15 A14 A17 A16 A19 A18 A21 A20 A23 A22 A25 A24 [7] [7] VCCIO_4 VCCIO_5 5 C67 10uF SizeC C64 10uF SizeC Optional pull-up, pull-down, and pad resistors. Do not load these resistors. TP_R4 TP_N5 TPR4G TPN5G Test Points have 0.100 inch spacing. VCCIO_5 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 R113 R265 R261 R257 R253 R246 R240 R233 R226 R220 R213 R206 R200 R193 R186 R180 R173 R166 R160 R153 R146 R140 R133 R126 R121 R117 DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS A[25..0] 4 R114 DNS R118 DNS R122 DNS R127 DNS R134 DNS R141 DNS R147 DNS R154 DNS R161 DNS R167 DNS R174 DNS R181 DNS R187 DNS R194 DNS R201 DNS R207 DNS R214 DNS R221 DNS R227 DNS R234 DNS R241 DNS R247 DNS R254 DNS R258 DNS R262 DNS R266 DNS 4 C68 0.1uF CC0402 C65 0.1uF CC0402 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 C69 0.01uF CC0402 C66 0.01uF CC0402 A1 A0 A3 A2 A5 A4 A7 A6 A9 A8 A11 A10 A13 A12 A15 A14 A17 A16 A19 A18 A21 A20 A23 A22 A25 A24 TOE L7 L8 R8 T9 P8 T8 R7 T7 P7 N8 T6 R6 T5 P6 N7 M8 T4 R5 R3 T3 R2 T2 N6 M7 P5 R1 R4 N5 P4 LFXP10E-5F256C VCCIO5_L7 VCCIO5_L8 PB20A PB20B PB19A PB19B PB18A / BDQS18 PB18B PB16A PB17B PB15A PB15B PB14A PB14B PB13A PB13B PB12A PB12B / VREF1_5 PB11A PB11B PB10A / BDQS10 PB10B PB8A PB9B 3 3 (2 OF 5) PB21A PB21B BANK 4 VCCIO4_L9 VCCIO4_L10 PB35A PB35B BDQS34 / PB34A PB34B PB32A PB33B VREF1_4 / PB31A PB31B PB30A PB30B PB29A PB29B PB28A PB28B PB27A PB27B BDQS26 / PB26A VREF0_4 / PB26B PB24A PB25B PB23A PB23B PCLKT4_0 / PB22A PCLKC4_0 / PB22B LFXP10E (fpBGA256) PB7A / VREF0_5 PB7B PB6A PB6B TOE BANK 5 U4B L9 L10 T15 R15 P11 N12 T14 R14 R11 P12 T13 P14 N10 M10 M11 N11 P13 R13 R12 T12 N9 M9 R10 P10 T10 T11 R9 P9 B1 B0 B3 B2 B5 B4 B7 B6 B9 B8 B11 B10 B13 B12 B15 B14 B17 B16 B19 B18 B21 B20 B23 B22 B25 B24 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 2 DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS 2 R267 R263 R259 R255 R248 R242 R235 R228 R222 R215 R208 R202 R195 R188 R182 R175 R168 R162 R155 R148 R142 R135 R128 R123 R119 R115 Da te : Size B Title B[25..0] R268 R264 R260 R256 R249 R243 R236 R229 R223 R216 R209 R203 R196 R189 R183 R176 R169 R163 R156 R149 R143 R136 R129 R124 R120 R116 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 Tuesday, June 17, 2008 Do c ume nt Numbe r <Doc> B1 B0 B3 B2 B5 B4 B7 B6 B9 B8 B11 B10 B13 B12 B15 B14 B17 B16 B19 B18 B21 B20 B23 B22 B25 B24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TP_T15 R250 TP_R15 R252 TP_P11 R238TP_N12 R244 TP_T14 R230 TP_R14 R232 TP_R11 R218 TP_P12 R224 TP_T13 R210 TP_P14 R212 TP_N10 R198TP_M10 R204 TP_M11 R190 TP_N11 R192 TP_P13 R178TP_R13 R184 TP_R12 R170 TP_T12 R172 TP_N9 R158 TP_M9 R164 TP_R10 R150 TP_P10 R152 TP_T10 R138TP_T11 R144 TP_R9 R130 TP_P9 R132 TPT15G TPR15G TPP11G TPN12G TPT14G TPR14G TPR11G TPP12G TPT13G TPP14G TPN10G TPM10G TPM11G TPN11G TPP13G TPR13G TPR12G TPT12G TPN9G TPM9G TPR10G TPP10G TPT10G TPT11G TPR9G TPP9G Test Points have 0.100 inch spacing. 1 She e t 5 of 8 Re v A Optional pull-up, pull-down, and pad resistors. Do not load these resistors. Banks 4 and 5 DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS DNS 1 A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 12. Banks 4 and 5 18 A B C D 5 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND S S S S 5 J17 SMA Connector th_sma 2 3 4 5 J15 SMA Connector th_sma 2 3 4 5 J9 SMA Connector th_sma 2 3 4 5 J7 SMA Connector th_sma 2 3 4 5 1 1 1 1 50 ohm SMA Connectors GND GND GND GND GND GND GND GND S GND GND GND GND GND GND GND GND S S J21 SMA Connector th_sma 2 3 4 5 J19 SMA Connector th_sma 2 3 4 5 J13 SMA Connector th_sma 2 3 4 5 J11 SMA Connector th_sma 2 3 4 5 S 1 1 1 1 R31 DNS R25 DNS R19 DNS R14 DNS [7] [7] VCCIO_6 VCCIO_7 4 TP_4 C20 10uF SizeC C17 10uF SizeC Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms TP_3 4 R33 R29 R27 R23 R21 R18 R16 R12 0 0 0 0 0 0 0 C21 0.1uF CC0402 C18 0.1uF CC0402 C19 0.01uF CC0402 C22 0.01uF CC0402 G6 H6 J1 J2 H3 J3 TP_H3 TP_J3 G4 G5 H1 H2 G3 G2 G1 F3 F2 E3 F4 E1 F1 D1 E2 TP_J1 TP_J2 TP_G4 TP_G5 TP_H1 TP_H2 TP_G1 TP_F3 TP_F2 TP_D1 TP_E2 D2 D3 LFXP10E-5F256C VCCIO7_G6 VCCIO7_H6 PL18A PL18B PL16A / LDQS16 PL16B PL14A / VREF1_7 PL15B PL13A PL13B PL12A / LUM0_PLLT_IN_A PL12B / LUM0_PLLC_IN_A PL11B PL9A PL9B PL8A / LUM0_PLLT_OUT_A PL8B / LUM0_PLLC_OUT_A PL7A / LDQS7 PL7B PL5A / LUM0_PLL_RST PL6B / VREF0_7 LDQS24 / PL24A PL24B PL22A VREF0_6 / PL23B PCLKT6_0 / PL20A PCLKC6_0 / PL20B BANK 6 3 VCCIO6_J6 VCCIO6_K6 PL35A PL35B LLM0_PLLT_FB_A / PL34A LLM0_PLLC_FB_A / PL34B LDQS33 / PL33A PL33B VREF1_6 / PL31A LLM0_PLL_RST / PL32B LLM0_PLLT_OUT_A / PL29A LLM0_PLLC_OUT_A / PL29B PL28A PL26A PL26B LLM0_PLLT_IN_A / PL25A LLM0_PLLC_IN_A / PL25B (1 OF 5) LFXP10E (fpBGA256) PL3A / LUM0_PLLT_FB_A PL3B / LUM0_PLLC_FB_A BANK 7 Short stubs on all diff pairs U4A 0 J6 K6 M3 N3 L5 M6 P1 P2 N1 N2 K4 K5 L4 K3 L3 M1 M2 L1 L2 J4 J5 K1 K2 TP_M3 TP_N3 TP_P1 TP_P2 TP_N1 TP_N2 TP_L4 TP_K3 TP_L3 TP_L1 TP_L2 TP_J4 TP_J5 TP_5 R35 R32 R30 R26 R24 R20 R17 R13 Short stubs on all diff pairs Check Datasheet for Proper Termination Selection 3 0 0 0 0 0 0 0 0 R34 DNS R28 DNS R22 DNS R15 DNS Diff pair, equal length, 50 ohms 2 Diff pair, equal length, 50 ohms 1 1 1 1 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 D ate: 1 1 1 1 1 Tuesday, June 17, 2008 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 GND GND GND GND 2 3 4 5 1 Sheet J18 SMA Connector th_sma S J16 SMA Connector th_sma S J10 SMA Connector th_sma S J8 SMA Connector th_sma S 50 ohm SMA Connectors Banks 6 and 7 J22 SMA Connector th_sma S J20 SMA Connector th_sma S J14 SMA Connector th_sma S J12 SMA Connector th_sma S Si ze D ocument Number Custom <Doc> Title Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms 2 6 of 8 Rev A A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 13. Banks 6 and 7 A B C D 1 2 3 R271 DNI CR0805 R272 0 CR0805 1 FCB D1 MBRS340 SMC + VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V VCC_ADJ VCC_1.2V VCC_3.3V 5 2 4 6 JP13 JP12 2 4 6 2 4 6 JP11 2 4 6 JP10 2 4 6 JP3 2 4 6 JP2 2 4 6 JP1 HEADER_3X2 1 3 5 HEADER_3X2 1 3 5 HEADER_3X2 1 3 5 HEADER_3X2 1 3 5 HEADER_3X2 1 3 5 HEADER_3X2 1 3 5 3 VCCIO_0 VCCIO_6 VCCIO_5 VCCIO_4 VCCIO_3 VCCIO_2 VCCIO_1 C9 10uF SizeC C7 2200pF CC0805 [2] VCCIO_0 VCCM_3.3V PWR_3.3V R270 1 CR0805 R3 10K CR0805 Place Switch next to DC input jack HEADER_3X2 1 3 5 2 C2 0.001uF CC0805 3.3V On/Off Switch 1 On SW1 SW SPDT Off EEVFK1V101P C1 100uF Select only one voltage for each VCCIO VCC_3.3V INTVCC Banana Jack CONN_BLACK S J4 2.5mm Pin, (+) 5.5mm Barrel, (-) VCC_IN Banana Jack 4.5VDC to 28VDC J3 PWR JACK RAPC712 1 EG1257 S 1 2 Vosence Vprog Ith FCB Run/SS EXTVcc 1 2 3 SW VIN ISENSE SOT23-6 4 2 4 6 JP14 TPS64203DVB /EN GND FB U2 LTC1775 7 8 5 4 3 1 VCC_3.3V VCC_ADJ VCC_1.2V FCB C70 0.1uF CC0805 U1 16 Vin CONN_RED SGND 6 PGND 6 5 4 9 J2 1 2 + R1 10 CR0805 CR0805 C6 4.7uF C2012X5ROJ475M D2 1N5819 SOD-123 R4 VCCIO_7 R8 10K CR0805 C12 4.7pF CC0805 DRAIN_ADV 10 .47uF C0603C474K8PACTU CC0805 INTVCC C3 R6 10 CR0805 10 11 12 14 13 15 HEADER_3X2 1 3 5 BG INTVcc Boost SW TG TK 5 6 7 8 S D D D G D D D D4 B320A SMA 1 4 Q5 C16 4.7pF CC0805 2 3 2 1 3 C11 1uF SizeA F2 3A VCC_ADJ J5 CONN_RED D3 MBRS340 SMC VCC_3.3V VCC_ADJ VCC_1.2V 3 JP4 2 2 HEADER1X2 1 JP6 HEADER1X2 1 JP5 HEADER1X2 1 2 L1 DO5022P-103 1 2 10uH 15.24mmX18.54mm TP_1 Output Voltage Adjust R9 200K POT 5.6mmX3.6mm C10 100uF SizeD PWR_ADJ Q2 Si4840DY 8 7 6 5 3 2 1 Q1 Si4840DY 8 7 6 5 R11 100K CR0805 Si5447DC R5 10K CR0805 4 R2 10K CR0805 2 6.2uH 7mmX7mm L2 4 3 2 1 + + C5 470uF 1 2 3 SW VIN ISENSE 2 SOT23-6 TPS64203DVB /EN GND FB U3 6 5 4 2 Use 1.2V for LFXPxxE devices Use 1.8V, 2.5V, or 3.3V for LFXPxxC devices For 1.8V and 2.5V use VCC_ADJ Load only one current sense resistor for VCC_CORE [2] C8 10uF SizeC TP_2 T520D477M004ASE040 VCC_CORE PWR_3.3V C4 470uF PWR_3.3V F1 3A J1 CONN_RED S 1 2 1 R7 10 R10 10K CR0805 C15 4.7pF CC0805 DRAIN_1.2 CR0805 [2,3] VCC_3.3V JB2 PWR_1.2V JB3 C13 100uF SizeD JB4 JB5 C14 1uF SizeA F3 3A JB6 VCC_1.2V J6 CONN_RED JB7 JB9 JB10 JB11 JB12 JB13 JB14 1 Wednesday, September 07, 2005 D ocument Number <D oc> Sheet 7 of 8 Rev A JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JB8 Lattice Semiconductor Corporation Power D ate: Si ze C Q3 Si2323DS SOT23 JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JBLOCK JB1 G Another P-Channel MOSFET option in SOT23 package Si5447DC L3 2 6.2uH 7mmX7mm Title Title D5 B320A SMA 1 Q6 Q4 Si2323DS SOT23 Another P-Channel MOSFET option in SOT23 package G 1 S D S D 4 1 2 S 1 2 1 1 2 1 2 5 6 7 8 S D D D G D D D 4 3 2 1 5 3 1 1 2 S 1 2 1 1 19 2 A B C D Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 14. Power 20 4 3 2 Lattice Semiconductor Corporation D ate: 1 Wednesday, September 07, 2005 D ocument Number <D oc> Mechanical Drawing Sheet 8 of 8 Rev A A A Si ze C B B 5 Title 1 C 2 C 3 D 4 D 5 Lattice Semiconductor LatticeXP Standard Evaluation Board User’s Guide Figure 15. Mechanical Drawing