Power Estimation in
ispXPLD 5000MX Devices
April 2003
Technical Note TN1031
Introduction
The ispXPLD™ 5000MX family is a unique architecture built around the Multi-Function Block (MFB). This block
allows users to implement CPLD logic, dual-port memory (DPRAM), single port-memory (SRAM), pseudo dualport memory (PDPRAM), contents addressable memory (CAM), and FIFO memory.
This technical note explains how to estimate current consumption for the ispXPLD 5000MX devices based on
device utilization and operating frequency. These power estimates should be confirmed with devices operating in
the actual system. It is assumed that the reader has knowledge of the ispXPLD5000MX architecture. Please refer
to the ispXPLD 5000MX family data sheet for more details. The device utilization information in this technical note
can be obtained from the ispLEVER™ design tool.
Power Supply Current Calculations
The ispXPLD 5000MX devices have multiple power pins: VCCJ, VCCO, VCC, and VCCP. This section provides the detail
to calculate current requirements for each of the power supplies.
VCCJ Supply
The JTAG power supply pin (VCCJ) current has two components: background current and I/O related current.
• Background current consumption for the VCCJ pin is minimal.
– At 2.5V, less than 0.5mA
– At 3.6V less than 1.3mA
• I/O related current is dependent on loads connected to the JTAG pins. The JTAG pins are tri-stated and only
have background current consumption when the JTAG port is inactive.
VCCO Supply
The power supply pins for I/O banks (VCCO0, VCCO1, VCCO2, VCCO3) are used to drive the four bank output pins. The
typical unloaded (DC) VCCO current (per I/O bank) is 3mA. The AC current component is dependent on capacitance, output voltage swing, number of outputs, and average output frequency. Each bank supply has associated
current, therefore use the equation for each of the four banks.
VOH and VOL can be found in the sysIO™ sections of the ispXPLD 5000MX Family data sheet.
Parameters:
• IVCCO = Total current of VCCO per I/O bank
• Fn = Output frequency of output (MHz)
• Cn = Capacitive loading of output (when the output pin is connected to a CMOS input, typical load is 5-10pf)
• VOH = Output voltage high of the output (V)
• VOL = Output voltage low of the output (V)
• VCC = Operating voltage of the device (V)
• n = Number of outputs in the bank
• IVCCO_DC = Typical unloaded VCCO current per I/O bank = 3mA
IVCCO = [Σn=1 Cn * (VOH - VOL) * Fn] + IVCCO_DC
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tn1031_01
Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
VCC Supply
The power supply pin for core logic (VCC) is divided into six components for current consumption calculations:
ICC = ICC_DC + IMFB_CPLD + IMFB_ SRAM/PDPRAM/FIFO + IMFB_DPRAM + IMFB_CAM + IPLL_D
Where:
• ICC = Current consumption of VCC power supply (mA)
• ICC_DC = ICC DC component - Current consumption at 0MHz (mA)
• IMFB_CPLD = CPLD (non-memory logic) current consumption (mA)
• IMFB_SRAM/PDPRAM/FIFO = Current consumption for SRAM, PDPRAM, and FIFO (mA)
• IMFB_DPRAM = Current consumption for DPRAM (mA)
• IMFB_CAM = Current consumption for CAM (mA)
• IPLL_D = PLL current consumption of digital VCC power supply (mA)
Current Estimation Equations for VCC Supply
The ispXPLD 5000MX data sheet Power Estimation Coefficient tables specify the coefficient values for each of the
devices in the family. The coefficients are defined as:
•
•
•
•
•
•
•
•
•
•
•
•
•
K0 = Current per MFB input (µA/MHz)
K1 = Current per Product Term (µA/MHz)
K2 = Current per Global Routing Pool (GRP) line driven from MFB (µA/MHz)
K3 = Current per GRP line driven from I/O (µA/MHz)
K4 = Global clock tree current (µA/MHz)
K5 = PLL digital (mA/MHz)
K6 = PLL analog (mA/MHz)
K7 = PLL analog baseline (mA)
DC = Baseline current at 0MHz (mA)
K8 = CAM frequency component (mA/MHz)
K9 = CAM DC component (mA)
K10 = Current per row decoder (µA/MHz)
K11 = Current per column driver (µA/MHz)
ICC_DC (mA)
Use the appropriate value for ispXPLD 5000MC (1.8V power supply) or ispXPLD 5000MV/B (2.5V/3.3V power supply) from the data sheet.
IMFB_CPLD (mA)
= (((K0 * CPLD MFB inputs + K1 * CPLD Logical Product Terms +
K2 * CPLD GRP from MFB + K3 * CPLD GRP from IFB) * AF+ K4) / 1000µA/mA) * FREQ
IMFB-CAM (mA)
= CAM Memory MFBs * ((FREQ * K8) + K9) (CAM operating in typical mode)
IMFB_ SRAM/PDPRAM/FIFO (mA)
= ((WR_ PERCENT * (K1 + WR_ PERCENT * 8 * K0 + K10 + K11) +
RD_ PERCENT * (K1 + 128 * RD_PERCENT * K0 + 8 * OSW_PERCENT * K2))
* SRAM/PDPRAM/FIFO Memory MFBs / 1000µA/mA) * FREQ
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Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
IMFB_ DPRAM (mA)
= (WR_ PERCENT * (2 * K1 + 2 * WR_ PERCENT * 8 * K0 + K10 + K11) +
RD_ PERCENT * (2 * K1 + 2 * 128 * RD_PERCENT * K0 + 8 * OSW_PERCENT * K2))
* DPRAM Memory MFBs / 1000µA/mA) * FREQ
IPLL_D (mA)
= K5 * PLL_FREQ * number of PLLs used
IPPL_D is the PLL digital component of the VCC supply current.
Current Estimation Equations for VCCP Supply
The power supply for PLLs (VCCP pin) has current consumption if the PLL is used. If the PLL is not used, the current
consumption on the VCCP pin is minimal.
• IPLL_A = PLL analog power pin current consumption (VCCP pin)
IPLL_A (mA)
= (K6 * PLL_FREQ + K7) * number of PLLs used
Equation Parameters
Design-Based Parameters
Design-based parameters need to be determined or estimated when using the current calculation equations:
• FREQ = Average frequency of device operation (MHz).
• AF = PLD activity factor as a percentage (12.5% for a 16-bit counter). As a rule of thumb, use 25% if this
can’t be estimated (%).
• PLL_FREQ = Average PLL input frequency (MHz).
• WR_ PERCENT = Writes as a percentage of memory accesses. As a rule of thumb, use 50% if this can’t be
estimated (%).
• RD_PERCENT = Reads as a percentage of memory accesses. As a rule of thumb, use 50% if this can’t be
estimated (%).
• OSW_PERCENT = RAM output switching activity factor (how often the outputs change on the RAM). As a
rule of thumb, use 50% if this can’t be estimated (%).
CPLD Parameters
Device statistics are taken from the ispLEVER design tool report file. If memory is used, the resources associated
with the memory need to be removed to get an accurate CPLD ICC estimate. The Cluster_Table section of the
report file will show which MFBs are used for memory. If a memory needs to use any portion of a MFB, the entire
MFB is used and unused MFB resources are not available for CPLD logic. This equation will help determine
unknown CPLD parameters:
TOTAL report file parameter = CPLD related parameter + Memory related parameter
• CPLD MFB Inputs:
Total MFB Inputs are reported in Device_Resource_Summary. Use this if no memory is used in the design.
In the MFB_Resource_Summary section, the “Fanin” column is equivalent to MFB Inputs. Determine the
CPLD MFB inputs by using the MFB_Resource_Summary, not counting the memory MFB related “Fanin”.
• CPLD Logical Product Terms:
Total Logical Product Terms are reported in Device_Resource_Summary. Use this if no memory is used in
the design. In the MFB_Resource_Summary section, the “Logic PTs” column is equivalent to Logical Product Terms. Determine the CPLD Logical Product Terms by using the MFB_Resource_Summary, not counting the memory MFB related “Logic PTs”.
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Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
• CPLD GRP from MFB: (MFB Feedback to the Global Routing Pool)
Total GRP from MFB is reported in the Device_Resource_Summary. Use this if no memory is used in the
design. Determine the number of CPLD GRPs from MFB by estimating the number of memory inputs from
CPLD logic and subtracting this from the total GRPs from MFB.
• CPLD GRP from IFB: (I/O Feedback to the Global Routing Pool)
Total GRP from IFB is reported in the Device_Resource_Summary. Use this if no memory is used in the
design. Determine the number of CPLD GRPs from IFB by estimating the number of input pins used for
CPLD logic. Alternatively, estimate the number of pins used for memory, and subtract this number from Total
GRPs from IFB.
Note: the Logic_Array_Fanin section gives source information per MFB (pin or macrocell). It can be used to estimate CPLD GRP from MFB (macrocell) and CPLD GRP from IFB (pin), but duplicated signals should be counted
only once and will complicate using this information.
Memory Parameters
Memory usage is reported per macrocell in the report file. In the ispXPLD family, there are 32 macrocells per MFB.
• SRAM/PDPRAM/FIFO Memory MFBs:
Memory MFBs used by SRAM/PDPRAM/FIFO (at 16k bits per MFB). For example, if a 16k x 2 SRAM is
used, with 64 memory macrocells reported, two Memory MFBs are used.
• DPRAM Memory MFBs:
Memory MFBs used by DPRAM (at 8k bits per MFB). For example if a 4k x 4 DPRAM is implemented, two
Memory MFBs will be used (16k / 8k = 2).
• CAM Memory MFBs:
Memory MFBs used by CAM (at 16k bits per MFB).
• Number of PLLs used:
This is reported in the PLL section of the report file if PLLs are used.
Sample ICC vs. Frequency Curves
Figure 1 and Figure 2 show trends of VCC pin current versus frequency for two ispXPLD 5512MX designs.
Figure 1. ICC vs. Frequency of ispXPLD 5512MX Filled with 16-Bit Counters (12.5% Activation Factor)
ispXPLD 5512MX CPLD Icc vs. Frequency
350
300
Icc (mA)
250
200
150
Icc (mA)
100
50
0
0
50
100
150
Frequency (MHz)
4
200
250
Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
Figure 2. ICC vs. Frequency of ispXPLD 5512MX Filled with 14 GLB 1x8 DPRAM at 12.5% Output Switching
Levels
ispXPLD 5512MX DPRAM Icc vs. Frequency
200
180
160
Icc (mA)
140
120
100
80
Icc (mA)
60
40
20
0
0
20
40
60
80
100
Frequency (MHz)
Note: The power calculations as described in this technical note are only estimates. These estimates should be
confirmed with devices operating in the actual system.
VCC Supply Current Calculation Example
As an example calculation, a sample design was fit into an ispXPLD 5512MC device. The design contains one 8k x
2-bit DPRAM, and four 16-bit counters all running at 80MHz. Below is an abbreviated ispLEVER report file from the
design.
Device_Resource_Summary
Total
Available Used Available Utilization
---------------------------------------------------------------------Dedicated Pins
Clock Pins
2
2
0
-->
100
Clock/Clock Enable Pins
2
2
0
-->
100
Enable Pins
2
0
2
-->
0
Reset Pins
1
0
1
-->
0
I/O Pins
253
102
151
-->
40
Logic Macrocells
765
274
491
-->
35
Input Registers
253
0
253
-->
0
Unusable Macrocells
..
0
..
-->
..
MFB Inputs
Logical Product Terms
Occupied MFBs
Occupied Macrocells
Two Function Macrocells
One Function Macrocells
Zero Function Macrocells
Memory Macrocells
Arithmetic Macrocells
Occupied Product Terms
Control Product Terms:
Segment Product Term Enable
MFB Clocks
1088
2560
16
512
..
..
..
..
..
2624
216
611
13
222
1
107
2
64
48
747
872
1949
3
290
..
..
..
..
..
1877
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
19
23
81
43
..
..
..
..
..
28
16
16
0
0
16
16
-->
-->
0
0
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Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
MFB Resets
Macrocell Clocks
Macrocell Clock Enables
Macrocell Enables
Macrocell Resets
Macrocell Presets
16
512
512
512
512
512
9
0
0
0
15
3
7
512
512
512
497
509
-->
-->
-->
-->
-->
-->
56
0
0
0
2
0
Global Routing Pool
765
147
618
-->
19
GRP from IFB
..
34
..
-->
..
(from input signals)
..
34
..
-->
..
(from output signals)
..
0
..
-->
..
(from bidir signals)
..
0
..
-->
..
GRP from MFB
..
113
..
-->
..
---------------------------------------------------------------------<Note> 1 : IFB is I/O feedback.
<Note> 2 : MFB is macrocell feedback.
...
MFB_E_CLUSTER_TABLE
MMMM MMMM MMMM MMMM MMMM MMMM MMMM MMMM GGGGSBBB
I
P P
EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE CCORECCA
/
B T
MMMM MMMM MMMM MMMM MMMM MMMM MMMM MMMM KEEEBKER Type O
Y E
Signal
------------------------------------------------------------------------------M00 U0\RamBaseBlockInst0{RAMB8K_X2_X2}
-------M01 U0\RamBaseBlockInst0{RAMB8K_X2_X2}
-------M02 U0\RamBaseBlockInst0{RAMB8K_X2_X2}
-------...
MFB_F_CLUSTER_TABLE
MMMM MMMM MMMM MMMM MMMM MMMM MMMM MMMM GGGGSBBB
I
P P
EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE CCORECCA
/
B T
MMMM MMMM MMMM MMMM MMMM MMMM MMMM MMMM KEEEBKER Type O
Y E
Signal
------------------------------------------------------------------------------M00 U0\RamBaseBlockInst1{RAMB8K_X2_X2}
-------M01 U0\RamBaseBlockInst1{RAMB8K_X2_X2}
-------M02 U0\RamBaseBlockInst1{RAMB8K_X2_X2}
-------...
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Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
MFB_Resource_Summary
# of PT
I/O
Input Macrocells
Macrocells
Logic clusters
Fanin
Pins
Regs Used Unusable available
PTs
used
-----------------------------------------------------------------------------Maximum
MFB
68
*(1)
16
--32
160
32
==============================================================================
MFB
A
13
10/16
0
22
0
10
46
22
MFB
B
14
6/16
0
16
0
16
28
16
MFB
C
0
0/11
0
0
0
32
0
0
MFB
D
0
0/14
0
0
0
32
0
0
-----------------------------------------------------------------------------MFB
E
35
0/14
0
32
0
0
160
32
MFB
F
35
0/14
0
32
0
0
160
32
MFB
G
32
8/16
0
24
0
8
39
24
MFB
H
22
8/16
0
17
0
15
23
17
-----------------------------------------------------------------------------MFB
I
1
10/16
0
1
0
31
1
1
MFB
J
0
0/16
0
0
0
32
0
0
MFB
K
19
16/18
0
29
0
3
53
29
MFB
L
9
16/18
0
9
0
23
22
9
-----------------------------------------------------------------------------MFB
M
8
11/18
0
4
0
28
6
4
MFB
N
9
3/18
0
6
0
26
7
6
MFB
O
13
10/16
0
22
0
10
46
22
MFB
P
6
4/16
0
8
0
24
20
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-----------------------------------------------------------------------------<Note> 1 : For LC5000MX devices, the number of IOs depends on the MFB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
To calculate ICC for the VCC supply:
ICC = ICC-DC + IMFB_CPLD + IMFB_SRAM/DPRAM/FIFO + IMFB_CAM + IPLL_D
ICC-DC
= 17mA
IMFB_CPLD
= (((K0 * CPLD MFB inputs + K1 * CPLD Logical Product Terms + K2 * CPLD GRP from MFB + K3 * CPLD GRP
from IFB) * AF+ K4) / 1000µA/mA) * FREQ
Looking at the cluster table, MFB E and MFB F are where the DPRAM is placed. Therefore, remove resources
associated with these memory MFBs.
• CPLD MFB inputs: 216 (total MFB inputs) - 70 (MFB E, MFB F Fanin) = 146.
• CPLD Logical Product Terms: 611 (Total Logical Product Terms) - 320 (MFB E, MFB F Logic PTs) = 291.
• CPLD GRP from MFB: 113 (Total GRP from MFB). Memory is connected to external pins. Assume 0 GRP
from MFB associated with memory. Use CPLD GRP from MFB = 113.
• CPLD GRP from IFB: 34 (Total GRP from IFB). Memory is connected to pins, 0 input pins used for counters
(don’t count clock and reset). Use CPLD GRP from IFB = 0.
• AF = 12.5% (for 16-bit counters)
• FREQ = 80MHz
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Power Estimation in
ispXPLD 5000MX Devices
Lattice Semiconductor
IMFB-CPLD
= (((2.2µA/MHz * 146 + 8.4µA/MHz * 291+ 9.4µA/MHz * 113 + 27.6µA/MHz * 0) * .125 + 151µA/MHz) 1000µA/mA)
* 80MHz/
= 50mA
IMFB_CAM
= 0 (CAM Memory MFBs = 0)
IMFB_ SRAM/PDPRAM/FIFO
= 0 (Memory MFBs = 0)
IMFB_ DPRAM
= ((WR_ PERCENT * (2 * K1 + 2 * WR_ PERCENT * 8 * K0 + K10 + K11) +
RD_ PERCENT * (2 * K1 + 2 * 128 * RD_PERCENT * K0 + 8 * OSW_PERCENT * K2))
* DPRAM Memory MFBs / 1000µA/mA) * FREQ
Where:
• WR_PERCENT = 50%
• RD_ PERCENT = 50%
• OSW_PERCENT = 50%
• DPRAM Memory MFBs = 2
• FREQ = 80MHz
IMFB_ DPRAM
= (.5 * (2 * 8.4µA/MHz + 2 * .5 * 8 * 2.2µA/MHz + 4.4µA/MHz + 2.9µA/MHz) + .5 * (2 * 8.4µA/MHz + 2 * 128 * .5 *
2.2µA/MHz + 8 * .5 * 9.4µA/MHz)) * 2 / 1000µA/mA) * 80MHz
= 30mA
IPLL_D
= 0 (number of PLLs used = 0)
ICC = ICC-DC + IMFB_CPLD + IMFB_SRAM/DPRAM/FIFO + IMFB_CAM + IPLL_D
ICC = 17mA + 50mA + 0 + 30mA + 0 + 0
= 97mA
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