IN-SYSTEM PROGRAMMABLE CLOCK DISTRIBUTION DEVICES ispClock5300S Integrates Zero Delay Buffers and Fan-out Buffers and Provides Multi-voltage Logic Interface Key Features and Benefits Each Output Programmable as FOB or ZDB from the Reference Clock • Single chip replaces a variety of ZDB and FOB ICs • Single chip meets most clock distribution needs Imagine using a single, low-cost, programmable clock distribution device as a zero delay buffer (ZDB) or a non-zero delay fan-out buffer (FOB), or both, in the same package instead of selecting different clock ICs from multiple vendors! That is what you get with Lattice’s revolutionary ispClock™5300S family. Programmable Output Interface Standard • Integrates logic translation buffers • Used across multiple clock networks Precision Programmable Skew • Minimizes serpentine traces to reduce circuit board area • Compensates for unforeseen changes to set-up and hold times The ispClock5300S architecture is built around a high performance PLL with programmable input, feedback, and output interface standards. Each output’s skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. Additionally, each output can be individually configured for fan-out buffer or zerodelay buffer operation. The programmable output termination per output feature enables interfacing of the ispClock5300S device to any clock network with standard trace impedance. Programmable Output Termination • Eliminates external termination resistors to reduce circuit board area Programmable Single-ended or Differential Clock Reference Input • Single chip replaces differential/single-ended input FOB and ZDB ICs Four Modes of Operation V3 Dual Non-Zero Delay Buffer V1 PLL V2 Output Routing Matrix V3 Five Devices with 4, 8, 12, 16 or 20 Outputs • Covers a wide clock distribution application range Single Ended Clock Input V1 V2 V3 Output Routing Matrix Single Ended Clock Input Output Routing Matrix Output Routing Matrix Single Ended Clock Input ispClock 5300S JTAG Programming and Boundary Scan • Increases test coverage and reduces manufacturing time Output Routing Matrix Output Routing Matrix External Feedback Single Ended Clock Input Single ispClock Ended 5300S Clock Input Output Routing Matrix V2 Single ispClock Ended 5300S Clock Input Output Routing Matrix PLL V1 Output Routing Matrix Single Ended/ ispClock 5300S Diff. Clock Input High Performance PLL • Low jitter (<12ps) • Low skew (<100ps) Non-Zero Delay Buffer with & w/o Divider Mode Zero Delay & Non-Zero Delay Buffer Zero Delay Buffer External Feedback ispClock5300S Block Diagram Programmable Clock Input • Differential/ Single-Ended • LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL • Programmable Termination REFA/REFP PLL Core REFB/REFN 0 1 Phase/ Frequency Detector 1 Filter VCO REFSEL FBK Programmable Feedback Input LVTTL, LVCMOS, SSTL, HSTL Programmable Termination JTAG Programming & Boundary Scan PLL Bypass Path for Fan-Out Buffer Implementation 0 Skew Control Output Dividers ÷ V0 5-bit ÷ V1 5-bit ÷ V2 5-bit Output Drivers Output Routing Matrix Universal Fan-Out Buffer, Single Ended LVTTL, LVCMOS, SSTL, HSTL, Slew Rate LATTICESEMI.COM Design Made Simple with PAC-Designer Software Lattice’s PAC-Designer software, a PC-based software tool, provides simple and intuitive pull-down menus for configuring all programmable features of the device. In addition, design utilities ® like the Skew Editor, Frequency Calculator and Frequency Synthesizer enable easy configuration of various counters and other options. Configurations can be downloaded into ispClock devices from a PC parallel port. 1. Set Reference and Feedback Clock Interface. 5. Download and Verify Design with Evaluation Board. 2. Set Output Clock Properties. 4. Set Individual Clock Output Skews. 3. Set Input and Output Clock Frequencies. ispClock5300S Attributes Application Diagram ispClock5300S Device Feature Outputs I/O Frequency Ranges 5304S 5308S 5312S 5316S 5320S 4 8 12 16 20 8 to 267MHz (input), 5 to 267MHz (output) VCO Operation 160 to 400 MHz Spread Spectrum Compatibility Programmable Input Types LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential SSTL, Differential HSTL Programmable Output and Feedback Interface Types LVTTL, LVCMOS, SSTL, HSTL 12ps Maximum Static Phase Offset -40ps to 100ps Package f1 LVCMOS 3.3V f1 FOB f1 LVCMOS 3.3V 100ps Maximum Period Jitter (RMS) Programmable Termination Offers JTAG bounday scan feature External/Internal Maximum Output Skew Programmable Skew Integrates fan-out buffers, zero-delay buffers and termination resistors No trace snaking necessary Yes PLL Feedback The ispClock5300S is a PLD that can be used as a standard clock distribution IC across all designs. f2 LVCMOS 1.8V 156ps to 5ns 40 to 70W & 20W Settings 48 TQFP f2 ZDB f2 LVCMOS 1.8V 64 TQFP f1 LVCMOS 3.3V f1 Applications Support 1-800-LATTICE (528-8423) 503-268-8001 [email protected] f2 ispClock 5300S f1 LVCMOS 3.3V f2 LVCMOS 1.8V f2 LVCMOS 1.8V Copyright © 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., Lattice (design), ispClock, ispPAC, PAC-Designer and ispDOWNLOAD are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. October 2012 Order #: I0193A LATTICESEMI.COM