ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER FEATURES GENERAL DESCRIPTION • Fully integrated PLL The ICS87951I is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Cock Generator. The CS87951I has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. • Nine single ended 3.3V LVCMOS/LVTTL outputs • Selectable single ended CLK0 or differential CLK1, nCLK1 inputs • The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels • CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency range: 25MHz to 180MHz • VCO range: 200MHz to 480MHz • External feedback for ”zero delay” clock regeneration • Cycle-to-cycle jitter: ±100ps (typical) • Output skew: 375ps (maximum) • PLL reference zero delay: 350ps window (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages PIN ASSIGNMENT GND QB VDDO QA GND CLK0 PLL_SEL CLK_SEL 32 31 30 29 28 27 26 25 VDDA 1 24 EXT_FB 2 23 VDDO DIV_SELA 3 22 QC1 21 GND 20 QD0 QC0 DIV_SELB 4 DIV_SELC 5 DIV_SELD 6 19 VDDO GND 7 18 QD1 CLK1 8 17 GND ICS87951I 9 10 11 12 13 14 15 16 QD2 VDDO QD3 GND QD4 VDDO MR/nOE nCLK1 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View 87951AYI www.idt.com 1 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER BLOCK DIAGRAM DIV_SELA Internal Pulldown PLL_SEL Internal Pulldown CLK0 Internal Pulldown CLK_SEL nCLK1 CLK1 Internal Pulldown Internal Pulldown/ Pullup 1 0 ÷2 PHASE DETECTOR VCO 200-480MHz 0 1 0 QA ÷4 ÷8 1 0 LPF QB 1 EXT_FB Internal Pullup DIV_SELB Internal Pulldown 0 QC0 1 QC1 DIV_SELC Internal Pulldown MR/nOE Internal Pulldown POWER-ON RESET QD0 0 QD1 1 QD2 QD3 DIV_SELD Internal Pulldown QD4 87951AYI www.idt.com 2 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power 2 EXT_FB Input Pullup 3 DIV_SELA Input Pulldown 4 DIV_SELB Input Pulldown 5 DIV_SELC Input Pulldown 6 DIV_SELD Input Pulldown 7, 13, 17, 21, 25, 29 GND Power 8 CLK1 Input 9 nCLK1 Input Pulldown Inver ting differential clock input. MR/nOE Input Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated Pulldown (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 10 Type 11, 15, 19, 23, 27 12, 14, 16, 18, 20 VDDO Power QD4, QD3, QD2, QD1, QD0 Output 22, 24 QC1, QC0 Output 26 QB Output 28 QA Output 30 CLK0 Input 31 PLL_SEL Input 32 CLK_SEL Input Description Analog supply pin. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Power supply ground. Pullup Non-inver ting differential clock input. Output supply pins. Bank D clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank B clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL phase detector reference clock input. Selects between the PLL and the reference clock as the input to the Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance 87951AYI Test Conditions Minimum Typical VDDA, VDDO = 3.47V Maximum 4 pF 25 pF 51 KΩ 51 5 www.idt.com 3 Units 7 KΩ 12 Ω REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Inputs Outputs MR/nOE QA QB QC0, QC1 QD0:QD4 1 HiZ HiZ HiZ HiZ 0 Enabled Enabled Enabled Enabled TABLE 3B. OPERATING MODE FUNCTION TABLE Inputs PLL_SEL Operating Mode 0 Bypass 1 PLL TABLE 3C. PLL INPUT FUNCTION TABLE Inputs CLK_SEL PLL Input 0 CLK1, nCLK1 1 CLK0 TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE Inputs Outputs DIV_SELA DIV_SELB DIV_SELC DIV_SELD QA QB QCx QDx 0 0 0 0 VCO/2 VCO/4 VCO/4 VCO/4 0 0 0 1 VCO/2 VCO/4 VCO/4 VCO/8 87951AYI 0 0 1 0 VCO/2 VCO/4 VCO/8 VCO/4 0 0 1 1 VCO/2 VCO/4 VCO/8 VCO/8 0 1 0 0 VCO/2 VCO/8 VCO/4 VCO/4 0 1 0 1 VCO/2 VCO/8 VCO/4 VCO/8 0 1 1 0 VCO/2 VCO/8 VCO/8 VCO/4 0 1 1 1 VCO/2 VCO/8 VCO/8 VCO/8 1 0 0 0 VCO/4 VCO/4 VCO/4 VCO/4 1 0 0 1 VCO/4 VCO/4 VCO/4 VCO/8 1 0 1 0 VCO/4 VCO/4 VCO/8 VCO/4 1 0 1 1 VCO/4 VCO/4 VCO/8 VCO/8 1 1 0 0 VCO/4 VCO/8 VCO/4 VCO/4 1 1 0 1 VCO/4 VCO/8 VCO/4 VCO/8 1 1 1 0 VCO/4 VCO/8 VCO/8 VCO/4 1 1 1 1 VCO/4 VCO/8 VCO/8 VCO/8 www.idt.com 4 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDDA + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.1°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDDO Power Supply Current 115 mA IDDA Analog Supply Current 20 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 1.3 V -0.3 0.8 V 300 1000 mV GND + 0.5 VDD - 0.85 V All VDD pins TABLE 4B. DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH VIL Input High Voltage Input Low Voltage Test Conditions CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE VCMR Peak-to-Peak CLK1, nCLK1 Input Voltage Common Mode Input Voltage; NOTE 1, 2 VOH Output High Voltage IOH = -40mA VOL Output Low Voltage IOL = 40mA VPP Minimum Typical 2.4 IIN Input Current NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V. 87951AYI www.idt.com 5 V 0.5 V ±120 µA REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fREF Input Reference Frequency Test Conditions Minimum Typical Maximum Units 100 MHz TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units QA ÷2 180 MHz QA/QB ÷4 120 MHz QB ÷8 60 MHz fVCO PLL VCO Lock Range 200 480 MHz -185 15 165 ps t(Ø) CLK0 Static Phase Offset; C LK1, NOTE 1,3 nCLK1 -445 -265 -95 ps Same Frequencies 375 ps Different Frequencies QAfMAX < 150MHz QAfMAX > 150MHz 500 750 ps ps ps 10 mS 1.0 ns tsk(o) Output Skew; NOTE 2, 3 fREF = 50MHz, Feedback = VCO/8 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 3 tLOCK PLL Lock Time; NOTE 3 tR Output Rise Time 0.8 to 2V tF Output Fall Time 0.8 to 2V tPW Output Pulse Width tPZL tPLZ, tPHZ ±100 0.1 0.1 1.0 ns tcycle/2 - 1000 tcycle/2 + 1000 ps Output Enable Time 6 ns Output Disable Time 7 ns All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 87951AYI www.idt.com 6 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% V DD SCOPE VDDA, VDDO nCLK1 Qx LVCMOS V V Cross Points PP CMR CLK1 GND GND -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V V DDO V DDO 2 ➤ tcycle n DDO 2 tcycle n+1 ➤ V DDO 2 ➤ Qx 2 ➤ V DDO Qy t jit(cc) = tcycle n –tcycle n+1 2 t sk(o) 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT SKEW Clock Outputs nCLK1 VOH CLK0, CLK1 VOL 2V 2V 0.8V 0.8V tR VOH VDDO tF 2 EXT_FB VOL ➤ t (Ø) OUTPUT RISE/FALL TIME QA, QB, QCx, QDx tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter VDDO VDDO 2 2 t (Ø) mean = Static Phase Offset VDDO (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) 2 t PW t PERIOD odc = t PW t PERIOD PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 87951AYI ➤ QA, QB, QCx, QDx DIFFERENTIAL INPUT LEVEL www.idt.com 7 AND STATIC PHASE OFFSET REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 87951AYI 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING www.idt.com 8 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK1 /nCLK1 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK1/nCLK1 input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 87951AYI www.idt.com 9 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87951I is: 2674 87951AYI www.idt.com 10 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 87951AYI www.idt.com 11 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 87951AYI ICS87951AYI 32 Lead LQFP tube -40°C to 85°C 87951AYIT ICS87951AYI 32 Lead LQFP 1000 tape & reel -40°C to 85°C 87951AYILF ICS87951AYIL 32 Lead "Lead-Free" LQFP tube -40°C to 85°C 87951AYILFT ICS87951AYIL 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 87951AYI www.idt.com 12 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER Rev Table T1 T2 B 5 T9 C 87951AYI Page 3 3 T9 8 9 1 9 12 12 14 REVISION HISTORY SHEET Description of Change Pin Description Table - revised MR/nOE description. Pin Characteristics Table - changed CIN 4pf max. to 4pf typical. Added ROUT row. DC Characteristics - changed VIH CLK0 from 3.6V max to VDD + 0.3V and added VIL CLK0 row. Updated Single Ended Signal Driving Differential Input diagram. Added CLK/nCLK Input Interface section. Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking, and note. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. www.idt.com 13 Date 7/10/03 11/23/05 7/17/10 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 [email protected] © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 87951AYI www.idt.com 14 REV. C JULY 17, 2010