RENESAS R1EX25002ASA00A

R1EX25002ASA00A/R1EX25004ASA00A
R1EX25002ATA00A/R1EX25004ATA00A
Serial Peripheral Interface
2k EEPROM (256-word × 8-bit)
4k EEPROM (512-word × 8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0357-0001
Preliminary
Rev.0.01
Jan.25.2008
Description
R1EX25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 16-byte
page programming function to make it’s write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phones,
camcorders, audio equipments. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial Peripheral Interface compatible (SPI bus)
 SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
 Standby: 2µA (max)
 Active (Read): 2 mA (max)
 Active (Write): 2.5 mA (max)
• Automatic page write: 16-byte/page
• Write cycle time: 5 ms
• Endurance: 106 Erase/Write Cycles
• Data retention: 10 Years
• Small size packages: SOP-8pin, TSSOP-8pin
• Shipping tape and reel
 TSSOP-8pin: 3,000 IC/reel
 SOP-8pin
: 2,500 IC/reel
• Temperature range: −40 to +85 °C
• Lead free product.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications
REJ03C0357-0001 Rev.0.01 Jan.25.2008
page 1 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Ordering Information
Type No.
R1EX25002ASA00A
Internal organization Operating voltage
Frequency
2-kbit (256 × 8-bit)
1.8 V to 5.5 V
5 MHz
(2.5 V to 5.5 V)
R1EX25004ASA00A
4-kbit (512 × 8-bit)
R1EX25002ATA00A
2-kbit (256 × 8-bit)
R1EX25004ATA00A
4-kbit (512 × 8-bit)
3 MHz
(1.8 V to 5.5V)
1.8 V to 5.5 V
5 MHz
(2.5 V to 5.5 V)
3 MHz
(1.8 V to 5.5 V)
Pin Arrangement
8-pin SOP/TSSOP
S
1
8
VCC
Q
2
7
HOLD
W
3
6
C
VSS
4
5
D
(Top view)
Pin Description
C
Pin name
Function
Serial clock
D
Q
S
W
HOLD
VCC
VSS
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 2 of 20
Package
150mil 8-pin plastic SOP
PRSP0008DF-B
(FP-8DBV)
Lead free
8-pin plastic TSSOP
PTSP0008JC-B
(TTP-8DAV)
Lead free
R1EX25002Axx00A/R1EX25004Axx00A
Block Diagram
High voltage generator
C
HOLD
D
Y
decoder
W
Control logic
S
Address generator
VSS
X
decoder
VCC
Memory array
Y-select & Sense amp.
Serial-parallel converter
Q
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage relative to VSS
VCC
Input voltage relative to VSS
VIN
1
Operating temperature range*
Topr
Storage temperature range
Tstg
Notes: 1. Including electrical characteristics and data retention.
2. VIN (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
Value
−0.6 to + 7.0
−0.5*2 to +7.0*3
−40 to +85
−55 to +125
Unit
V
V
°C
°C
DC Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature range
Symbol
VCC
VSS
VIH
VIL
Topr
Notes: 1. VIN (min): −1.0 V for pulse width ≤ 50 ns.
2. VIN (max): VCC + 1.0 V for pulse width ≤ 50 ns.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 3 of 20
Min
1.8
0
VCC × 0.7
−0.3*1
−40
Typ

0



Max
5.5
0
VCC + 0.5*2
VCC × 0.3
+85
Unit
V
V
V
V
°C
R1EX25002Axx00A/R1EX25004Axx00A
DC Characteristics
Parameter
Input leakage current
Symbol
ILI
Min

Max
2
Unit
µA
ILO

2
µA
VCC = 5.5 V, VOUT = 0 to 5.5 V
(Q)
Standby
ISB

2
µA
VIN = VSS or VCC,
VCC = 5.5 V
Active
ICC1

2
mA
ICC2

2.5
mA
VOL1
VOL2
VOH1
VOH2


VCC × 0.8
VCC × 0.8
0.4
0.4


V
V
V
V
VCC = 5.5 V, Read at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
Q = OPEN
VCC = 5.5 V, Write at 5 MHz
VIN = VCC × 0.1/VCC × 0.9
VCC = 5.5 V, IOL = 2 mA
VCC = 2.5 V, IOL = 1.5 mA
VCC = 5.5 V, IOL = −2 mA
VCC = 2.5 V, IOL = −0.4 mA
Output leakage current
VCC current
Output voltage
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 4 of 20
Test conditions
VCC = 5.5 V, VIN = 0 to 5.5 V
(S, D, C, HOLD, W)
R1EX25002Axx00A/R1EX25004Axx00A
AC Characteristics
Test Conditions
• Input pules levels:
 VIL = VCC × 0.2
 VIH = VCC × 0.8
• Input rise and fall time: ≤ 10 ns
• Input and output timing reference levels: VCC × 0.3, VCC × 0.7
• Output reference levels: VCC × 0.5
• Output load: 100 pF
(Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH

tCLH
tCLL
Min

90
90
90
90
90
90
90
Max
5







Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Notes
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
tRC
tFC
tDSU
tDH






20
30
70
40
60
60
1
1






µs
µs
ns
ns
ns
ns
ns
ns
2
2
100
70

50
50
50
100
5

ns
ns
ns
ns
ns
ns
ns
ms
cycles
2
Output disable time
tSHQZ
tDIS

Clock low to output valid
tCLQV
tV

Output hold time
tCLQX
tHO
0
Output rise time
tQLQH
tRO

Output fall time
tQHQL
tFO

HOLD high to output low-Z
tHHQX
tLZ

HOLD low to output high-Z
tHLQZ
tHZ

Write time
tW
tWC

Erase / Write Endurance


106
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Value guaranteed by characterization, not 100% tested in products.
6
10 cycles(Ta = 25°C)
105cycles(Ta = 85°C)
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 5 of 20
1
1
2
2
2
2
3
R1EX25002Axx00A/R1EX25004Axx00A
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
Output disable time
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH

tCLH
tCLL
tRC
tFC
tDSU
tDH




Min

100
100
150
100
100
150
150


30
50
140
90
120
120
Max
3







1
1






Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
Notes
tSHQZ
tDIS

200
ns
2
120

100
100
100
100
5

ns
ns
ns
ns
ns
ns
ms
cycles
2
2
2
2
Clock low to output valid
tCLQV
tV

Output hold time
tCLQX
tHO
0
Output rise time
tQLQH
tRO

Output fall time
tQHQL
tFO

HOLD high to output low-Z
tHHQX
tLZ

HOLD low to output high-Z
tHLQZ
tHZ

Write time
tW
tWC

Erase / Write Endurance


106
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Value guaranteed by characterization, not 100% tested in products.
6
10 cycles (Ta = 25°C)
105cycles (Ta = 85°C)
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 6 of 20
1
1
2
2
3
R1EX25002Axx00A/R1EX25004Axx00A
Timing Waveforms
Serial Input Timing
tSHSL
S
tCHSL
tCHSH
tSHCH
tSLCH
C
tDVCH
D
tCHCL
tCLCH
tCHDX
MSB IN
LSB IN
High Impedance
Q
Hold Timing
S
tHHCH
tHLCH
tCHHL
C
tCHHH
D
tHLQZ
tHHQX
Q
HOLD
Output Timing
S
tSHQZ
tCH
C
tCL
D
ADDR
LSB IN
tCLQV
tCLQX
tCLQX
Q
tCLQV
LSB OUT
tQLQH
tQHQL
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 7 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Pin Function
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be
written. Values are latched on the rising edge of serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input
(D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of
serial clock (C).
Chip select (S)
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an
internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S) low enables the
device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the
start of any instruction.
Hold (HOLD)
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care. To start the hold condition, the device must be selected, with chip select (S) driven low.
Write protect (W)
This input signal is used to protect the memory against write instructions. When write protect (W) is held low, write
instructions (WRSR, WRITE) are ignored. No action on this signal can interrupt a write cycle that has already started.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 8 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
b7
1
b0
1
1
1
BP1
BP0
WEL
WIP
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be protected
against Write instructions.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent
(one not contained in the following table), the device automatically deselects itself.
Instruction Set
Instruction
Description
WREN
Write Enable
WRDI
Write Disable
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read from Memory Array
WRITE
Write to Memory Array
Notes: 1. “×” is Don’t care.
2. “A” is A8 address on the R1EX25004A, and Don’t care on the R1EX25002A.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 9 of 20
Instruction Format
0000 ×110
0000 ×100
0000 ×101
0000 ×001
0000 A011
0000 A010
R1EX25002Axx00A/R1EX25004Axx00A
Write Enable (WREN):
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is
to send a Write Enable instruction to the device. As shown in the following figure, to send this instruction to the device,
chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then
enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high.
Write Enable (WREN) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
1
2
3
4
5
VIH
VIL
Instruction
VIH
VIL
Q
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 10 of 20
High-Z
6
7
R1EX25002Axx00A/R1EX25004Axx00A
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown
in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction
byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The
Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:





Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
WRITE protect (W) is driven low
Write Disable (WRDI) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
1
2
3
4
5
VIH
VIL
Instruction
VIH
VIL
Q
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 11 of 20
High-Z
6
7
R1EX25002Axx00A/R1EX25004Axx00A
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
VIH
VIL
Status Register Out
Q
High-Z
7
6
5
4
3
2
1
0
7
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the
internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Status
Register Format table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can
be written provided that the Hardware Protected mode has not been set.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 12 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch(WEL). The instruction sequence is
shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of
the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of
serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the
self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, Write Enable Latch(WEL) is reset. The Write Status Register (WRSR) instruction allows the user
to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,
as defined in the Status Register Format table.
The contents of Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of
the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the
execution of Write Status Register (WRSR) instruction.
Write Status Register (WRSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
Status Register In
D
VIH
VIL
Q
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 13 of 20
7
MSB
High-Z
6
5
4
3
2
1
0
R1EX25002Axx00A/R1EX25004Axx00A
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q). The most
significant address (A8) should be sent as fifth bit in the instruction byte.
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
S
W
C
D
VIH
VIL
VIH
VIL
VIH
VIL
VIH
0
1
2
3
4
5
6
7
8
9 10
12 13 14 15 16 17 18 19 20 21 22 23
8-Bit Address
Instruction
A8
A7
A6 A5
A3 A2 A1
A0
VIL
Data Out 1
Q
Note:
High-Z
7
6
5
4
3
Data Out 2
2
1
0
7
1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t
care.
Address Range Bits
Device
Address bits
A8 to A0
Note: 1. A8 is don’t care on the R1EX25002A.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
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R1EX25004A
R1EX25002A
A7 to A0
R1EX25002Axx00A/R1EX25004Axx00A
Write to Memory Array (WRITE):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the
following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is
being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in AC
Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the input data is
shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be
written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the
number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the
beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these
device is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:




If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
If a Write cycle is already in progress
If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
If Write Protect (W) is low
Byte Write (WRITE) Sequence (1 Byte)
S
W
C
VIH
VIL
VIH
VIL
VIH
0
1
2
3
4
5
6
7
8
VIH
12 13 14 15 16 17 18 19 20 21 22 23
8-Bit Address
A8
A7
A6 A5
A3
A2
Data Byte 1
A1
A0
7
6
5
4
3
2
1
0
VIL
Q
Note:
10
VIL
Instruction
D
9
High-Z
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bit is
don’t care.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 15 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Byte Write (WRITE) Sequence (Page)
S
W
C
VIH
VIL
VIH
VIL
0
VIH
1
2
3
4
5
6
7
8
9
VIH
8-Bit Address
A8
A7 A6 A5
W
C
A1
A0
7
6
5
4
3
2
1
1
0
0
VIH
VIL
VIH
VIL
VIH
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
VIL
7
6
5
4
3
2
Q
Note:
A2
High-Z
Data Byte 2
D
A3
Data Byte 1
VIL
Q
S
12 13 14 15 16 17 18 19 20 21 22 23
VIL
Instruction
D
10
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
High-Z
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bit is
don’t care.
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 16 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Data Protect
The Block Protect bits (BP1, BP0) define the area of memory that is protected against the execution of write cycle, as
summarized in the following table.
When Write Protect (W) is driven low, write to memory array (WRITE) and write status register (WRSR) are disabled,
and WEL bit is reset.
Write Protected Block Size
0
0
1
1
Status register bits
BP1
BP0
0
1
0
1
Protected blocks
None
Upper quarter
Upper half
Whole memory
Array addresses protected
R1EX25004A
R1EX25002A
None
None
180h − 1FFh
C0h − FFh
100h − 1FFh
80h − FFh
000h − 1FFh
00h − FFh
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking
sequence.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care.
To enter the hold condition, the device must be selected, with chip select (S) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in
the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to
reset any processes that had been in progress.
The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being
low (as shown in the following figure).
The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being
low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock
(C) being low.
Hold Condition Activation
HOLD status
C
HOLD
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 17 of 20
HOLD status
R1EX25002Axx00A/R1EX25004Axx00A
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn
the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power
on reset function. Be careful of the notices described below in order for the power on reset function to operate
correctly.
• S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off may
cause the trigger for the unintentional programming.
• VCC should be turned on/off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the unintentional
programming mode.
• VCC turn on speed should be slower than 10 µs/V.
• When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after waiting
write cycle time (tW).
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 18 of 20
R1EX25002Axx00A/R1EX25004Axx00A
Package Dimensions
R1EX25002ASA00A/R1EX25004ASA00A (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code
P-SOP8-3.9x4.89-1.27
RENESAS Code
PRSP0008DF-B
*1
Previous Code
FP-8DBV
D
8
MASS[Typ.]
0.08g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
5
*2
c
E
HE
bp
Reference
Symbol
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
4.89
5.15
E
3.90
A2
1
Z
4
e
*3
A1
bp
x
M
0.14
L1
0.35
0.40
0.45
0.15
0.20
0.25
6.02
6.20
b1
c
A
c
A1
θ
L
y
Detail F
0.254
1.73
bp
1
θ
0°
HE
5.84
8°
1.27
e
x
0.25
y
0.10
Z
0.69
0.406
L
L
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 19 of 20
0.102
A
1
0.60
1.06
0.889
R1EX25002Axx00A/R1EX25004Axx00A
R1EX25002ATA00A/R1EX25004ATA00A (PTSP0008JC-B / Previous Code: TTP-8DAV)
JEITA Package Code
P-TSSOP8-4.4x3-0.65
RENESAS Code
PTSP0008JC-B
*1
D
8
MASS[Typ.]
0.034g
Previous Code
TTP-8DAV
F
5
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c
HE
*2
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
3.00
3.30
E
4.40
A2
Index mark
A1
0.03
0.07
0.15
0.20
0.25
0.10
0.15
0.20
6.40
6.60
A
L1
0.10
1.10
bp
b1
1
4
e
c
*3
bp
x
c
M
θ
A1
A
Z
L
Detail F
y
θ
0°
HE
6.20
e
8°
0.65
0.13
x
y
0.10
Z
0.805
L
L
REJ03C0357-0001 Rev. 0.01 Jan.25.2008
page 20 of 20
1
0.40
1
0.50
1.00
0.60
Revision History
Rev.
0.01
Date
Jan.25, 2008
R1EX25002Axx00A/R1EX25004Axx00A
Data Sheet
Contents of Modification
Page

Initial issue
Description
Sales Strategic Planning Div.
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Notes:
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