To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. [Preliminary] This product is under development and its specification might be changed without any notice. R1LV0816ASD -5SI, 7SI 8Mb Advanced LPSRAM (512k word x 16bit / 1M word x 8bit) REJ03C0397-0001 Preliminary Rev.0.01 2009.12.08 Description The R1LV0816ASD is a family of low voltage 8-Mbit static RAMs organized as 524,288-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LV0816ASD is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1LV0816ASD is packaged in a 52pin thin small outline mount device [µTSOP/ 10.79mm x 10.49 mm with the pin-pitch of 0.40mm]. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features Single 2.4-3.6V power supply Small stand-by current: 1.2 A (Vcc=3.0V, typ.) No clocks, No refresh All inputs and outputs are TTL compatible Easy memory expansion byCS2, CS1#, LB# and UB# Common Data I/O Three-state outputs: OR-tie capability OE# prevents data contention in the I/O bus Operation temperature: -40 ~ +85°C Ordering information Type No. R1LV0816ASD-5SI R1LV0816ASD-7SI Power supply Access time 2.7V to 3.6V 55 ns 2.4V to 2.7V 2.4V to 3.6V 70 ns 70 ns REJ03C0397-0001 Rev.0.01 Page 1 of 16 2009.12.08 Temperature Range Package -40 ~ +85°C 350 mil 52-pin plastic μ-TSOP (II) (normal-bend type) (52PTG) R1LV0816ASD –5SI, 7SI Preliminary Pin Arrangement REJ03C0397-0001 Rev.0.01 Page 2 of 16 A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 Vss A11 5 48 LB# A10 6 47 DQ15/A-1 A9 7 46 DQ7 A8 8 45 DQ14 NC 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 NC 17 36 DQ10 A18 18 35 DQ2 A17 19 34 DQ9 A7 20 33 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 Vss A2 25 28 NC A1 26 27 A0 2009.12.08 52-pin TSOP (II) R1LV0816ASD –5SI, 7SI Preliminary Pin Description Pin name Vcc Vss A0 to A18 A-1 to A18 DQ0 to DQ15 CS1# CS2 WE# OE# LB# UB# BYTE# NC Function Power supply Ground Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte enable Upper byte enable Byte control mode enable Non connection REJ03C0397-0001 Rev.0.01 Page 3 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Block Diagram A0 A1 MEMORY ARRAY ADDRESS ROW 512k-word x16-bit BUFFER DECODER or DQ0 1M-word x8-bit DQ1 A18 DQ BUFFER DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 COLUMN DECODER DQ DQ9 BUFFER CLOCK CS2 GENERATOR DQ15 / A -1 CS1# LB# X8 / x16 UB# CONTROL BYTE# WE# OE# REJ03C0397-0001 Rev.0.01 Page 4 of 16 2009.12.08 Vcc Vss R1LV0816ASD –5SI, 7SI Preliminary Operation Table CS1# CS2 BYTE# LB# UB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand-by X L X X X X X High-Z High-Z High-Z Stand-by X X H H H X X High-Z High-Z High-Z Stand-by L H H L H L X Din High-Z High-Z Write in lower byte L H H L H H L Dout High-Z High-Z Read in lower byte L H H L H H H High-Z High-Z High-Z Output disable L H H H L L X High-Z Din Din Write in upper byte L H H H L H L High-Z Dout Dout Read in upper byte L H H H L H H High-Z High-Z High-Z Output disable L H H L L L X Din Din Din Word write L H H L L H L Dout Dout Dout Word read L H H L L H H High-Z High-Z High-Z Output disable L H L L L L X Din High-Z A-1 Byte write L H L L L H L Dout High-Z A-1 Byte read L H L L L H H High-Z High-Z A-1 Output disable Note 1. H: VIH L:VIL X: VIH or VIL 2. When BYTE#=”L”, both LB# and UB# must be active. (LB#=UB#=”L”) Absolute Maximum Ratings Parameter Symbol Value unit Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note 1. -3.0V in case of AC (Pulse width ≤30ns) 2. Maximum voltage is +4.6V Vcc VT PT Topr Tstg Tbias -0.5 to +4.6 -0.5*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to 150 -40 to +85 V V W °C °C °C REJ03C0397-0001 Rev.0.01 Page 5 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Recommend Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Symbol Min. Typ. Max. Unit Test conditions Vcc Vss 2.4 0 2.0 2.2 -0.2 -0.2 -40 3.0 0 - 3.6 0 Vcc+0.2 Vcc+0.2 0.4 0.6 +85 V V V V V V °C Vcc=2.4V to 2.7V Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Vcc=2.7V to 3.6V - VIH VIL Ta Note 1 1 Note 1. -3.0V in case of AC (Pulse width ≤30ns) DC Characteristics Parameter Input leakage current Output leakage current Symbol Min. Typ. Max. Unit | ILI | - - 1 μA | ILO | - - 1 μA ICC1 - 20*1 35 mA Average operating current Standby current ICC2 - 2*1 5 mA ISB - 0.1*1 0.3 mA - 1.2*1 4 μA - 3*2 6 μA - - 15 μA - - 20 μA VOH 2.4 - - V VOH2 2.0 - - V VOL - - 0.4 V VOL2 - - 0.4 V Standby current ISB1 Output high voltage Output low voltage Test conditions Vin = Vss to Vcc BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIH or CS2 =VIL or OE# =VIH or WE# =VIL or LB# = UB# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS2 =VIL Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOH = -1mA Vcc≥2.7V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOH = -0.1mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOL = 2mA Vcc≥2.7V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOL = 0.1mA Note 1.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+25°C), and not 100% tested. 2.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+40°C), and not 100% tested. REJ03C0397-0001 Rev.0.01 Page 6 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Typ. Max. Unit Test conditions Note 10 10 pF pF Vin =0V V I/O =0V 1 1 Input capacitance C in Input / output capacitance C I/O Note 1.Typical parameter is sampled and not 100% tested. AC Characteristics Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C) Input pulse levels: VIL = 0.4V, VIH = 2.4V (Vcc = 2.7V ~ 3.6 V) VIL = 0.4V, VIH = 2.2V (Vcc = 2.4V ~ 2.7 V) Input rise and fall times: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm DQ CL = 30 pF REJ03C0397-0001 Rev.0.01 Page 7 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Read cycle R1LV0816ASD-5SI Parameter Symbol Read cycle time Address access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z REJ03C0397-0001 Rev.0.01 Page 8 of 16 Unit Note Max. 55 55 55 Min. 70 - Max. 70 70 70 ns ns ns ns tCLZ1 tCLZ2 10 10 10 30 55 - 10 10 10 35 70 - ns ns ns ns ns 2,3 2,3 tBLZ tOLZ tCHZ1 tCHZ2 5 5 0 0 20 20 5 5 0 0 25 25 ns ns ns ns 2,3 2,3 1,2,3 1,2,3 tBHZ tOHZ 0 0 20 20 0 0 25 25 ns ns 1,2,3 1,2,3 tACS1 tACS2 Output enable to output valid Output hold from address change LB#, UB# access time R1LV0816ASD-7SI Min. 55 - tRC tAA Chip select access time (Note 0) tOE tOH tBA 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Write Cycle R1LV0816ASD-5SI Parameter Symbol Write cycle time Address valid to end of write Chip select to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ (Note 0) Min. 55 50 50 40 50 0 0 25 0 5 0 0 Max. 20 20 R1LV0816ASD-7SI Min. 70 65 65 55 65 0 0 35 0 5 0 0 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 Note 0. If Vcc is 2.4-2.7V, parameters of R1LV0816ASA-7SI and R1LV0816ASD-7SI7SI are applied. 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. Typical parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or low UB#. A write begins at the latest transitions among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transitions among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle REJ03C0397-0001 Rev.0.01 Page 9 of 16 2009.12.08 [Preliminary] This product is under development and its specification might be changed without any notice. BYTE# function Parameter Byte setup time Byte recovery time Symbol tBS tBR R1LV0816ASD-5SI Min. 5 5 Max. - R1LV0816ASD-7SI Min. 5 5 BYTE# Timing Waveforms CS1# tBS BYTE# REJ03C0397-0001 Rev.0.01 Page 10 of 16 2009.12.08 tBR Max. - Unit ms ms Note [Preliminary] This product is under development and its specification might be changed without any notice. Timing Waveforms Read Cycle *1 tRC A0~18 (Word Mode) A -1~18 tBA LB#,UB# tBLZ tBHZ tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 WE# tOH tAA (Byte Mode) tCHZ2 VIH WE# = “H” level VIL tOE OE# tOLZ DQ0~15 High impedance Valid Data (Word Mode) DQ0~7 (Byte Mode) Note1.BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0397-0001 Rev.0.01 Page 11 of 16 tOHZ 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Write Cycle (1)*1 (WE# CLOCK) tWC A0~18 (Word Mode) A -1~18 tOH (Byte Mode) tBW LB#,UB# tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ tOW DQ0~15 (Word Mode) Valid Data DQ0~7 tDW (Byte Mode) Note1.BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0397-0001 Rev.0.01 Page 12 of 16 2009.12.08 tDH R1LV0816ASD –5SI, 7SI Preliminary Write Cycle (2)*1 (CS1#, CS2 CLOCK) tWC A0~18 (Word Mode) A -1~18 tAW (Byte Mode) tBW LB#,UB# tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# OE# = “H” level VIH VIL tDW DQ0~15 (Word Mode) Valid Data DQ0~7 (Byte Mode) Note1.BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0397-0001 Rev.0.01 Page 13 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Write Cycle (3)*1 (LB#, UB# CLOCK) tWC A0~18 (Word Mode) A -1~18 tAW (Byte Mode) tAS tBW tWR LB#,UB# tCW CS1# tCW CS2 tWP WE# OE# OE# = “H” level VIH VIL tDW tDH DQ0~15 (Word Mode) DQ0~7 Valid Data (Byte Mode) Note1.BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0397-0001 Rev.0.01 Page 14 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Data Retention Characteristics Parameter Symbol VCC for data retention VDR Data retention current Min. Typ. Max. Unit 1.5 - 3.6 V - 1.2*1 4 μA - 3*2 6 μA - - 15 μA - - 20 μA 0 5 - - ns ms ICCDR Chip select to data retention time Operation recovery time tCDR tR Test conditions*3 Vin ≥ 0V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Vcc=3.0V, Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V See retention waveform. Note 1.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+25°C), and not 100% tested. 2.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+40°C), and not 100% tested. 3.CS2 controls address buffer, WE# buffer, CS1# Buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or 0V ≤ CS2 ≤ 0.2V . The other inputs levels (address, WE#, OE#, CS1#, LB#, UB#, DQ) can be in the high impedance state. REJ03C0397-0001 Rev.0.01 Page 15 of 16 2009.12.08 R1LV0816ASD –5SI, 7SI Preliminary Data Retention Timing Waveforms *1 (1) CS1# controlled Vcc 2.4V tCDR 2.4V tR VDR 2.0V 2.0V CS1# ≥ Vcc - 0.2V CS1# (2) CS2 controlled Vcc 2.4V tCDR CS2 2.4V tR VDR 0.4V 0.4V 0V ≤ CS2 ≤ 0.2V (3) LB#, UB# controlled Vcc 2.4V tCDR VDR 2.0V LB#, UB# LB#, UB# ≥ Vcc - 0.2V Note1.BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0397-0001 Rev.0.01 Page 16 of 16 2.4V 2009.12.08 tR 2.0V Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. 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