H7N1002LD,H7N1002LS,H7N1002LM Datasheet

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Preliminary
H7N1002LD, H7N1002LS, H7N1002LM
Silicon N Channel MOS FET
High Speed Power Switching
REJ03G1131-0800
Rev.8.00
Nov 13, 2009
Features
• Low on-resistance
RDS (on) = 8 mΩ typ.
• Low drive current
• Available for 4.5 V gate drive
Outline
RENESAS Package code: PRSS0004AE-A
(Package name: LDPAK (L)
: PRSS0004AE-B
: LDPAK (S)-(1) )
4
4
1
1
2
3
: PRSS0004AE-C
: LDPAK (S)-(2) )
2
4
1
3
H7N1002LS
D
1. Gate
2. Drain
3. Source
4. Drain
G
2
3
H7N1002LM
H7N1002LD
S
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Storage temperature
Notes: 1. PW ≤ 10 μs, duty cycle ≤ 1%
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 1 of 8
Symbol
VDSS
VGSS
ID
ID (pulse) Note 1
IDR
Value
100
±20
75
300
75
Unit
V
V
A
A
A
IAP Note 3
EAR Note 3
Pch Note 2
Tch
Tstg
50
166
100
150
–55 to +150
A
mJ
W
°C
°C
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Symbol
V (BR) DSS
V (BR) GSS
IGSS
IDSS
VGS (off)
Static drain to source on state
resistance
RDS (on)
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate to source charge
Gate to drain charge
Turn-on delay time
Rise time
Turn-off delay time
|yfs|
Ciss
Coss
Crss
Qg
Qgs
Qgd
td (on)
tr
td (off)
Fall time
Body to drain diode forward voltage
Body to drain diode reverse recovery
time
Note:
4. Pulse test
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 2 of 8
tf
VDF
trr
Min
100
±20
—
—
1.5
—
—
57
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
8
10
95
9700
740
330
155
35
33
43
245
130
Max
—
—
±10
10
2.5
10
15
—
—
—
—
—
—
—
—
—
—
Unit
V
V
μA
μA
V
mΩ
mΩ
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
—
—
—
25
0.93
70
—
—
—
ns
V
ns
Test Conditions
ID = 10 mA, VGS = 0
IG = ±100 μA, VDS = 0
VGS = ±16 V, VDS = 0
VDS = 100 V, VGS = 0
ID = 1 mA, VDS = 10 V Note 4
ID = 37.5 A, VGS = 10 V Note 4
ID = 37.5 A, VGS = 4.5 V Note 4
ID = 37.5 A, VDS = 10 V Note 4
VDS = 10 V
VGS = 0
f = 1 MHz
VDD = 50 V
VGS = 10 V
ID = 75 A
VGS = 10 V, ID = 37.5 A
RL = 0.8 Ω
Rg = 4.7 Ω
IF = 75 A, VGS = 0
IF = 75 A, VGS = 0
diF/dt = 100 A/μs
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Main Characteristics
Maximum Safe Operation Area
Power vs. Temperature Derating
1000
150
100
50
ID (A)
300
100
Drain Current
Channel Dissipation
Pch (W)
200
10
0
0
50
100
150
Case Temperature
200
1
30
DC Operation
(Tc = 25°C)
3
PW = 10 ms
1 Operation in
(1shot)
0.3 this area is
limited by RDS(on)
0.1
Ta = 25°C
0.03
0.1 0.3
1
3
10 30
Drain to Source Voltage
Tc (°C)
Typical Output Characteristics
VDS = 10 V
Pulse Test
3.6 V
40
Pulse Test
40
30
Drain Current
Drain Current
VDS (V)
50
10 V
4V
30
3.4 V
20
10
VGS = 3 V
20
Tc = 75°C
25°C
10
–25°C
0
0
0
2
4
6
Drain to Source Voltage
8
0
10
Pulse Test
0.8
0.6
ID = 50 A
0.4
20 A
0.2
10 A
0
0
5
10
15
20
Gate to Source Voltage VGS (V)
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 3 of 8
2
3
4
5
VGS (V)
Static Drain to Source on State Resistance
vs. Drain Current
Drain to Source on State Resistance
RDS(on) (mΩ)
1.0
1
Gate to Source Voltage
VDS (V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source Saturation Voltage
VDS(on) (V)
100 300
Typical Transfer Characteristics
ID (A)
ID (A)
50
1
10 0 μs
0
m
μs
s
50
Pulse Test
20
VGS = 4.5 V
10
10 V
5
2
1
0.5
2
5
10
20
50
Drain Current ID (A)
100 200
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
Drain to Source on State Resistance
RDS(on) (mΩ)
Static Drain to Source on State Resistance
vs. Temperature
40
Pulse Test
32
50 A
24
ID = 10 A, 20 A
16
VGS = 4.5 V
50 A
8
10 A, 20 A
10 V
0
–40
0
40
80
120
Case Temperature
160
200
100
Tc = –25°C
10
25°C
1
75°C
0.1
VDS = 10 V
Pulse Test
0.02
0.01
Tc (°C)
100
20000
10000
Capacitance C (pF)
Reverse Recovery Time trr (ns)
10
Typical Capacitance vs.
Drain to Source Voltage
100
50
20
di / dt = 100 A / μs
VGS = 0, Ta = 25°C
10
0.1
Ciss
5000
2000
1000
Coss
500
200
Crss
100
50
VGS = 0
f = 1 MHz
20
0.3
1
3
10
Reverse Drain Current
30
100
0
10
160
16
VDD = 25 V
50 V
80 V
120
12
VDS
80
8
40
4
VDD = 80 V
50 V
25 V
0
0
80
160
240
320
Gate Charge Qg (nc)
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 4 of 8
40
50
0
400
1000
Switching Time t (ns)
VGS
VGS (V)
20
ID = 75 A
30
Switching Characteristics
Gate to Source Voltage
200
20
Drain to Source Voltage VDS (V)
IDR (A)
Dynamic Input Characteristics
VDS (V)
1
Drain Current ID (A)
Body to Drain Diode Reverse
Recovery Time
Drain to Source Voltage
0.1
300
tr
td(off)
100
td(on)
30
tf
10
3
1
0.1
VGS = 10 V, VDD = 30 V
PW = 5 μs, duty ≤ 1 %
Rg = 4.7 Ω
0.3
1
3
Drain Current
10
30
ID (A)
100
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Maximum Avalanche Energy vs.
Channel Temperature Derating
Repetitive Avalanche Energy EAR (mJ)
Reverse Drain Current
IDR
(A)
Reverse Drain Current vs.
Source to Drain Voltage
100
80
10 V
60
40
VGS = 0, –5 V
5V
20
Pulse Test
0
0
0.4
0.8
1.2
1.6
Source to Drain Voltage
2.0
200
IAP = 50 A
VDD = 25 V
duty < 0.1 %
Rg ≥ 50 Ω
160
120
80
40
0
25
VSD (V)
50
75
100
125
150
Channel Temperature Tch (°C)
Normalized Transient Thermal Impedance γ s (t)
Normalized Transient Thermal Impedance vs. Pulse Width
3
Tc = 25°C
1
D=1
0.5
0.3
0.2
θch – c (t) = γ s (t) • θch – c
0.1
0.1
θch – c = 1.25°C/W, Tc = 25°C
0.05
PDM
0 .0 2
0.03
0 .0
1
t
ho
1s
0.01
10 μ
D=
lse
pu
PW
T
PW
T
100 μ
1m
10 m
100 m
10
1
Pulse Width PW (S)
Avalanche Test Circuit
VDS
Monitor
Avalanche Waveform
L
EAR =
1
• L • IAP2 •
2
VDSS
VDSS – VDD
IAP
Monitor
Rg
V(BR)DSS
IAP
D.U.T
VDD
VDS
ID
Vin
15 V
50 Ω
0
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 5 of 8
VDD
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Switching Time Test Circuit
90%
Vout
Monitor
Vin Monitor
D.U.T.
Rg
Waveform
Vin
Vout
Vin
10 V
10%
RL
VDS
= 30 V
10%
90%
td(on)
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 6 of 8
10%
tr
90%
td(off)
tf
H7N1002LD, H7N1002LS, H7N1002LM
Preliminary
Package Dimensions
RENESAS Code
PRSS0004AE-A
MASS[Typ.]
1.40g
4.44 ± 0.2
1.3 ± 0.15
1.3 ± 0.2
1.37 ± 0.2
0.76 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
JEITA Package Code
SC-83
RENESAS Code
PRSS0004AE-B
2.49 ± 0.2
11.0 ± 0.5
0.2
0.86 +– 0.1
Package Name
LDPAK(S)-(1)
Unit: mm
10.2 ± 0.3
8.6 ± 0.3
11.3 ± 0.5
0.3
10.0 +– 0.5
Previous Code
LDPAK(L) / LDPAK(L)V
Previous Code
LDPAK(S)-(1) / LDPAK(S)-(1)V
0.4 ± 0.1
MASS[Typ.]
1.30g
(1.5)
10.0
2.54 ± 0.5
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 7 of 8
0.4 ± 0.1
0.3
3.0 +– 0.5
2.54 ± 0.5
0.2
0.86 +– 0.1
7.8
7.0
2.49 ± 0.2
0.2
0.1 +– 0.1
1.37 ± 0.2
1.3 ± 0.2
7.8
6.6
1.3 ± 0.15
+ 0.3
– 0.5
8.6 ± 0.3
(1.5)
(1.4)
4.44 ± 0.2
10.2 ± 0.3
Unit: mm
1.7
JEITA Package Code
⎯
(1.4)
Package Name
LDPAK(L)
2.2
H7N1002LD, H7N1002LS, H7N1002LM
JEITA Package Code
⎯
RENESAS Code
PRSS0004AE-C
Previous Code
LDPAK(S)-(2) / LDPAK(S)-(2)V
MASS[Typ.]
1.35g
7.8
6.6
(2.3)
10.0
2.49 ± 0.2
0.2
0.1 +– 0.1
7.8
7.0
1.3 ± 0.15
+ 0.3
– 0.5
8.6 ± 0.3
(1.5)
(1.4)
4.44 ± 0.2
10.2 ± 0.3
Unit: mm
1.7
Package Name
LDPAK(S)-(2)
Preliminary
2.2
1.37 ± 0.2
2.54 ± 0.5
0.2
0.86 +– 0.1
2.54 ± 0.5
0.4 ± 0.1
0.3
5.0 +– 0.5
1.3 ± 0.2
Ordering Information
Part Name
H7N1002LD-E
H7N1002LSTL-E
H7N1002LMTL-E
Quantity
500 pcs
1000 pcs
1000 pcs
REJ03G1131-0800 Rev.8.00 Nov 13, 2009
Page 8 of 8
Shipping Container
Box (Conductive Sack)
Taping
Taping
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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rights or any other rights of Renesas or any third party with respect to the information in this document.
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
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have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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Colophon .7.2