HM62V8100I Series Wide Temperature Range Version 8 M SRAM (1024-kword × 8-bit) ADE-203-1278B (Z) Rev.2.00 Nov.02.2009 Description The HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-word × 8-bit. HM62V8100I Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged package with 0.75 mm bump pitch or standard 44-pin TSOP II for high density surface mounting. Features • • • • • • • • Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 55 ns (Max) Power dissipation: Active: 6.0 mW/MHz (Typ) Standby: 1.5 µW (Typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: –40 to +85°C Rev.2.00, Nov.02.2009, page 1 of 15 HM62V8100-I Series Ordering Information Type No. Access time Package HM62V8100LTTI-5 HM62V8100LTTI-5SL 55 ns 55 ns 400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE) Rev.2.00, Nov.02.2009, page 2 of 15 HM62V8100-I Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (Top view) Pin Description Pin name Function A0 to A19 Address input I/O0 to I/O7 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable VCC VSS Power supply Ground NC No connection Rev.2.00, Nov.02.2009, page 3 of 15 A5 A6 A7 OE CS2 A8 NC NC I/O7 I/O6 VSS VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14 HM62V8100-I Series Block Diagram LSB A5 A6 A7 A4 A3 A9 A10 A11 A12 A13 MSB A14 V CC V SS • • • • • Row decoder I/O0 Memory matrix 2,048 x 4,096 Column I/O • • Input data control Column decoder I/O7 LSB MSB A16 A17A18 A19 A0 A1 A2 A15A8 • • CS2 CS1 Control logic WE OE Rev.2.00, Nov.02.2009, page 4 of 15 • • HM62V8100-I Series Operation Table CS1 CS2 WE OE I/O0 to I/O7 Operation H × L L L × L H H H × × H L H × × L × H High-Z High-Z Dout Din High-Z Standby Standby Read Write Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS VCC –0.5 to + 4.6 V Terminal voltage on any pin relative to VSS VT –0.5*1 to VCC + 0.3*2 V Power dissipation PT 1.0 W Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –40 to +85 °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.6 V V Input high voltage Input low voltage Ambient temperature range Note: VSS 0 0 0 VIH VIL Ta 2.2 –0.3 –40 — — — VCC + 0.3 V 0.6 V 85 °C 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns. Rev.2.00, Nov.02.2009, page 5 of 15 Note 1 HM62V8100-I Series DC Characteri stics Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA Vin = VSS to VCC Output leakage current |ILO| — — 1 µA CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, or VI/O = VSS to VCC Operating current ICC — — 20 mA CS1 = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA Average operating current ICC1 — 14 25 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL ICC2 — 2 4 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V Standby current ISB Standby current Output high voltage Output low voltage Note: — 0.1 0.3 mA CS2 = VIL 2 ISB1* — 0.5 25 µA 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V ISB1*3 — 0.5 10 µA VOH VOL 2.2 — — — — 0.4 V V IOH = –1 mA IOL = 2 mA 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L version. 3. This characteristic is guaranteed only for L-SL version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin — — 8 pF Vin = 0 V 1 Input/output capacitance CI/O — — 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.2.00, Nov.02.2009, page 6 of 15 HM62V8100-I Series AC Characteristics (Ta = -40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig) VTM R1 Dout R1 = 3070 Ω 30pF Rev.2.00, Nov.02.2009, page 7 of 15 R2 R2 = 3150 Ω VTM = 2.8 V HM62V8100-I Series Read Cycle HM62V8100I -5 Parameter Symbol Min Max Unit Read cycle time tRC 55 — ns Notes Address access time tAA — 55 ns Chip select access time tACS1 — 55 ns Output enable to output valid Output hold from address change Chip select to output in low-Z tACS2 tOE tOH tCLZ1 — — 10 10 55 35 — — ns ns ns ns 2, 3 tCLZ2 10 — ns 2, 3 Output enable to output in low-Z tOLZ 5 — ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 ns 1, 2, 3 Output disable to output in high-Z tCHZ2 tOHZ 0 0 20 20 ns ns 1, 2, 3 1, 2, 3 Rev.2.00, Nov.02.2009, page 8 of 15 HM62V8100-I Series Write Cycle HM62V8100I -5 Parameter Symbol Min Max Unit Notes Write cycle time tWC 55 — ns Address valid to end of write tAW 50 — ns Chip selection to end of write tCW 50 — ns 5 Write pulse width Address setup time Write recovery time Data to write time overlap tWP tAS tWR tDW 40 0 0 25 — — — — ns ns ns ns 4 6 7 Data hold from write time tDH 0 — ns Output active from end of write tOW 5 — ns 2 Output disable to output in High-Z tOHZ 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 20 ns 1, 2 Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. Rev.2.00, Nov.02.2009, page 9 of 15 HM62V8100-I Series Timing Waveform Read Cycle t RC Address Valid address tAA tACS1 CS1 tCLZ1*2, 3 CS2 tCHZ1*1, 2, 3 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tOHZ*1, 2, 3 tOE OE tOLZ*2, 3 Dout High impedance Rev.2.00, Nov.02.2009, page 10 of 15 tOH Valid data HM62V8100-I Series Write Cycle (1) (WE Clock) tWC Valid address Address tWR*7 tCW*5 CS1 tCW*5 CS2 tAW tWP*4 WE tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout Rev.2.00, Nov.02.2009, page 11 of 15 HM62V8100-I Series Write Cycle (2) (CS Clock, OE = VIH) tWC Valid address Address tAW tAS *6 tWR*7 tCW*5 CS1 tCW*5 CS2 tWP*4 WE tDW Valid data Din High impedance Dout Rev.2.00, Nov.02.2009, page 12 of 15 tDH HM62V8100-I Series Low VCC Data Retention Characteristics (Ta = -40 to +85°C) Parameter Symbol Min Typ*4 Max Unit Test conditions*3 VCC for data retention VDR 2.0 — 3.6 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC – 0.2 V CS1 ≥ VCC – 0.2 V Data retention current ICCDR*1 — 0.5 25 µA VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC – 0.2 V, CS1 ≥ VCC – 0.2 V ICCDR*2 — 0.5 10 µA Chip deselect to data retention time tCDR 0 — — ns Operation recovery time tR tRC*5 — — ns See retention waveform Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for L-SL version. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed. 5. tRC = read cycle time. Rev.2.00, Nov.02.2009, page 13 of 15 HM62V8100-I Series Low VCC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR Data retention mode tR VCC 2.7 V 2.2 V VDR CS1 0V CS1 ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode VCC 2.7 V CS2 VDR 0.6 V 0 V < CS2 < 0.2 V 0V Rev.2.00, Nov.02.2009, page 14 of 15 tR HM62V8100-I Series Package Dimensions HM62V8100LTTI Series (TTP-44DE) As of July, 2001 Unit: mm 18.41 18.81 Max 23 10.16 44 0.80 *0.27 ± 0.07 0.25 ± 0.05 22 0.80 0.13 M 11.76 ± 0.20 1.005 Max *Dimension including the plating thickness Base material dimension Rev.2.00, Nov.02.2009, page 15 of 15 0.13 ± 0.05 0.10 *0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0˚ – 5˚ 0.50 ± 0.10 Hitachi Code JEDEC JEITA Mass (reference value) TTP-44DE — — 0.43 g 0.68 1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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