MAX1232 Microprocessor Monitor General Description The MAX1232 microprocessor (μP) supervisory circuit provides μP housekeeping and power-supply supervision functions while consuming only 1/10th the power of the DS1232. The MAX1232 enhances circuit reliability in μP systems by monitoring the power supply, monitoring the software execution, and providing a debounced manual reset input. The MAX1232 is a plug-in upgrade of the Dallas DS1232. A reset pulse of at least 250ms duration is supplied on power-up, power-down, and low-voltage brownout conditions (5% or 10% supply tolerances can be selected digitally). Also featured is a debounced manual reset input that forces the reset outputs to their active states for a minimum of 250ms. A digitally programmable watchdog timer monitors software execution and can be programmed for timeout settings of 150ms, 600ms, or 1.2s. The MAX1232 requires no external components. Applications ●● ●● ●● ●● Features ●● Consumes 1/10th the Power of the DS1232 ●● Precision Voltage Monitor—Adjustable +4.5V or +4.75V ●● Power-OK/Reset Pulse Width—250ms Min ●● No External Components ●● Adjustable Watchdog Timer—150ms, 600ms, or 1.2s ●● Debounced Manual Reset Input for External Override ●● Available in 8-Pin PDIP/SO and 16-Pin Wide SO Packages Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1232C/D 0°C to +70°C Dice* MAX1232CPA 0°C to +70°C 8 PDIP MAX1232CSA 0°C to +70°C 8 SO Ordering Information continued at end of data sheet. Computers Controllers Intelligent Instruments Critical μP Power Monitoring *Contact factory for dice specifications. Note: Devices in PDIP and SO packages are available in both leaded(Pb) and lead(Pb)-free packaging. Specify lead(Pb)-free by adding the “+” symbol at the end of the part number when ordering. Lead-free not available for CERDIP package. Pin Configurations Typical Operating Circuit TOP VIEW VCC TOL RST 5%/10% TOLERANCE SELECT RESET GENERATOR PB RST 1 8 VCC TD 2 7 ST TOL 3 6 RST GND 4 5 RST MAX1232 REF RST PB RST MAX1232 DEBOUNCE DIP/SO N.C. 1 16 N.C. PB RST 2 15 VCC 14 N.C. N.C. 3 TD WATCHDOG TIMEBASE SELECT WATCHDOG TIMER GND ST TD 4 MAX1232 12 N.C. TOL 6 11 RST N.C. 7 10 N.C. 9 GND 8 WIDE SO 19-3899; Rev 2; 9/14 13 ST N.C. 5 RST MAX1232 Microprocessor Monitor Absolute Maximum Ratings Voltage Range on Any Pin (with respect to GND)......-1V to +7V Operating Temperature Range C Suffix................................................................0°C to +70°C E Suffix............................................................ -40°C to +85°C M Suffix.......................................................... -55°C to +125°C Storage Temperature Range............................. -65°C to +160°C Lead Temperature (soldering, 10s).................................. +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = TMIN to TMAX, unless otherwise noted.) MIN TYP MAX UNITS Supply Voltage PARAMETER SYMBOL VCC CONDITIONS 4.5 5.0 5.5 V ST and PBRST Input High Level (Note 1) VIH 2.0 ST and PBRST Input Low Level VIL -0.3 VCC + 0.3 V +0.8 V MAX UNITS +1.0 µA DC Electrical Characteristics (VCC = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS IIL Input Leakage ST, TOL Output Current RST MIN TYP -1.0 IOH VOH = 2.4V -1.0 -12 Output Current RST, RST IOL VOL = 0.4V 2.0 10 Operating Current (Note 2) ICC VCC 5% Trip Point (Note 3) VCCTP TOL = GND VCC 10% Trip Point (Note 3) VCCTP TOL = VCC mA mA 50 200 µA 4.50 4.62 4.74 V 4.25 4.37 4.49 V MIN TYP MAX UNITS CIN 5 pF COUT 7 pF Capacitance (Note 4) (TA = +25°C, unless otherwise noted.) PARAMETER Input Capacitance ST, TOL Output Capacitance RST, RST www.maximintegrated.com SYMBOL CONDITIONS Maxim Integrated │ 2 MAX1232 Microprocessor Monitor AC Electrical Characteristics (VCC = +5V ±10%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tPB Figure 3 20 PBRST Delay tPBD Figure 3 1 4 20 ms Reset Active Time tRST 250 610 1000 ms PBRST (Note 5) ST Pulse Width tST ST Timeout Period tTD Figure 4 ms 75 ns Figure 4, TD pin = 0V 62.5 150 250 TD pin = open 250 600 1000 TD pin = VCC 500 1200 2000 ms VCC Fall Time (Note 4) tF Figure 5 10 µs VCC Rise Time (Note 4) tB Figure 6 0 µs VCC Detect to RST High and RST Low tBPD Figure 7, VCC falling VCC Detect to RST Low and RST Open (Note 6) tBPU Figure 8, VCC rising Note Note Note Note Note Note 250 610 100 ns 1000 ms 1: PBRST is internally pulled up to VCC with an internal impedance of typically 40kΩ. 2: Measured with outputs open. 3: All voltages referenced to GND. 4: Guaranteed by design. 5: PBRST must be held low for a minimum of 20ms to guarantee a reset. 6: tR = 5μs. Pin Description PIN NAME FUNCTION WIDE SO DIP/SO 1, 3, 5, 7, 10, 12, 14, 16 — N.C. 2 1 PBRST 4 2 TD Time Delay Set. The watchdog timebase select input (tTD = 150ms for TD = 0V, tTD = 600ms for TD = open, tTD = 1.2s for TD = VCC). 6 3 TOL Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance. 8 4 GND Ground No Connection Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms in duration and is guaranteed to recognize inputs of 20ms or greater. 9 5 RST Reset Output (Active High). Goes active: (1) If VCC falls below the selected reset voltage threshold. (2) If PBRST is forced low. (3) If ST is not strobed within the minimum timeout period. (4) During power-up. Reset Output (Active Low, Open Drain). See RST. 11 6 RST 13 7 ST 15 8 VCC www.maximintegrated.com Strobe Input. Input for watchdog timer. +5V Power-Supply Input Maxim Integrated │ 3 MAX1232 Microprocessor Monitor Detailed Description Watchdog Timer Power Monitor A voltage detector monitors VCC and holds the reset outputs (RST and RST) in their active states whenever VCC is below the selected 5% or 10% tolerance (4.62V or 4.37V, typically). To select the 5% level, connect TOL to ground. To select the 10% level, connect TOL to VCC. The reset outputs will remain in their active states until VCC has been continuously in-tolerance for a minimum of 250ms (the reset active time) to allow the power supply and μP to stabilize. The RST output both sinks and sources current, while the RST output, an open-drain MOSFET, sinks current only and must be pulled high. Pushbutton Reset Input The MAX1232’s debounced manual reset input (PBRST) manually forces the reset outputs into their active states. The reset outputs go active after PBRST has been held low for a time tPBD, the pushbutton reset delay time. The reset outputs remain in their active states for a minimum of 250ms after PBRST rises above VIH (Figure 3). A mechanical pushbutton or an active logic signal can drive the PBRST input. The debounced input ignores input pulses less than 1ms and is guaranteed to recognize pulses of 20ms or greater. The PBRST input has an internal pullup to VCC of about 100μA; therefore, an external pullup resistor is not necessary. The microprocessor drives the ST input with an input/ output (I/O) line. The microprocessor must toggle the ST input within a set period (as determined by TD) to verify proper software execution. If a hardware or software failure keeps ST from toggling within the minimum timeout period—ST is activated only by falling edges (a high-tolow transition)—the MAX1232 reset outputs are forced to their active states for 250ms (Figure 2). This typically initiates the microprocessor’s power-up routine. If the interruption continues, new reset pulses are generated each timeout period until ST is strobed. The timeout period is determined by the TD input connection. This timeout period is typically 150ms with TD connected to GND, 600ms with TD floating, or 1200ms with TD connected to VCC. The software routine that strobes ST is critical. The code must be in a section of software that executes frequently enough so the time between toggles is less than the watchdog timeout period. One common technique controls the microprocessor I/O line from two sections of the program. The software might set the I/O line high while operating in the foreground mode, and set it low while in the background or interrupt mode. If both modes do not execute correctly, the watchdog timer issues reset pulses. +5V +5V 10kΩ VCC TD PB RST ST MAX1232 RST GND Figure 1. Pushbutton Reset www.maximintegrated.com I/O MICROPROCESSOR RESET +8V 7805 +5V 3-TERMINAL REGULATOR VCC 0.10µF RST MICROPROCESSOR MAX1232 ST TOL TD TOL RESET I/O GND Figure 2. Watchdog Timer Maxim Integrated │ 4 MAX1232 Microprocessor Monitor tST ST tPB tPBD PB RST tTD VIH VIL tRST RST NOTE: tSD IS THE MAXIMUM ELAPSED TIME BETWEEN ST HIGH-TO-LOW TRANSITIONS (ST IS ACTIVATED BY FALLING EDGES ONLY) WHICH WILL KEEP THE WATCHDOG TIMER FROM FORCING THE RESET OUTPUTS ACTIVE FOR A TIME OF tRST. tTD IS A FUNCTION OF THE VOLTAGE AT THE TD PIN, AS TABULATED BELOW. RST Figure 3. Pushbutton Reset. The debounced PBRST input ignores input pulses less than 1ms and is guaranteed to recognize pulses of 20ms or greater. CONDITION MIN tTD TYP MAX TD pin = 0V TD pin = open TD pin = VCC 62.5ms 250ms 500ms 150ms 250ms 1200ms 250ms 1000ms 2000ms Figure 4. Watchdog Strobe Input tF tR VCC +4.75V +4.75V +4.25V +4.25V VCC Figure 5. Power-Down Slew Rate www.maximintegrated.com Figure 6. Power-Up Slew Rate Maxim Integrated │ 5 MAX1232 Microprocessor Monitor VCC +4.5V (5% TRIP POINT) +4.75V (5% TRIP POINT) +4.25V (10% TRIP POINT) +4.5V (10% TRIP POINT) VCC tRPD RST tRPU RST VOH RST VOL VOH RST VOL VCC SLEW RATE = 1.66mV/sec (0.5V/300µsec) Figure 7. VCC Detect Reset Output Delay (Power-Down) www.maximintegrated.com Figure 8. VCC Detect Reset Output Delay (Power-Up) Maxim Integrated │ 6 MAX1232 Microprocessor Monitor Chip Topography Ordering Information PB RST VCC TD 0.099" (2.51 mm) PART TEMP RANGE PIN-PACKAGE MAX1232CWE 0°C to +70°C MAX1232EPA -40°C to +85°C 8 PDIP MAX1232ESA -40°C to +85°C 8 SO MAX1232EWE -40°C to +85°C 16 Wide SO MAX1232MJA -55°C to +125°C 8 CERDIP 16 Wide SO *Contact factory for dice specifications. Note: Devices in PDIP and SO packages are available in both leaded(Pb) and lead(Pb)-free packaging. Specify lead(Pb)-free by adding the “+” symbol at the end of the part number when ordering. Lead-free not available for CERDIP package. ST TOL Package Information RST GND 0.070" (1.78 mm) www.maximintegrated.com RST For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 CERDIP J8-2 21-0045 — 8 PDIP P8+2 21-0043 — 8 SO S8+4 21-0041 90-0096 16 Wide SO W16+1 21-0042 90-0107 PACKAGE TYPE Maxim Integrated │ 7 MAX1232 Microprocessor Monitor Revision History REVISION NUMBER REVISION DATE 1 11/05 Added lead-free information to the Ordering Information table 1, 6 2 9/14 Removed reference to automotive systems in the Applications 1 DESCRIPTION PAGES CHANGED For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │ 8