MIC1232 - Micrel

MIC1232
5V Voltage Supervisor with Manual Reset,
Watchdog Timer and Dual Reset Outputs
General Description
Features
The MIC1232 is a low-current microprocessor supervisor
for monitoring 5V systems. The device features logic
selectable (TOL) reset thresholds of 5% or 10% of 5V; a
pushbutton reset input (/PBRST); a watchdog timer with
three-state selectable (TD) timeout periods of 150ms,
600ms, or 1.2s; a fixed reset timeout period of 250ms
(min); and active-low open-drain reset (/RST) and activehigh push-pull reset (RST) outputs. The /RST output
maintains a valid reset condition for VCC as low as 1.4V.
The MIC1232 asserts a reset condition if the supply
voltage drops below the reset threshold, the pushbutton
reset is asserted low, or the watchdog timer does not see
a high-to-low transition on the watchdog timer input within
the watchdog timer period. A reset condition is held for the
reset timeout period of 250ms (min) after the pushbutton
input is released or after the supply voltage increases
above the reset threshold voltage.
The MIC1232 is a drop-in replacement for the DS1232,
MAX1232, and TC1232. It consumes a low 18µA (typ) of
supply current, 40µA (max). This is one-tenth the max
current of the DS1232, and one-quarter the max current of
the MAX1232 and TC1232. It operates over the –40C to
+85C temperature range and is available in the Pb-Free
8-pin SOIC and PDIP packages.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Low-current version of
DS1232/MAX1232/TC1232/CAT1232
• Low current: 18µA (typ), 40µA (max)
• Selectable threshold (TOL): 5% or 10% of 5V
• Selectable watchdog timer (TD): 150ms, 600ms, 1.2s
• Power OK/Reset time delay: 250ms (min)
• Debounced pushbutton reset input (/PBRST)
• Dual complementary reset outputs
– Active-low, open-drain reset output
– Active-high, push-pull reset output
• Available in Pb-Free 8-pin SOIC and PDIP packages
• –40°C to +85°C temperature range
• Pin-for-Pin compatible with MIC1832/DS1832/CAT1832
Applications
•
•
•
•
•
Automotive systems
Intelligent systems
Critical microprocessor power monitoring
Battery powered computers
Controllers
_________________________________________________________________________________________________________________________
Typical Application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 2013
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Micrel, Inc.
MIC1232
Ordering Information
Part Number
Temperature Range
Package
Lead Finish
MIC1232NY
–40° to +85°C
8-Pin PDIP
Pb-Free
MIC1232MY
–40° to +85°C
8-Pin SOIC
Pb-Free
Pin Configuration
8-Pin PDIP
8-Pin SOIC
Pin Description
Pin Number
Pin Name
Pin Function
1
/PBRST
Pushbutton Reset input: This input is debounced and can be driven with external logic signals or by
using a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the
/PBRST pin are ignored; any pulse with a duration of 20ms or greater is guaranteed to cause a
reset.
2
TD
Time Delay input: This input selects the timebase used by the watchdog timer. When TD = 0V, the
watchdog timeout period is set to a normal value of 150ms. When TD = open, the watchdog timeout
period is set to a nominal value of 600ms. When TD = VCC, the watchdog period is 1.2s nominally.
3
TOL
Tolerance Select input: This input selects whether 5% or 10% of VCC is used as the reset threshold
voltage. When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10% tolerance
level is selected.
4
GND
IC ground pin, 0V reference.
RST
RST is asserted high if either VCC goes below the reset threshold, the watchdog times out, or
/PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period
after VCC exceeds the reset threshold, after the watch times out, or after /PBRST goes high.
6
/RST
/RST is asserted low if either VCC goes below the reset threshold, the watchdog times out, or
/PBRST is pulled low for a minimum of 20ms. /RST remains asserted for one reset timeout period
after VCC exceeds the reset threshold, after the watch times out, or after /PBRST goes high. Opendrain output.
7
/ST
Input to watchdog timer. If /ST does not see a transition from high to low within the watchdog
timeout period, RST and /RST will be asserted.
8
VCC
Primary supply input, +5V.
5
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MIC1232
Absolute Maximum Ratings(1)
Operating Ratings(2)
Terminal Voltage
VCC ......................................................... −0.3V to +6.0V
All other inputs ............................. −0.3V to (VCC + 0.3V)
Input Current
VCC ...................................................................... 250mA
GND, all other inputs ............................................ 25mA
Lead Temperature (soldering, 10sec.) ....................... 300°C
Storage Temperature (Ts)........................... −65°C to 150°C
(3)
ESD Rating ....................................................... see Note 3
Operating Temperature Range
MIC1232M/N......................................... –40°C to +85°C
Electrical Characteristics
VCC = 4.5 V to 5.5V; TA = Operating Temperature Range; bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Parameter
Condition
Min
Supply Voltage Range
VCC
4.5
Supply Current
(4)
ICC
/ST and /PBRST Input Levels
(5)
VIH
Typ
Max
Units
5.5
V
40
µA
2.0
VCC + 0.3
V
−0.3
0.8
V
±1
µA
18
VIL
Input Leakage
IIL
Output Source Current, RST
VOH = 2.4V
1.0
10
mA
Output Sink Current, /RST. RST
VOL = 0.4V
2.0
10
mA
VCC 5% Trip Point (Reset Threshold Voltage)
TOL = GND
4.5
4.62
4.74
V
VCC 10% Trip Point (Reset Threshold Voltage)
TOL = VCC
4.25
4.37
4.49
V
Input Capacitance, /ST, TOL
(6)
CIN
5
pF
Output Capacitance, /RST, RST
COUT
7
pF
(6)
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
The device is not guaranteed to function outside its operating rating.
3.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4.
ICC is measured with outputs open and inputs within 0.5V of supply rails.
5.
/PBRST has an internal pull-up resistor to VCC (typ. 40kΩ).
6.
Guaranteed by design.
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MIC1232
AC Electrical Characteristics
VIN = 4.5V to 5.5V; TA = Operating Temperature Range; bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Parameter
/PBRST Min. Pulse Width, tPB
Condition
Min
/PBRST = VIL
(1)
Typ
Max
20
Units
ms
1
4
20
ms
Reset Active Time, tRST
250
610
1000
ms
/ST Pulse Width, tST
20
/PBRST Delay, tPBD
/ST Timeout Period, tTD
ns
TD = 0V
62.5
150
250
ms
TD = Open
250
600
1000
ms
TD = VCC
500
1200
2000
ms
VCC Fall Time, tF
10
VCC Rise Time, tR
0
VCC Detect to /RST Low and RST High, tRPD
VCC Falling
(2)
VCC Detect to /RST Low and RST Low, tRPD
VCC Falling
(3)
250
µs
ns
50
150
µs
610
1000
ms
Notes:
1.
/PBRST must be held low for a minimum of 20ms to guarantee a reset.
2.
VCC falling at 1.66mV/μs.
3.
/RST has an open drain output
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Timing Diagrams
Figure 1. Power-Up/Power-Down Sequence
Figure 2. Watchdog Input
Figure 3. Pushbutton Reset
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MIC1232
Application Information
Power Monitor
The /RST and RST pins are asserted whenever VCC falls
below the reset threshold voltage determined by the TOL
pin. A 5% tolerance level (4.62V reset threshold voltage)
can be selected by connecting the TOL pin to ground. A
10% tolerance level can be selected by connecting the
TOL pin to VCC. The reset pins will remain asserted for a
period of 250ms after VCC has risen above the reset
threshold voltage. The reset function ensures that the
microprocessor is properly reset and powers up into a
known condition after a power failure. /RST will remain
valid with VCC as low as 1.4V.
Pushbutton Reset Input
The /PBRST input can be driven with a manual
pushbutton switch or with external logic signals. The
input is internally debounced and requires an active low
signal to force the reset outputs into their active states.
The /PBRST input recognizes any pulse that is 20ms or
longer in duration and ignores all pulses that are less
than 1ms in duration.
Watchdog Timer
The microprocessor can be mounted by connecting the
/ST pin (watchdog input) to a bus line or I/O line. If a
high-to-low does not occur on the /ST pin within the
watchdog timeout period determined by the TD pin (see
the Electrical Characteristics Table), the /RST and the
RST will remain asserted for 250ms. A minimum pulse of
20ns or any transition high-to-low on the /ST pin resets
the watchdog timer. The watchdog timer is reset if /ST
sees a valid transition within the watchdog timeout
period.
Block Diagram
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MIC1232
Package Information(1)
8-Pin DIP (N)
8-Pin SOIC (M)
Note:
1.
Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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© 2000 Micrel, Incorporated.
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