MAX17122ETL+

TION KIT
EVALUA BLE
IL
AVA A
19-4951; Rev 1; 11/09
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Features
The MAX17122 multiple-output power-supply IC generates all the supply rails for thin-film transistor (TFT) liquidcrystal display (LCD) TV panels. It can operate from 8V
to 16.5V input voltages and is optimized for LCD TV
panel applications running directly from 12V regulated
supplies. It includes a 22V internal-switch step-down
regulator for digital logic, a 22V internal switch stepup regulator to power the TFT source drivers, and a
temperature-compensated 36V internal-switch boostbuck regulator that produces a negative output that can
vary according to the temperature sensed by an external NTC thermistor. All three of these regulators feature
high-efficiency and fixed-frequency operation. Highfrequency operation allows the use of small inductors
and capacitors, resulting in a compact solution.
S 8V to 16.5V Operating Range
S 750kHz Switching Frequency
S 22V Internal-Switch High-Performance Step-Up
Regulator
Fast Load-Transient Response
Current-Mode PWM Operation
100mI, 3.9A nMOS Switch
Capacitor-Adjustable Soft-Start
High-Voltage Stress Function
Drives External pMOS Shutdown Switch
S 22V Internal-Switch Step-Down Regulator
Preset 1% Accurate 3.3V Output Voltage or Adjustable Output (Dual Mode™)
Current-Mode PWM Operation
200mI, 2.5A nMOS Switch
Capacitor-Adjustable Power-Good Output
S 36V Internal-Switch Boost-Buck Regulator
Temperature-Compensated Output
Programmable Fixed Levels with Temperature-
Controlled Transition
Current-Mode PWM Operation
200mI, 1.8A pMOS Switch
S Positive Charge-Pump Linear Regulator Controller
Adjustable 1% Accurate Output Voltage
Uses External pnp Transistor
Regulates Switching-Node-Driven Charge Pump Doubler
Power-Good Output
S Negative Linear Regulator Controller
Adjustable 1.5% Accurate Output Voltage
Uses External npn Transistor
S Soft-Start for All Outputs
S Adjustable Power-Up Sequence
S Timed-Output Fault Protection with Restart for All
Outputs
S Latched Thermal-Shutdown Protection
S 40-Pin, 6mm x 6mm Thin QFN Package
The MAX17122 includes a positive charge-pump linear
regulator controller that uses an external pnp bipolar
junction transistor (BJT) to typically form a regulated
charge-pump doubler to supply the LCD positive gatedriver supply voltage. A negative gate-driver supply is
derived linearly between the boost-buck regulator’s output and ground, using an external npn BJT connected to
ground and a small bypass capacitor.
Other features include an external-capacitor-timed,
open-drain, power-good output that monitors the stepdown regulator’s feedback and a simple untimed output
that monitors the positive charge-pump linear regulator’s
feedback. A high-voltage stress function is available for
the step-up regulator output. The GATE output directly
drives an external p-channel MOSFET to provide True
ShutdownK of the step-up output.
The MAX17122 is available in a 6mm x 6mm, 40-pin thin
QFN lead-free package and operates over the -40NC to
+85NC temperature range.
Applications
LCD TV Panels
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17122ETL+
-40NC to +85NC
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
True Shutdown and Dual Mode are trademarks of Maxim
Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17122
General Description
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
ABSOLUTE MAXIMUM RATINGS
IN, IN2, IN3, EN1, EN2, LX1, GATE,
DRVP, RHVS to AGND.......................................-0.3V to +22V
GATE to IN............................................................-6.5V to +0.3V
GND1 to AGND.................................................................. Q0.3V
DLY1, DLY2, DEL, VL, RESET, GPGD,
HVS to AGND.......................................................-0.3V to +6V
FBP, FBN, FB1, FB2, FB3, COMP1, COMP3, OUTB
SET, NTC, SS to AGND.......................... -0.3V to (VVL + 0.3V)
DRVN to VL............................................................-36V to +0.3V
LX2 to GND1............................................. -0.3V to (VIN2 + 0.3V)
LX3 to IN3...............................................................-36V to +0.3V
BST2 to VL..............................................................-0.3V to +22V
BST2 to LX2..............................................................-0.3V to +6V
RMS LX1, GND1, IN2, IN3, LX3 Current (each pin).............1.6A
RMS LX2 (total for both pins)................................................2.4A
RMS VL, DRVN, DRVP Current...........................................50mA
Continuous Power Dissipation (TA = +70NC)
40-Pin Thin QFN
(derate 35.7mW/NC above +70NC)..........................2857.1mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+160NC
Storage Temperature Range............................. -65NC to +165NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = 0°C to +85°C. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
16.5
V
GENERAL
IN, IN2, IN3
Input-Voltage Range
IN + IN2 + IN3
Quiescent Current
IN + IN2 + IN3
Shutdown Current
8
Only LX2 and LX3 switching (VFB1 = VFBP = 1.5V, VFB2 =
1.1V, VFB3 = 1.8V, VFBN = 1.5V); VEN1 = VEN2 = 5V
10
LX2 and LX3 not switching (VFB1 = VFB2 = VFBP = 1.5V,
VFBN = 1.5V, VFB3 = 0); VEN1 = VEN2 = 5V
2
4
0.55
1
mA
Phase Difference Between
Regulators
750
862
kHz
IN Undervoltage-Lockout
Threshold
mA
EN1 = EN2 = AGND (shutdown)
SMPS Operating Frequency
638
Step-down and boost-buck
180
Step-down and step-up
180
VIN rising, 2.5% hysteresis
15
Degrees
6
7
8
V
VL REGULATOR
VL Output Voltage
IVL = 10mA, VFB1 = VFB2 = VFBP = 1.1V, VFBN = 0.75V,
VFB3 = 1.8V (all regulators switching)
4.9
5.0
5.1
V
VL Undervoltage-Lockout
Threshold
VL rising, 2.5% hysteresis
3.6
4.0
4.4
V
TA = +25NC
3.267
3.300
3.333
0NC < TA < +85NC
3.25
STEP-DOWN REGULATOR
OUTB Voltage in Fixed Mode
FB2 = AGND, no load (Note 1)
FB2 Voltage in Adjustable Mode
VOUTB = 3.3V, no load (Note 1)
FB2 Adjustable-Mode
Threshold Voltage
Dual-mode comparator
TA = +25NC
0NC < TA < +85NC
1.2375
3.35
1.250
1.23
0.10
1.2625
1.27
0.15
2 _______________________________________________________________________________________
0.20
V
V
V
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = 0°C to +85°C. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3.6
V
1.0
1.04
V
125
200
nA
Output Voltage Adjust Range
Step-down output
1.5
FB2 Fault-Trip Level
Falling edge
0.96
FB2 Input-Bias Current
VFB2 = 1.5V
50
DC Load Regulation
0.4A < ILOAD < 2A
0.5
%
DC Line Regulation
No load, 10.8V < VIN2 < 13.2V
0.1
%/V
LX2-to-IN2 nMOS Switch
On-Resistance
200
400
mI
LX2-to-GND1 nMOS Switch
On-Resistance
6
10
24
I
BST2-to-VL pMOS Switch
On-Resistance
6
12
24
I
Low-Frequency Operation
OUTB Threshold
LX2 only
Low-Frequency Operation
Switching Frequency
LX2 Positive Current Limit
Soft-Start Ramp Time
2.5
Zero to full limit
0.8
V
188
kHz
3.0
3.5
3
Maximum Duty Factor
A
ms
68
75
82
TA = +25NC
1.63
1.65
1.67
0NC < TA < +85NC
1.62
1.65
1.68
-125
%
BOOST-BUCK REGULATOR
FB3 Regulation Voltage
No load, VNTC = 2V
FB3 Input-Bias Current
VFB3 = 0.5V
-50
FB3 Pulldown Resistance
EN1 = AGND
300
1.9
-210
nA
1200
I
FB3 Fault-Trip Level
Rising edge
DC Load Regulation
0A < ILOAD < 400mA
0.3
%
DC Line Regulation
No load, 10.8V < VIN2 < 13.2V
0.1
%/V
LX3-to-IN3 pMOS Switch
On-Resistance
LX3 Positive Current Limit
Duty cycle = 60%
Soft-Start Ramp Time
Zero to full limit
Maximum Duty Factor
0NC < TA < +25NC
NTC, SET Current
1.8
2.1
200
400
2.1
2.4
3
V
mI
A
ms
85
89
94
98
100
102
100
+25NC < TA < +85NC
NTC, SET Effective Voltage
Range
2.0
V
0NC < TA < +25NC
0.1
1.65
+25NC < TA < +85NC
0.3
1.65
%
FA
V
_______________________________________________________________________________________ 3
MAX17122
ELECTRICAL CHARACTERISTICS (continued)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = 0°C to +85°C. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STEP-UP REGULATOR
Output-Voltage Range
VIN
20
V
Oscillator Maximum Duty Cycle
70
76
83
%
1.2375
1.250
1.2625
TA = +25NC
FB1 Regulation Voltage
VFB1 = COMP, CCOMP = 1nF
FB1 Output Undervoltage
Fault Trip Level
Falling edge
0.96
1.0
1.04
FB1 Output Short Trip Level
Falling edge
0.35
0.375
0.4
FB1 Load Regulation
0 < ILOAD < full, transient only
FB1 Line Regulation
10.8V < VIN < 13.2V
0.08
0.15
%/V
FB1 Input-Bias Current
VFB1 = 2V
10
125
200
nA
FB1 Transconductance
DI = Q2.5FA at COMP, FB1 = COMP
150
320
560
FB1 Voltage Gain
FB1 to COMP
LX1 Bias Current
VFB1 = 1.5V, VLX1 = 20V
LX1 Current Limit
VFB1 = 1.1V, duty cycle = 25%
0NC < TA < +85NC
1.23
1.27
-1
V
V
V
%
3500
FS
V/V
10
40
3.9
4.5
5.1
A
0.16
0.23
0.3
V/A
LX1 On-Resistance
100
200
mI
SS Full Output Level
1.25
Current-Sense Transresistance
SS Charge Current
FA
V
6
9
12
1.2375
1.250
1.2625
FA
POSITIVE CHARGE-PUMP LINEAR REGULATOR (DRVP)
TA = +25NC
FBP Regulation Voltage
IDRVP = 1.35mA
FBP Input-Bias Current
VFBP = 1.25V
FBP Effective Load-Regulation
Error (Transconductance)
VDRVP = 15V, IDRVP = 0.6mA to 6mA
DRVP Sink Current
VDRVP = 15V, VFBP = 1.1V
DRVP Off-Leakage Current
VDRVP = 15V, VFBP = 1.5V
FBP Fault-Trip Level
Falling edge
Positive Regulator Soft-Start
Period
7-bit voltage ramp with filtering to prevent high peak
currents
0NC < TA < +85NC
V
1.23
1.27
-50
+50
nA
30
mV
30
mA
0.1
10
FA
1.0
1.04
V
15
10
0.96
3
ms
NEGATIVE LINEAR-REGULATOR CONTROLLER (DRVN)
FBN Regulation Voltage
IDRVN = 1.35mA
TA = +25NC
0.985
1
1.015
0NC < TA < +85NC
0.98
1
1.02
FBN Input-Bias Current
V
-50
+50
nA
FBN Pulldown Resistance
EN1 = AGND
250
1000
I
FBN Fault-Trip Level
Falling edge
0.45
0.5
0.55
V
FBN Effective Load-Regulation
Error (Transconductance)
VDRVN = -7.5V, IDRVN = 0.6mA to 6mA
23
46
mV
DRVN Source Current
VDRVN = -7.5V, VFBN = 0.85V
DRVN Off-Leakage Current
VDRVN = -7.5V, VFBN = 1.15V
10
4 _______________________________________________________________________________________
mA
40
FA
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = 0°C to +85°C. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.975
1.00
1.025
V
POWER-GOOD BLOCKS
FB2 Power-Good Threshold
FB2 rising
FB2 Threshold Hysteresis
12
mV
RESET Output Low Voltage
IRESET = 1mA
0.4
V
RESET Leakage Current
VRESET = 3V
1
FA
FBP Power-Good Threshold
FBP rising
1.2
V
1.1
FBP Threshold Hysteresis
1.15
125
mV
GPGD Output Low Voltage
IGPGD = 1mA
0.4
V
GPGD Leakage Current
VGPGD = 3V
1
FA
GATE FUNCTION
GATE Pulldown Current
GATE charging current
0.15
Gate done current
0.62
GATE Drive Voltage
VIN2 - VGATE, GATE enabled
GATE Pullup Resistance
GATE off, to IN2
5.0
5.35
mA
5.65
25
V
I
HVS BLOCK
HVS Input Low Voltage
0.6
HVS Input High Voltage
1.85
HVS Input Pulldown Resistance
RHVS Output Resistance
IRHVS = 4mA
V
V
1
MI
25
I
SEQUENCE CONTROL
EN1, EN2, DLY1, DLY2, DEL
Charge Current
Measured at 1V
EN1, EN2, DLY1, DLY2, DEL
Turn-On Threshold
6
8.5
11
FA
1.25
1.30
V
EN1, EN2 Discharge Switch
On-Resistance
VL < UVLO or fault tripped
50
I
DLY1, DLY2, DLP Discharge
Switch On-Resistance
EN1 = low or fault tripped
10
I
Duration to Trigger Fault
50
ms
Duration to Restart After Fault
160
ms
+160
NC
FAULT DETECTION
Thermal-Shutdown Threshold
Typical hysteresis = 15NC
_______________________________________________________________________________________ 5
MAX17122
ELECTRICAL CHARACTERISTICS (continued)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = -40°C to +85°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
16.5
V
GENERAL
IN, IN2, IN3
Input-Voltage Range
8
IN + IN2 + IN3
Quiescent Current
Only LX2 and LX3 switching (VFB1 = VFBP = 1.5V, VFB2 =
1.1V, VFB3 = 1.8V, VFBN = 1.5V); VEN1 = VEN2 = 5V
15
mA
IN + IN2 + IN3
Quiescent Current
LX2 and LX3 not switching (VFB1 = VFB2 = VFBP = 1.5V,
VFBN = 1.5V, VFB3 = 0); VEN1 = VEN2 = 5V
4
mA
IN + IN2 + IN3
Shutdown Current
EN1 = EN2 = AGND (shutdown)
1
mA
638
862
kHz
6
8
V
SMPS Operating Frequency
IN Undervoltage-Lockout
Threshold
VIN rising, 2.5% hysteresis
VL REGULATOR
VL Output Voltage
IVL = 10mA, VFB1 = VFB2 = VFBP = 1.1V, VFBN = 0.75V,
VFB3 = 1.8V (all regulators switching)
4.9
5.1
V
VL Undervoltage-Lockout
Threshold
VL rising, 2.5% hysteresis
3.6
4.4
V
STEP-DOWN REGULATOR OUTB Voltage in Fixed Mode
FB2 = AGND, no load (Note 1)
-40NC < TA < +85NC
3.25
3.35
V
FB2 Voltage in Adjustable Mode
VOUTB = 3.3V, no load (Note 1)
-40NC < TA < +85NC
1.23
1.27
V
FB2 Adjustable-Mode
Threshold Voltage
Dual-mode comparator
0.10
0.20
V
Output Voltage Adjust Range
Step-down output
1.5
3.6
V
FB2 Fault-Trip Level
Falling edge
0.96
1.04
V
FB2 Input-Bias Current
VFB2 = 1.5V
50
200
nA
400
mI
LX2-to-IN2 nMOS Switch
On-Resistance
LX2-to-GND1 nMOS Switch
On-Resistance
6
24
I
BST2-to-VL pMOS Switch
On-Resistance
6
24
I
LX2 Positive Current Limit
2.5
3.5
A
Maximum Duty Factor
68
82
%
BUCK-BOOST REGULATOR
FB3 Regulation Voltage
No load, VNTC = 2V
1.62
1.68
V
FB3 Input-Bias Current
VFB3 = 0.5V
-50
-210
nA
FB3 Pulldown Resistance
EN1 = AGND
300
1200
I
FB3 Fault-Trip Level
Rising edge
1.9
2.1
V
400
mI
-40NC < TA < +85NC
LX3-to-IN3 pMOS Switch
On-Resistance
6 _______________________________________________________________________________________
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = -40°C to +85°C.) (Note 2)
PARAMETER
LX3 Positive Current Limit
CONDITIONS
Duty cycle = 60%
Maximum Duty Factor
MIN
TYP
MAX
UNITS
1.8
2.4
A
85
94
%
FA
NTC, SET Current
-40NC < TA < +25NC
97
104
NTC, SET Effective Voltage
Range
0NC < TA < +25NC
0.1
1.65
+25NC < TA < +85NC
0.3
1.65
VIN
20
V
V
STEP-UP REGULATOR
Output-Voltage Range
Oscillator Maximum Duty Cycle
70
83
%
1.23
1.27
V
Falling edge
0.96
1.04
V
FB1 Output Short-Trip Level
Falling edge
0.35
FB1 Line Regulation
10.8V < VIN < 13.2V
FB1 Input-Bias Current
VFB1 = 2V
FB1 Transconductance
DI = Q2.5FA at COMP, FB1 = COMP
LX1 Bias Current
VFB1 = 1.5V, VLX1 = 20V
LX1 Current Limit
VFB1 = 1.1V, duty cycle = 25%
3.9
5.1
A
0.16
0.3
V/A
200
mI
6
12
FA
1.23
1.27
V
-50
+50
nA
30
mV
30
mA
10
FA
0.96
1.04
V
0.98
1.02
V
-50
+50
nA
FB1 Regulation Voltage
FB1 = COMP, CCOMP = 1nF
FB1 Output Undervoltage
Fault-Trip Level
-40NC < TA < +85NC
Current-Sense Transresistance
0.4
V
0.15
%/V
10
200
nA
150
560
FS
40
FA
LX1 On-Resistance
SS Charge Current
POSITIVE CHARGE-PUMP LINEAR REGULATOR (DRVP)
FBP Regulation Voltage
IDRVP = 1.35mA
FBP Input-Bias Current
VFBP = 1.25V
FBP Effective Load-Regulation
Error (Transconductance)
VDRVP = 15V, IDRVP = 0.6mA to 6mA
DRVP Sink Current
VDRVP = 15V, VFBP = 1.1V
DRVP Off-Leakage Current
VDRVP = 15V, VFBP = 1.5V
FBP Fault-Trip Level
Falling edge
-40NC < TA < +85NC
10
NEGATIVE LINEAR-REGULATOR CONTROLLER (DRVN)
FBN Regulation Voltage
IDRVN = 1.35mA
-40NC < TA < +85NC
FBN Input-Bias Current
FBN Pulldown Resistance
EN1 = AGND
250
1000
I
FBN Fault-Trip Level
Falling edge
0.45
0.55
V
FBN Effective Load-Regulation
Error (Transconductance)
VDRVN = -7.5V, IDRVN = 0.6mA to 6mA
46
mV
DRVN Source Current
VDRVN = -7.5V, VFBN = 0.85V
DRVN Off-Leakage Current
VDRVN = -7.5V, VFBN = 1.15V
10
mA
40
FA
_______________________________________________________________________________________ 7
MAX17122
ELECTRICAL CHARACTERISTICS (continued)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VIN2 = VIN3 = 12V, TA = -40°C to +85°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.025
V
0.4
V
1
FA
1.2
V
POWER-GOOD BLOCKS
FB2 Power-Good Threshold
FB2 rising
RESET Output Low Voltage
IRESET = 1mA
0.975
RESET Leakage Current
VRESET = 3V
FBP Power-Good Threshold
FBP rising
GPGD Output Low Voltage
IGPGD = 1mA
0.4
V
GPGD Leakage Current
VGPGD = 3V
1
FA
5.65
V
0.6
V
1.1
GATE FUNCTION
GATE-Drive Voltage
VIN2 - VGATE, GATE enabled
5.0
HVS BLOCK
HVS Input Low Voltage
HVS Input High Voltage
1.85
V
SEQUENCE CONTROL
EN1, EN2, DLY1, DLY2, DEL
Charge Current
Measured at 1V
6
EN1, EN2, DLY1, DLY2, DEL
Turn-On Threshold
11
FA
1.30
V
Note 1: When the inductor is in continuous conduction (EN2 = VL or heavy load), the output voltage has a DC regulation level
lower than the error-comparator threshold by 50% of the output-voltage ripple. In discontinuous conduction (light load),
the step-down regulator’s output voltage has a DC regulation level higher than the error-comparator threshold by up to
50% of the output-voltage ripple.
Note 2: Specifications to -40NC are guaranteed by design, not production tested.
8 _______________________________________________________________________________________
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
STEP-DOWN REGULATOR EFFICIENCY
vs. LOAD CURRENT
0.4
VIN = 12V
80
MAX17122 toc02
85
OUTPUT-VOLTAGE ERROR (%)
VIN = 10V
EFFICIENCY (%)
0.6
MAX17122 toc01
90
STEP-DOWN REGULATOR NORMALIZED
OUTPUT VOLTAGE vs. LOAD CURRENT
75
70
65
0.2
0
VIN = 12V
-0.2
-0.4
-0.6
-0.8
VIN = 10V
-1.0
-1.2
-1.4
60
0.10
0
10
1
0.4
0.8
1.2
1.6
2.0
LOAD CURRENT (A)
LOAD CURRENT (A)
STEP-DOWN REGULATOR LOAD-TRANSIENT
RESPONSE (0.2A TO 1.7A)
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17122 toc03
VOUTB
(AC-COUPLED)
200mV/div
0V
92
EFFICIENCY (%)
0A
VIN = 12V
94
IL2
1A/div
MAX17122 toc04
96
2.4
VIN = 10V
90
88
86
84
ILOAD
1A/div
0A
82
80
L = 4.7µH
0.01
20µs/div
0.10
1
10
LOAD CURRENT (A)
STEP-UP REGULATOR NORMALIZED
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17122 toc06
MAX17122 toc05
0.10
0.05
OUTPUT-VOLTAGE ERROR (%)
STEP-UP REGULATOR LOAD-TRANSIENT
RESPONSE (0.2A TO 1.2A)
0
IL1
1A/div
0A
-0.05
-0.10
-0.15
0V
VAVDD
(AC-COUPLED)
200mV/div
0A
ILOAD
1A/div
VIN = 10V
-0.20
-0.25
VIN = 12V
-0.30
-0.35
0
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
2.5
L1 = 4.7µH
CCOMP1 = 330pF
RCOMP1 = 39.2kI
CCOMP1P = 10pF
40µs/div
_______________________________________________________________________________________ 9
MAX17122
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT
RESPONSE (0.2A TO 2.2A)
STEP-UP REGULATOR
STARTUP SEQUENCE
MAX17122 toc07
MAX17122 toc08
VEN2
5V/div
IL1
1A/div
0A
VAVDD
(AC-COUPLED)
200mV/div
0V
0V
VGATE
10V/div
0V
VAVDD
10V/div
0V
ILOAD
1A/div
0A
VLX1
10V/div
0V
4ms/div
10µs/div
5.8
5.6
85
80
EFFICIENCY (%)
5.4
5.2
5.0
4.8
4.6
BOOST-BUCK REGULATOR NORMALIZED
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17122 toc10
90
MAX17122 toc09
6.0
BOOST-BUCK REGULATOR
EFFICIENCY vs. LOAD CURRENT
VIN = 10V
75
VIN = 12V
70
65
60
4.4
0.50
0
VIN = 12V
-0.50
MAX17122 toc11
STEP-UP REGULATOR PEAK
INDUCTOR CURRENT AT CURRENT
LIMIT vs. INPUT VOLTAGE
OUTPUT-VOLTAGE ERROR (%)
L1 = 4.7µH
CCOMP1 = 330pF
RCOMP1 = 39.2kI
CCOMP1P = 10pF
PEAK INDUCTOR CURRENT (A)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
VIN = 10V
-1.00
-1.50
55
4.2
4.0
-2.00
50
8
9
10
11
INPUT VOLTAGE (V)
12
13
0.01
0.10
LOAD CURRENT (A)
1
0
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
10 ��
0.6
0.7
0.8
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
BOOST-BUCK REGULATOR PEAK
INDUCTOR CURRENT AT CURRENT
LIMIT vs. INPUT VOLTAGE
BOOST-BUCK REGULATOR
LOAD-TRANSIENT
RESPONSE (40mA TO 380mA)
MAX17122 toc12
MAX17122 toc13
2.40
VGOFF2
(AC-COUPLED)
200mV/div
0V
2.30
2.25
2.20
2.15
2.10
2.05
ILOAD
200mA/div
0A
2.00
9
8
100µs/div
L3 = 22µH
CCOMP3 = 470pF
RCOMP3 = 47.5kI
CCOMP3P = 10pF
10
11
12
13
-10
-15
-20
VIN = 10V
0
MAX17122 toc15
MAX17122 toc16
0.2
OUTPUT-VOLTAGE ERROR (%)
-5
POSITIVE CHARGE-PUMP
REGULATOR LOAD-TRANSIENT
RESPONSE (0A TO 100mA)
POSITIVE CHARGE-PUMP REGULATOR
NORMALIZED LOAD REGULATION
MAX17122 toc14
0
-0.2
-0.6
VGON
(AC-COUPLED)
1V/div
0V
VIN = 12V
-0.4
VAVDD = 16.5V
IAVDD = 350mA
VAVDD = 16.5V
IAVDD = 350mA
ILOAD
50mA/div
-0.8
0A
-1.0
-25
-40
-20
0
20
14
INPUT VOLTAGE (V)
BOOST-BUCK REGULATOR OUTPUT
TEMPERATURE COMPENSATION
OUTPUT VOLTAGE (V)
PEAK INDUCTOR CURRENT (A)
2.35
MAX17122
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
40
TEMPERATURE (°C)
60
80
0
50
100
150
200
40µs/div
LOAD CURRENT (mA)
______________________________________________________________________________________ 11
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
NEGATIVE LINEAR REGULATOR
LOAD-TRANSIENT
RESPONSE (0A TO 100mA)
NEGATIVE LINEAR REGULATOR
NORMALIZED LOAD REGULATION
MAX17122 toc18
MAX17122 toc17
0.5
0.4
OUTPUT-VOLTAGE ERROR (%)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
0.3
0.2
VGOFF1
(AC-COUPLED)
100mV/div
0V
0.1
0
-0.1
-0.2
-0.3
-0.4
ILOAD
50mA/div
0A
-0.5
0
100
200
300
400
500
20µs/div
LOAD CURRENT (mA)
POWER-UP SEQUENCE OF
ALL SUPPLY OUTPUTS
MAX17122 toc19
0V
0V
0V
RESET FUNCTION
VIN
VEN1
VOUTB
VEN2
VGON
VAVDD
MAX17122 toc20
VOUTB
2V/div
0V
VDEL
1V/div
0V
VGOFF1
VGOFF2
0V, 0V
0V
0V
0V
VRESET
2V/div
0V
VIN = 10V/div
VEN1 = 5V/div
VOUTB = 5V/div
VEN2 = 5V/div
10ms/div
VGON = 10V/div
VAVDD = 10V/div
VGOFF1 = 5V/div
VGOFF2 = 10V/div
4ms/div
12 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
PIN
NAME
FUNCTION
External p-Channel MOSFET Control Output. When the step-up regulator is enabled, GATE
pulls down to control the step-up output during its soft-start. Once GATE is fully on, the step-up
regulator begins switching to regulate the final portion of its soft-start.
1
GATE
2
IN
Input of the Internal 5V Linear Regulator and the Startup Circuitry. Bypass IN to AGND with 0.22FF
close to the IC.
3, 4
IN2
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between
IN2 and LX2.
5, 24
AGND
6, 7
LX2
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET
connected between IN2 and LX2. Connect the inductor and Schottky catch diode to LX2 and minimize the trace area for low EMI.
8
BST2
Step-Down Regulator Bootstrap Capacitor Connection for High-Side Gate Driver. Connect a 0.1FF
ceramic capacitor from BST2 to LX2.
9
OUTB
Step-Down Regulator Output-Voltage Sense Input. Connect OUTB to the step-down regulator
output.
Analog Ground
10
FB2
Step-Down Regulator Feedback Input. Connect FB2 to AGND to select the step-down converter’s
3.3V fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider
between the step-down regulator output and AGND to set the step-down regulator output voltage.
Place the resistive voltage-divider within 5mm of FB2.
11
GPGD
GON Power-Good Signal Open-Drain Output. GPGD is connected to AGND whenever VFBP is less
than the VFBP power-good threshold. GPGD is high impedance whenever VFBP is greater than the
threshold.
12
DLY1
Step-Up Regulator Delay Input. Connect a capacitor from DLY1 and AGND to set the delay time
between EN2’s rise and the step-up regulator’s soft-start. An 8FA current source charges CDLY1.
DLY1 is internally pulled to AGND whenever either EN1 or EN2 is low or VL is below its UVLO
threshold.
13
EN1
Step-Down Enable Input. An 8FA current source charges the capacitor at EN1. When EN1 is high,
the step-down regulator begins operating.
14
EN2
Step-Up and Positive Charge-Pump Linear Regulator Enable Input. Negative linear regulator and
boost-buck regulator enable input. An 8FA current source charges the capacitor at EN2. When
EN2 is high, DLY1 and DLY2 begin charging. DLY1 starts GATE, which turns on the external
p-channel MOSFET and the step-up regulator. DLY2 starts the positive charge-pump linear regulator. EN2 is inactive until after the step-down regulator soft-start is finished.
15
HVS
High-Voltage Stress Mode Control Input. When HVS is high, the RHVS open-drain output connects
to AGND. RHVS is high impedance when HVS is low.
16
FBN
Negative Linear-Regulator Controller Feedback Input. Connect FBN to the center of a resistive
voltage-divider between the negative output and a 3.3V reference to set the negative chargepump regulator output voltage. Place the resistive voltage-divider within 5mm of FBN.
______________________________________________________________________________________ 13
MAX17122
Pin Description
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Pin Description (continued)
PIN
NAME
FUNCTION
17
SS
Step-Up Regulator Soft-Start Input. Connect a capacitor at SS to control the step-up regulator softstart ramp time. The capacitor charge current is 10FA and the SS voltage ramps from 0 to 1.25V
for a zero-to-full-scale regulated output.
DRVN
GOFF1 Negative Linear-Regulator Controller Base-Drive Output. Open drain of an internal
p-channel MOSFET. Connect DRVN to the base of the external npn output transistor as shown
in the typical operating circuit (Figure 1). The buffer can source current from ground to GOFF2
to maintain a regulated voltage on GOFF1 as measured at FBN.
19
DLY2
Positive Charge-Pump Linear-Regulator Delay Input. Connect a capacitor from DLY2 to AGND to
set the delay time between the step-up regulator and the startup of the positive charge pump. An
8FA current source charges CDLY2. DLY2 is internally pulled to AGND until the step-down softstart is finished or when either EN1 or EN2 is low or VL is below its UVLO threshold.
20
FBP
Positive Charge-Pump Linear-Regulator Feedback Input. Connect FBP to the center of a resistive
voltage-divider between the positive charge-pump output and AGND to set the positive chargepump output voltage. Place the resistive voltage-divider within 5mm of FBP.
DRVP
Positive Charge-Pump Linear-Regulator Controller Base-Drive Output. Open drain of an internal
n-channel MOSFET. Connect DRVP to the base of the external pnp transistor as shown in the
typical operating circuit (Figure 1). The buffer can source current from AVDD to the charge-pump
diodes to maintain a regulated voltage on GON as measured at FBP.
22
RESET
Open-Drain Power-Good Output. Monitors the step-down output voltage. RESET is connected to
AGND whenever the internal feedback voltage is less than its power-good threshold and DEL is
less than 1.25V. RESET is high impedance whenever the internal feedback voltage is greater than
the threshold and DEL is greater than 1.25V.
23
DEL
Power-Good Reset Timing Pin. Connect a capacitor from DEL to AGND to set the step-down
output-rising RESET delay. An 8FA current source charges CDEL.
25
SET
GOFF2 Cold-Temperature Reference-Voltage Input. Connect a resistor from SET to AGND to set
the cold-temperature GOFF2 reference level. The SET output current is 100FA (typ). Leave SET
unconnected or connect to 3.3V if GOFF2 temperature compensation is not used.
26
NTC
Thermistor Network Connection Input. Connect a network including a thermistor from NTC to
AGND to control the temperature behavior of the GOFF2 output voltage. If thermal compensation
is not used, NTC may be left unconnected or connected to AGND.
27
FB3
GOFF2 Regulator Feedback Input. FB3 regulates at 1.65V nominal and can vary from 0.1V to
1.65V with temperature according to the voltages on SET and NTC. Connect FB3 to the center of
a resistive voltage-divider between the regulator output and a 3.3V reference to set the GOFF2
regulator output voltage.
28
COMP3
29, 36
N.C.
No Connection. Not internally connected.
30
LX3
GOFF2 Boost-Buck Regulator Switching Node. LX3 is the source of the internal n-channel
MOSFET connected between IN3 and LX3. Connect the inductor and Schottky catch diode to LX3
and minimize the trace area for low EMI.
18
21
Compensation Pin for the Boost-Buck Error Amplifier. Connect a series resistor and capacitor from
COMP3 to AGND. Typical values are 5kI and 4.7nF.
14 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
PIN
NAME
FUNCTION
31
IN3
Boost-Buck Regulator Power Input. Drain of the internal p-channel MOSFET connected between
IN3 and LX3.
32
RHVS
High-Voltage Stress Mode Output. When HVS is high, the RHVS open-drain output connects to
AGND. RHVS is high impedance when HVS is low.
33
FB1
34
COMP1
Compensation Pin for the Step-Up Error Amplifier. Connect a series resistor and capacitor from
COMP1 to AGND. Typical values are 40kI and 330pF.
35
VL
5V Internal Linear-Regulator Output. Bypass VL to AGND with 1FF minimum. Provides power for
the internal MOSFET driving circuits, the PWM controllers, charge-pump regulators, logic and
references, and other analog circuitry. Provides 25mA load current when all switching regulators
are enabled. VL is active whenever IN is above its UVLO threshold.
37, 38
LX1
Step-Up Regulator Switching Node. LX1 is the drain of the internal n-channel MOSFET connected
between LX1 and PGND. Connect the inductor and Schottky catch diode to both LX1 pins and
minimize the trace area for low EMI.
39, 40
GND1
—
EP
Boost Regulator Feedback Input. Connect FB1 to the center of a resistive voltage-divider between
the step-up regulator output and AGND to set the step-up regulator output voltage. Place the
resistive voltage-divider within 5mm of FB1.
Step-Up Regulator Power Ground. Source of the internal power n-channel MOSFET.
Exposed Pad. Connect EP to the ground plane to maximize thermal dissipation.
______________________________________________________________________________________ 15
MAX17122
Pin Description (continued)
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Typical Operating Circuit
The typical operating circuit (Figure 1) of the MAX17122
is a complete power-supply system for TFT LCD TV
panels. The circuit generates a +3.3V logic supply, a
22µF
16V
Q1
IN
12V
C8
22nF
20V
100mI
BST2
LX1
LX1
GND1
GND1
GATE
3A
30V
D2
COMP1
OUTB
FB2
10I
(OPTIONAL)
0.22µF
25V
VL
1µF
10V
RHVS
HVS
IN3
LX3
IN
C2
22µF x 2
25V
RCOMP1
40kI
CCOMP1
330pF
CCOMP1P
10pF
CCOMP3
470pF 3.3V
CCOMP3P
10pF
MAX17122
SET
3.3V
GPGD
N1
R4
22.1kI
RSET
7.5kI
NTC
CDEL
NTC
10kI
VGON
POWER_GOOD
510I
INCP
(AVDD)
47kI
8.2kI
LX1
1µF
25V
DRVN
GOFF1
-7.5V
100mA
DRVP
510I
C6
2.2µF
16V
R7
81.7kI
FBN
VGOFF2
R8
22.1kI
P1
CP
10kI
SS
FBP
GOFF2
-12V ~ -20V
450mA
R3
181kI
RCOMP3
5kI
COMP3
RESET
DEL
R2
33kI
C3
22µF
25V
22µH
1.6A
FB3
AGND
AGND
3.3V
POWER_GOOD
RHVS
324kI
FROM SYSTEM
IN
D3
VL
15V
2.2A
R1
365kI
1A
50V
EN1
EN2
DLY1
DLY2
FROM
SYSTEM
AVDD
3A
30V
FB1
LX2
LX2
4.7µH
3.5A
IN
C1
IN2
IN2
L2
C5
22µF
6.3V
L1
4.7µH
3.5A
D1
0.1µF
16V
C7
22µF
16V
OUTB
2A
+15V source driver supply, a +28V positive gate-driver
supply, and a negative gate-driver supply that is derived
linearly between -7.5V and -12V. Table 1 lists some
selected components and Table 2 lists the contact information of component suppliers.
D4
RP
R5
226kI
C4
1µF
50V
CSS
R6
10.5kI
3.3V
Figure 1. Typical Operating Circuit
16 ��
GON
28V
100mA
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
DESIGNATION
C1, C7
C2, C3
C4
C5
C6
D1, D2
DESCRIPTION
22FF Q20%, 16V X5R ceramic capacitors (1206)
Murata GRM31CR61C226M
Taiyo Yuden EMK316BJ226M
22FF Q20%, 25V X5R ceramic capacitors (1210)
Murata GRM32ER61E226K
Murata GRM32ER61E226M
1FF Q10%, 50V X7R ceramic capacitor
(1206)
Murata GRM31MR71H105KA
TDK C3216X7R1H105K
22FF Q20%, 6.3V X5R ceramic capacitor
(0805)
Murata GRM21BR60J226M
TDK C2012X5R0J226K
2.2FF Q10%, 16V X5R ceramic capacitor
(0603)
Murata GRM188R61C225K
TDK C1608Y5V1C225ZT
DESIGNATION
D3
D4
Small-signal diode (SOT23)
Fairchild BAT54S
Diodes Inc. BAT54S
Inductors, 4.7FH, 3.5A
TOKO FDV0620-4R7M
Sumida CDRH6D26HPNP-4R7P
NEC MPLC0730L4R7
L1, L2
Schottky diodes 30V, 3A (M Flat)
Toshiba CMS02
DESCRIPTION
Schottky diode 50V, 1A (SMA)
Fairchild SS15
Diodes Inc. B150
L3
Inductor, 22FH, 1.6A
Sumida CDRH8D28NP-220N
N1
High-gain, 25V npn transistor (DPAK)
Fairchild KSH200
ON Semi MJD200
P1
High gain, -25V pnp transistor (DPAK)
Fairchild KSH210
ON Semi MJD210
Q1
-30V, 0.056I p-channel MOSFET (6-pin
SC70 PowerPAK)
Vishay SiA421DJ
Table 2. Component Suppliers
SUPPLIER
PHONE
FAX
Diodes Incorporated
805-446-4800
805-446-4850
www.diodes.com
Fairchild Semiconductor
408-822-2000
408-822-2102
www.fairchildsemi.com
Murata Electronics North America, Inc.
770-436-1300
770-436-3030
www.murata-northamerica.com
ON Semiconductor
888-743-7826
—
www.onsemi.com
Sumida Corp.
847-545-6700
847-545-6720
www.sumida.com
TDK Corp.
847-803-6100
847-390-4405
www.component.tdk.com
Toshiba America Electronic Components, Inc.
949-455-2000
949-859-3963
www.toshiba.com/taec
Detailed Description
The MAX17122 is a multiple-output power supply
designed primarily for TFT LCD TV panels. It contains
a step-down switching regulator to generate the supply
for system logic, a step-up switching regulator to generate the supply for source-driver ICs, a linear-controlled
positive charge-pump regulator to generate the supply
for TFT positive gate drivers, a boost-buck regulator, and
a negative linear regulator to generate the supply for TFT
negative gate drivers.
Each switching regulator features adjustable output voltage, digital soft-start, and timer-delayed fault protection.
WEBSITE
They all use fixed-frequency (750kHz) current-mode
control architectures. The step-up regulator switches
in-phase with a boost-buck regulator while 180N out-ofphase with a step-down regulator to minimize the input
ripple and noise coupling.
The boost-buck regulator also features a temperature-compensated output so it can vary according to the temperature sensed by an external NTC thermistor. The step-down
regulator also features an adjustable-delay, open-drain,
power-good output. A simple untimed output monitors the
positive charge-pump linear regulator’s feedback.
______________________________________________________________________________________ 17
MAX17122
Table 1. Component List
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
In addition, the MAX17122 features an internal 5V linear regulator, well-defined power-up and power-down
sequences, and fault and thermal-overload protection.
Figure 2 shows the MAX17122’s functional diagram.
IN
BST2
IN2
AVDD
GATE
MAX17122
VL
LX1
OUTB
STEP-DOWN
OSC
STEP-DOWN
LX2
GND1
FB1
STEPDOWN FB
OUTB
COMP1
HVS
RHVS
FROM
SYSTEM
HVS CONTROL
IN3
150mV
FB2
BOOST-BUCK
VL
VL
VL
FB3
COMP3
AGND
FROM
SYSTEM
3.3V
EN1
EN2
DLY1
DLY2
SS
SET
3.3V
SEQUENCE
STEP-DOWN
FB
FBP
VGON PGOOD
NTC
3.3V
GPGD
RESET
POWER_
GOOD
LX1
VL
DRVN
VGON
POWER_
GOOD
INCP
(AVDD)
3.3V PGOOD
DEL
GOFF1
GOFF2
LX3
IN
IN
IN
DRVP
NEGATIVE REG
POSITIVE REG
GON
FBN
FBP
VGOFF2
3.3V
Figure 2. Functional Diagram
18 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
PWM Controller Block
The heart of the PWM controller block is a multi-input,
open-loop comparator that sums three signals: the output voltage signal with respect to the reference voltage,
the current-sense signal, and the slope compensation
signal. The PWM controller is a direct-summing type,
lacking a traditional error amplifier and the phase shift
associated with it. This direct-summing configuration
approaches ideal cycle-by-cycle control over the output
voltage.
The step-down controller always operates in fixedfrequency PWM mode. Each pulse from the oscillator
sets the main PWM latch that turns on the high-side
switch until the PWM comparator changes state. As the
high-side switch turns off, the low-side switch turns on.
The low-side switch stays on until the beginning of the
next clock cycle.
Current Limiting and Lossless Current Sensing
The current-limit circuit turns off the high-side MOSFET
switch whenever the voltage across the high-side
MOSFET exceeds an internal threshold. The actual
current limit is typically 3A.
For current-mode control, an internal lossless sense
network derives a current-sense signal from the inductor
DCR. The time constant of the current-sense network is
not required to match the time constant of the inductor
and has been chosen to provide sufficient current-ramp
signal for stable operation. The current-sense signal is
AC-coupled into the PWM comparator, eliminating most
DC output-voltage variation with load current.
Dual-Mode Feedback
The MAX17122’s step-down regulator supports both
fixed output and adjustable output. Connect FB2 to
AGND to enable the 3.3V fixed output voltage. Connect
a resistive voltage-divider between OUTB and AGND
with the center tap connected to FB2 to adjust the output
voltage. Choose RB (resistance from FB2 to AGND) to
be between 5kI and 50kI, and solve for RA (resistance
from OUTB to FB2) using the following equation:
V

RA = RB ×  OUTB - 1
 VFB2

where VFB2 = 1.25V and VOUTB may vary from 1.5V to 5V.
Soft-Start
The step-down regulator includes a 7-bit soft-start DAC
that steps its internal reference voltage from 0 to 1.25V in
128 steps. The soft-start period is 3ms (typ) and FB2 fault
detection is disabled during this period. The soft-start
feature effectively limits the inrush current during startup
(see the Step-Down Regulator Soft-Start Waveforms in
the Typical Operating Characteristics).
Step-Down Regulator Power Good (RESET)
The RESET power-good block is an open-drain-type
design with a capacitor-adjustable, active-low, output
timing. The block monitors the step-down regulator feedback node (FB2 in variable mode, or OUTB after divider
in fixed mode) with a 1.0V threshold. The threshold has
a 12mV (typ) hysteresis. RESET goes low when the monitored voltage is below the threshold. When the feedback
node voltage rises above the 1.0V threshold, DEL starts
to charge the capacitor connected there. RESET stays
low until VDEL exceeds 1.25V.
Step-Up Regulator
The step-up regulator employs a current-mode, fixedfrequency PWM architecture to maximize loop bandwidth
and provide fast-transient response to pulsed loads
typical of TFT LCD panel source drivers. The integrated
MOSFET and the built-in digital soft-start function reduce
the number of external components required while controlling inrush currents. The output voltage can be set
from VIN to 20V with an external resistive voltage-divider.
(Note: If the HVS function is used, AVDD cannot be set
to this maximum value under normal operating conditions.) The regulator controls the output voltage and the
power delivered to the output by modulating duty cycle
DSU of the internal power MOSFET in each switching
cycle. The duty cycle of the MOSFET is approximated by:
D SU ≈
VAVDD + VD1 - VIN
VAVDD + VD1 - VLX1
______________________________________________________________________________________ 19
MAX17122
Step-Down Regulator
The step-down regulator consists of an internal n-channel
MOSFET with gate driver, a lossless current-sense network, a current-limit comparator, and a PWM controller
block. The external power stage consists of a Schottky
diode rectifier, an inductor, and output capacitors. The
output voltage is regulated by changing the duty cycle
of the high-side MOSFET. A bootstrap circuit that uses
a 0.1FF flying capacitor between LX2 and BST provides
the supply voltage for the high-side gate driver. Although
the MAX17122 also includes a 10I (typical) low-side
MOSFET, this switch is used to charge the bootstrap
capacitor during startup and maintains fixed-frequency
operation at light load and cannot be used as a synchronous rectifier. An external Schottky diode (D2 in Figure
1) is always required.
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
where VAVDD is the output voltage of the step-up regulator, VD1 is the voltage drop across diode D1, and VLX1
is the voltage drop across the internal MOSFET. Figure 3
shows the step-up regulator block diagram.
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The MOSFET
remains off for the rest of the clock cycle.
Step-Up Regulator External pMOS Pass Switch
As shown in Figure 1, a series external p-channel
MOSFET (Q1) can be installed between the power
supply and inductor L1. This feature is used to sequence
power to AVDD after the MAX17122 has proceeded
through normal startup to limit input surge current during
the output capacitor initial charge, and to provide true
shutdown when the step-up regulator is disabled. When
EN2 is low, GATE is internally pulled up to IN2 through a
25I resistor. Once EN2 is high and the step-down regulator soft-start is finished, DLY1 begins charging. Once
DLY1 is above 1.25V, the GATE starts pulling down with
a 160FA (typ) internal current source. The step-up regulator is enabled and initiates a soft-start routine. When
the gate-source voltage of this external pMOS exceeds
approximately 3V, a boost current of 1mA is added to
quickly complete the charge of GATE capacitance. The
external p-channel MOSFET (Q1) turns on and connects
IN2 to step-up regulator power inductor L1 when GATE
falls below the turn-on threshold of the MOSFET. When
VGATE reaches VIN2 - 5.5V(GATE_OK), LX1 is allowed
to toggle.
PWM Controller Block
An error amplifier compares the signal at FB1 to
1.25V and changes the COMP1 output. The voltage
at COMP1 sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP1 output accordingly to produce the inductor peak
current necessary to service the load. To maintain
stability at high duty cycles, a slope-compensation signal is summed with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The
current through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the currentfeedback signal and the slope-compensation exceed
the COMP1 voltage, the controller resets the flip-flop
and turns off the MOSFET. Since the inductor current is
continuous, a transverse potential develops across the
inductor that turns on diode D1. The voltage across the
inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp back
LX1
CLOCK
LOGIC AND
DRIVER
GND1
ILIM
COMPARATOR
+
-
SOFTSTART
ILIMIT
SLOPE COMP
750kHz
OSCILLATOR
PWM
COMPARATOR
+
CURRENT
SENSE
TO FAULT LOGIC
FAULT +
COMPARATOR
ERROR
AMP
FB1
+
1.25V
COMP1
Figure 3. Step-Up Regulator Block Diagram
20 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
When not using this feature, leave GATE high impedance, and connect IN2 to the step-up regulator power
inductor (L1) directly.
Soft-Start
The step-up regulator achieves soft-start by linearly
ramping up its internal current limit. Connect a soft-start
capacitor (CSS) of at least 1nF between SS and AGND.
The SS pin voltage initially follows the FB1 pin voltage.
Once the GATE pin voltage reaches the GATE_OK
threshold (typically VIN - 5.5V), CSS is charged by a
10FA constant current. The soft-start terminates when
the SS pin voltage reaches 1.25V. Calculate CSS with the
following equation:
C SS = t SS ×
10FA
1.25V
where tSS is the desired soft-start duration. The soft-start
feature effectively limits the inrush current during startup
(see the Step-Up Regulator Soft-Start Waveforms in the
Typical Operating Characteristics).
Positive Charge-Pump Power Good (GPGD)
The GPGD power-good block is an open-drain type
design. The block monitors the positive charge-pump
feedback FBP with a 1.15V threshold. The threshold has
a 125mV (typ) hysteresis. GPGD goes low when FBP is
below the threshold.
Positive Charge-Pump Linear Regulator
The positive linear regulator controller is an analog gain
block with an open-drain n-channel output. It drives an
external pnp pass transistor (P1) with a 510I base-toemitter resistor. Its guaranteed base-drive sink current is
at least 10mA. The output voltage is set with an external
resistive voltage-divider from the charge-pump output to
AGND, with the midpoint connected to FBP. The regulator in Figure 1 uses a 1FF ceramic output capacitor
and is designed to deliver 100mA at 28V. Other output
voltages and currents are possible with the proper pass
transistor, output capacitor, number of charge-pump
stages, and the setting of the feedback divider. The positive charge-pump regulator output (VGON) is typically
used to generate the positive supply rail for the TFT LCD
gate-driver ICs.
The regulator utilizes the step-up regulator switching
node (LX1) to toggle the charge-pump flying capacitor.
Therefore, to have a good output regulation, it requires
LX1 to toggle with a known duty cycle. In other words,
the step-up regulator needs to be working in continuous
mode. The regulator achieves its loop control by limiting the current available through P1 to charge the flying
capacitor (CFLY). This topology eliminates the high-voltage stress on the DRVP pin. However, flying capacitor
charging-current pulses could cause early termination
of the step-up regulator switching pulses and cause
unstable performance of the step-up regulator. A small
resistor (RP) in series with charging diode D4 can reduce
the magnitude of these current pulses and prevent this
behavior. The value of this small resistor is determined
by the available headroom loss.
The positive linear regulator is enabled after the stepdown regulator finishes its soft-start and EN2 is pulled
high. Each time it is enabled, the regulator goes through
a soft-start routine by ramping up its internal reference
voltage from 0 to 1.25V in 128 steps. The soft-start period
is 3ms (typ) and FBP fault detection is disabled during
this period. The soft-start feature effectively limits the
inrush current during startup.
Negative Linear Regulator
The negative linear-regulator controller is an analog gain
block with an open-drain p-channel output. It drives an
external npn pass transistor (N1) with a 510I baseto-emitter resistor. Its guaranteed base-drive source
current is at least 10mA. The output voltage is set with
an external resistive voltage-divider from its output to
3.3V reference with the midpoint connected to FBN. The
regulator in Figure 1 uses a 1FF ceramic output capacitor and is designed to deliver 100mA at -7.5V. Other output voltages and currents are possible with the proper
pass transistor, output capacitor, and the setting of the
feedback divider. The negative linear-regulator output
(GOFF1) is typically used to linearly derive a negative
gate-driver supply between the boost-buck regulator’s
output GOFF2 and ground.
The negative linear regulator is enabled after the stepdown regulator finishes its soft-start and EN2 is pulled high.
______________________________________________________________________________________ 21
MAX17122
Since this is an open-loop control, gate-drain capacitor,
C8 is always required to reduce the inrush current during
startup; 22nF is suitable for this purpose.
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Temperature-Compensated
Boost-Buck Regulator
The boost-buck regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast-transient response to pulsed
loads typical of TFT LCD panel source drivers. The integrated MOSFET and the built-in digital soft-start function
reduce the number of external components required
while controlling inrush currents. The maximum negative
output voltage can be set to -36V relative to VIN3 with
an external resistive voltage-divider. The regulator controls the output voltage and the power delivered to the
output by modulating duty cycle D of the internal power
MOSFET in each switching cycle. The duty cycle of the
MOSFET is approximated by:
D BB ≈
-VGOFF2 + VD3
VIN3 + VD3 - VGOFF2 - VLX3
where VGOFF2 is the output voltage of the boost-buck
regulator, VD3 is the voltage drop across diode D3, and
VLX3 is the voltage drop across the internal MOSFET.
PWM Control Block
An error amplifier compares the signal at FB3 to a
reference voltage, which is determined by temperaturecompensation logic, and changes the COMP3 output.
The voltage at COMP3 sets the peak inductor current.
As the load varies, the error amplifier sources or sinks
current to the COMP3 output accordingly to produce
the inductor peak current necessary to service the load.
To maintain stability at high duty cycles, a slopecompensation signal is summed with the current-sense
signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the p-channel MOSFET and
applying the input voltage across the inductor. The
current through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the currentfeedback signal and the slope compensation exceed
the COMP3 voltage, the controller resets the flip-flop
and turns off the MOSFET. Since the inductor current
is continuous, a transverse potential develops across
the inductor that turns on diode D3. The voltage across
the inductor then becomes the negative output voltage.
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
Temperature Compensation
The GOFF2 boost-buck regulator output varies with temperature to compensate for lower TFT mobility at cold
temperatures. The output voltage is typically -12V at
+25NC and warmer, and -20V at 0NC and colder, with a
gradual change between +25NC and 0NC.
The circuit involves two constant voltages and one temperature-dependent voltage. The first constant voltage is
internally fixed at half of 3.3V (1.65V). The other constant
voltage should be less than 1.65V and is chosen by connecting resistor RSET from the 100FA current source at
the SET pin to AGND. The temperature-dependent voltage is developed by the network attached to the 100FA
current source at the NTC pin. The NTC voltage is subtracted from the 3.3V reference to provide the variable
voltage with the correct temperature slope.
If the differential voltage between the 3.3V reference
and the NTC pin is greater than 1.65V, then the 1.65V
voltage is used as the reference for the error amplifier at
FB3. This sets the warm-range output of the boost-buck
regulator. If the differential voltage between 3.3V
reference and the NTC pin is less than the voltage at
the SET pin, then the SET pin voltage is used as the
reference for the error amplifier at FB3. This sets the
cool-range output of the boost-buck regulator. If neither
is true, then the differential voltage itself is used as the
reference for the error amplifier at FB3.
These conditions are mutually exclusive as long as the
SET pin voltage is less than 1.65V. If the SET pin voltage is greater than 1.65V, which would be true if SET
was left open, then 1.65V is used as the reference for
the error amplifier at FB3 regardless of the differential
voltage between 3.3V reference and the NTC pin. This
ensures a defined behavior of operation and provides
a “disable” mode for the function. The minimum voltage
on SET is 0.1V.
The thermistor network and resistor on SET can be
adjusted to program almost any temperature variation
desired, limited to two output levels with a smooth transition between. Figure 4 shows the block diagram of the
temperature-compensation function and Figure 5 shows
the reference voltages and output voltage behavior for
the typical application components.
22 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
+
1.65V
R
3.3V
REFERENCE
+
-
1.65V TO
0.1V
+
1.65V
100µA
100µA
EA
+
NTC
1.65V
SET
-
FB3
3.3V
RSET
NTC
10kI
GOFF2
R4
R3
Figure 4. Switching Frequency vs. RFOSC
GOFF2(FB3) VOLTAGE
vs. TEMPERATURE
0
2.94
GOFF2 VOLTAGE (V)
WARM LEVEL
(FB3 = 1.65V)
-10
1.85
-15
1.31
TRANSITION LEVEL
(FB3 = 3.3V - NTC VOLTAGE)
-20
COLD LEVEL
(FB3 = SET VOLTAGE)
-25
-50
-25
0
25
50
TEMPERATURE (°C)
Figure 5. Compensation Network
75
0.76
0.22
100
FB3 VOLTAGE (V)
2.40
-5
Soft-Start
The boost-buck regulator includes a 7-bit soft-start
DAC that steps its internal reference voltage from 3.3V
to the reference voltage determined by temperaturecompensation logic in 128 steps. The soft-start period
is 3ms (typ) and FB3 fault detection is disabled during this period. The soft-start feature effectively limits
the inrush current during startup (see the Boost-Buck
Regulator Soft-Start Waveforms in the Typical Operating
Characteristics).
Linear Regulator (VL)
The MAX17122 includes an internal linear regulator. IN is
the input of the linear regulator. The input voltage range
is between 8V and 16.5V. The output voltage is set to 5V.
The regulator powers the internal MOSFET drivers, PWM
controllers, charge-pump regulators, and logic circuitry.
The total external load capability is 25mA. Bypass VL to
AGND with a minimum 1FF ceramic capacitor.
______________________________________________________________________________________ 23
MAX17122
-
R
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Power-Up Sequence
The step-down regulator starts up when the MAX17122’s
internal linear-regulator output VL is above its undervoltage lockout (UVLO) threshold and EN1 is high. Figure
6 shows the power-up sequence. Once the step-down
regulator soft-start is done, the FB2 fault-detection circuit
is enabled. The step-down regulator power-good timing
control signal (DEL) is enabled after OUTB is above its
designed threshold (see the Step-Down Regulator Power
Good (RESET) section). Once DEL passes above 1.25V,
RESET is passively pulled up high through a resistor. Set
the delay time using the following equation:
C DEL = DELAY_TIME ×
8FA
1.25V
The negative linear regulator and the boost-buck regulator are enabled after the step-down regulator finishes its
soft-start and EN2 is high. In the same time, both of the
delay control signals (DLY1 and DLY2) for the step-up
regulator and the positive charge-pump linear regulator
are also enabled.
VIN UVLO
IN, IN2, IN3
VL
EN1
OUTB
tSS
DEL
RESET
1.25V
TIME
VOFF1
GOFF2
tSS
EN2
DLY1
DLY2
1.25V
TIME
GON
AVDD
GATEOK
GATE
SS
1.25V
tSS
tSS
TIME
Figure 6. Power-Up Sequence
24 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
The positive charge-pump linear regulator is enabled
after the step-up regulator finishes its soft-start and DLY2
is above 1.25V. The FBP fault-detection circuit is enabled
after the positive linear regulator finishes its soft-start.
Fault Protection
During steady-state operation, if any of the five regulators’ output (step-down regulator, step-up regulator,
positive linear regulator, boost-buck regulator, and
gate-off linear regulator) goes lower than its respective
fault-detection threshold, the MAX17122 activates an
internal fault timer. If any condition, or the combination
of conditions, indicates a continuous fault for the faulttimer duration (50ms typ), the MAX17122 shuts down
temporarily for approximately 160ms (typ) and then
restarts. During restart, if any output voltage is below its
fault threshold at the end of its soft-start period, the IC
immediately shuts down again. This feature is only active
after a fault shutdown has occurred. It does not apply to
the initial startup, where the 50ms timer always applies.
Once all outputs have started properly after a restart, the
50ms fault timer is reenabled. The IC restarts indefinitely
for a continuous fault condition and never shuts down
permanently or waits for power cycling.
If a short to ground occurs on the step-down regulator,
step-up regulator, positive linear regulator, or boostbuck regulator, no fault timer is applied and the IC immediately shuts down. No harm occurs if the gate-off linear
regulator is shorted to ground, so this feature is omitted
for that output.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the MAX17122.
When the junction temperature exceeds TJ = +160NC, a
thermal sensor immediately activates the fault protection,
which shuts down all the outputs. Cycle the input voltage
to clear the fault latch and restart the MAX17122.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature rating of TJ = +150NC.
Design Procedure
Step-Down Regulator
Inductor Selection
Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance
(RDC). The following equation includes a constant (LIR),
which is the ratio of peak-to-peak inductor ripple current
to DC load current. A higher LIR value allows smaller
inductance, but results in higher losses and higher
ripple. A good compromise between size and losses is
typically found at a 30% ripple-current-to-load-current
ratio (LIR = 0.3), which corresponds to a peak inductor
current 1.15 times the DC load current:
L2 =
VOUTB × (VIN2 - VOUTB )
VIN2 × fSW × IOUTB(MAX) × LIR
where IOUTB(MAX) is the maximum DC load current,
and the switching frequency (fSW) is 750kHz. The exact
inductor value is not critical and can be adjusted to make
trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase
the output ripple and reduce the efficiency due to higher
peak currents. On the other hand, higher inductor values
increase efficiency, but at some point resistive losses
due to extra turns of wire will exceed the benefit gained
from lower AC current levels.
The inductor’s saturation current must exceed the peak
inductor current. The peak current can be calculated by:
V
× (VIN2 - VOUTB )
IOUTB_RIPPLE = OUTB
fSW × L 2 × VIN2
I
IOUTB_PEAK = IOUTB(MAX) + OUTB_RIPPLE
2
The inductor’s DC resistance should be low for good
efficiency. Find a low-loss inductor having the lowest
possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice. Shieldedcore geometries help keep noise, EMI, and switching
waveform jitter low.
______________________________________________________________________________________ 25
MAX17122
GATE is resistively pulled up towards IN2 during initial
startup. Once DLY1 passes above 1.25V, a 160FA
current source starts to pull down on GATE, turning on
external pMOS switch Q1 and enabling the step-up
regulator. When VGATE reaches its GATE_OK threshold
(VIN - 5.5V), the step-up regulator switch is allowed to
toggle. A 10FA current source charges the SS capacitor
pin and when the SS voltage reaches 1.25V, soft-start is
done. The FB1 fault-detection circuit is enabled after the
step-up regulator finishes its soft-start.
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Considering the typical operating circuit in Figure 1, the
maximum load current IOUT(MAX) is 2.0A with a 3.3V
output and a 12V (typ) input voltage. Choosing an LIR of
0.4 at this operation point:
L2 =
3.3V × (12V - 3.3V)
≈ 5.3FH
12V × 750kHz × 2A × 0.3
Pick L2 = 4.7FH. At that operation point, both the ripple
current and peak current are:
IOUTB_RIPPLE =
3.3V × (12V - 3.3V)
750kHz × 4.7FH × 12V
IOUTB_PEAK = 2A +
= 0.68A
0.68A
= 2.34A
2
Input Capacitors
The input filter capacitors reduce peak currents drawn
from the power source and reduce noise and voltage
ripple on the input caused by the regulator’s switching.
They are usually selected according to input ripplecurrent requirements and voltage rating, rather than
capacitance value. The input voltage and load current
determine the RMS input ripple current (IRMS):
IRMS = IOUTB ×
VOUTB × (VIN2 - VOUTB )
VIN2
The worst case is IRMS = 0.5 O IOUTB, which occurs at
VIN2 = 2 O VOUT.
For most applications, ceramic capacitors are used
because of their high-ripple-current and surge-current
capabilities. For optimal circuit long-term reliability,
choose an input capacitor that exhibits less than +10NC
temperature rise at the RMS input current corresponding
to the maximum load current.
Output Capacitor Selection
Since the MAX17122’s step-down regulator is internally
compensated, it is stable with any reasonable amount
of output capacitance. However, the actual capacitance
and ESR affect the regulator’s output-voltage ripple
and transient response. The rest of this section deals
with how to determine the output capacitance and ESR
needs according to the ripple voltage and load-transient
requirements.
The output-voltage ripple has two components: variations in the charge stored in the output capacitor, and
the voltage drop across the capacitor’s ESR caused by
the current into and out of the capacitor:
VOUTB_RIPPLE = VOUTB_RIPPLE(ESR) + VOUTB_RIPPLE(C)
VOUTB_RIPPLE(ESR) = IOUTB_RIPPLE × R ESR_OUTB
VOUTB_RIPPLE(C) =
IOUTB_RIPPLE
8 × C OUTB × fSW
where IOUTB_RIPPLE is defined in the Step-Down
Regulator and Inductor Selection sections, COUTB (C5
in Figure 1) is the output capacitance, and RESR_OUTB
is the ESR of output capacitor COUT. In Figure 1’s circuit,
the inductor ripple current is 0.68A. If the voltage-ripple
requirement of Figure 1’s circuit is Q1% of the 3.3V output, then the total peak-to-peak ripple voltage should
be less than 66mV. Assuming that the ESR ripple and
the capacitive ripple each should be less than 50% of
the total peak-to-peak ripple, then the ESR should be
less than 48.5mI and the output capacitance should
be greater than 3.4FF to meet the total ripple requirement. A 22FF capacitor with ESR (including PCB trace
resistance) of 10mI is selected for the typical operating
circuit in Figure 1, which easily meets the voltage-ripple
requirement.
The step-down regulator’s output capacitor and ESR
also affect the voltage undershoot and overshoot when
the load steps up and down abruptly. The undershoot
and overshoot also have two components: the voltage
steps caused by ESR and voltage sag, and soar due to
the finite capacitance and inductor slew rate. Use the
following formulas to check if the ESR is low enough
and the output capacitance is large enough to prevent
excessive soar and sag.
The amplitude of the ESR step is a function of the load
step and the ESR of the output capacitor:
VOUTB_ESR_STEP = ∆IOUTB × R ESR_OUTB
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle:
VOUTB_SAG =
L 2 × (∆IOUTB ) 2
(
2 × C OUTB × VIN2(MIN) × D MAX - VOUTB
26 ��
)
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
VOUTB_SOAR =
L 2 × (∆IOUTB ) 2
2 × C OUTB × VOUTB
Given the component values in the circuit of Figure 1,
during a full 2A step load transient, the voltage step due
to capacitor ESR is negligible. The voltage sag and soar
are 138mV and 129mV, respectively.
Rectifier Diode
The MAX17122’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 3A Schottky diode
works well in the MAX17122’s step-down regulator.
Step-Up Regulator
Inductor Selection
The inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor.
These factors influence the converter’s efficiency, maximum output-load capability, transient-response time,
and output-voltage ripple. Physical size and cost are
also important factors to be considered.
The maximum output current, input voltage, output voltage, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple and therefore reduce the peak current, which
decreases core losses in the inductor and I2R losses in
the entire power path. However, large inductor values
also require more energy storage and more turns of wire,
which increase physical size and can increase I2R losses in the inductor. Low inductance values decrease the
physical size but increase the current ripple and peak
current. Finding the best inductor involves choosing the
best compromise between circuit efficiency, inductor
size, and cost.
The equations used here include a constant (LIR), which
is the ratio of the inductor peak-to-peak ripple current to the average DC inductor current at the full load
current. The best trade-off between inductor size and
circuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and ratio
of inductor resistance to other power-path resistances,
the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extremely
thin high-resistance inductors are used, as is common
for LCD panel applications, the best LIR can increase to
between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
Calculate the approximate inductor value using the
typical input voltage (VIN), the maximum output current (IAVDD(MAX)), the expected efficiency (ETYP) taken
from an appropriate curve in the Typical Operating
Characteristics, and an estimate of LIR based on the
above discussion:
 VIN 
L1 = 

 VAVDD 
2
VAVDD - VIN  η TYP 


 I AVDD(MAX) × fSW  LIR 


Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
at the minimum input voltage VIN(MIN) using conservation of energy and the expected efficiency at that operating point (EMIN) taken from an appropriate curve in the
Typical Operating Characteristics:
IIN(DC,MAX) =
I AVDD(MAX) × VAVDD
VIN(MIN) × η MIN
Calculate the ripple current at that operating point and
the peak current required for the inductor:
I AVDD_RIPPLE =
(
VIN(MIN) × VAVDD - VIN(MIN)
L AVDD × VAVDD × fSW
)
I
I AVDD_PEAK = IIN(DC,MAX) + AVDD_RIPPLE
2
The inductor’s saturation current rating and the MAX17122’s
LX1 current limit should exceed IAVDD_PEAK and the
inductor’s DC current rating should exceed IIN(DC,MAX).
For good efficiency, choose an inductor with less than
0.1I series resistance.
Considering the typical operating circuit in Figure 1, the
maximum load current (IAVDD(MAX)) is 2.2A with a 15V
output and a typical input voltage of 12V. Choosing an
LIR of 0.3 and estimating efficiency of 90% at this operating point:
2
 12V   15V - 12V  90% 
L1 = 
 

 = 3.49FH
 15V   2.2A × 750kHz  0.3 
______________________________________________________________________________________ 27
MAX17122
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor value,
and the output voltage:
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Using the circuit’s minimum input voltage under normal
operation (12V) and estimating efficiency of 85% at that
operating point:
IIN(DC,MAX) =
2.2A × 15V
≈ 3.235A
12V × 85%
The ripple current and the peak current are:
I AVDD_RIPPLE =
12V × (15V - 12V)
4.7FH × 15V × 750kHz
I AVDD_PEAK = 3.235A +
≈ 0.68A
0.68A
≈ 3.575A
2
Output Capacitor Selection
The total output-voltage ripple has two components: the
capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due
to the capacitor’s ESR:
VAVDD_RIPPLE = VAVDD_RIPPLE(C) + VAVDD_RIPPLE(ESR)
V
I
-V 
VAVDD_RIPPLE(C) ≈ AVDD  AVDD IN 
C AVDD  VAVDDfSW 
and:
VAVDD_RIPPLE(ESR) ≈ I AVDD_PEAKR ESR_AVDD
where IAVDD_PEAK is the peak inductor current (see
the Inductor Selection section). For ceramic capacitors, the output voltage ripple is typically dominated by
VAVDD_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be considered. Note that all ceramic capacitors typically have
large temperature coefficient and bias voltage coefficients. The actual capacitor value in circuit is typically
significantly less than the stated value.
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input supply and reduces noise injection into
the IC. A 22FF ceramic capacitor is used in the typical
operating circuit (Figure 1) because of the high source
impedance seen in typical lab setups. Actual applications usually have much lower source impedance since
the step-up regulator often runs directly from the output
of another regulated supply. Typically, the input capacitance can be reduced below the values used in the typical operating circuit.
Rectifier Diode
The MAX17122’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 3A Schottky diode
complements the internal MOSFET well.
Output Voltage Selection
The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider
from the output (VAVDD) to AGND with the center tap
connected to FB1 (see Figure 1). Select R2 in the 10kI
to 50kI range. Calculate R1 with the following equation:
V

R1 = R2 ×  AVDD - 1
 VFB1

where VFB1, the step-up regulator’s feedback set point,
is 1.25V. Place R1 and R2 close to the IC.
HVS Function
When HVS exceeds its logic-high threshold, RHVS connects to AGND, effectively placing RHVS in parallel with
the low-side resistor-divider (R2) and regulates VAVDD to
a higher voltage VAVDD(HIGH). Connect the HVS pin to
ground to disable this function. Calculate RHVS with the
following equation:
R1× R2
R HVS =
 VAVDD(HIGH) 
R2
- 1 - R1
VFB1


Loop Compensation
Choose RCOMP1 to set the high-frequency integrator
gain for fast-transient response. Choose CCOMP1 to set
the integrator zero to maintain loop stability. Add a small
capacitor (CP1) from COMP1 to AGND to reduce jitter
and improve stability. Usually 10pF is enough for this
purpose.
For low-ESR output capacitors, use the following equations to obtain stable performance and good transient
response:
R COMP1 ≈
100 × VIN × VAVDD × C AVDD
L AVDD × I AVDD(MAX)
C COMP1 ≈
VAVDD × C AVDD
10 × I AVDD(MAX) × R COMP
To further optimize transient response, vary RCOMP1 in
20% steps and CCOMP1 in 50% steps while observing
transient-response waveforms.
28 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Inductor Selection
The inductance value, peak current rating, and series
resistance are factors to consider when selecting the
inductor. These factors influence the converter’s efficiency, maximum output-load capability, transient-response
time, and output-voltage ripple. Physical size and cost
are also important factors to be considered.
The maximum output current, input voltage, output voltage, and switching frequency determine the inductor
value. Very high inductance values minimize the current ripple and therefore reduce the peak current, which
decreases core losses in the inductor and I2R losses in
the entire power path. However, large inductor values also
require more energy storage and more turns of wire, which
increase physical size and can increase I2R losses in the
inductor. Low inductance values decrease the physical
size but increase the current ripple and peak current.
Finding the best inductor involves choosing the best compromise between circuit efficiency, inductor size, and cost.
The equations used here include a constant (LIR), which
is the ratio of the inductor peak-to-peak ripple current to the average DC inductor current at the full load
current. The best trade-off between inductor size and
circuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and ratio
of inductor resistance to other power-path resistances,
the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extremely
thin high-resistance inductors are used, as is common
for LCD panel applications, the best LIR can increase to
between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
Calculate the approximate inductor value using the
typical input voltage (VIN3), the typical output voltage
(VGOFF2), the maximum output current (IVOFF2(MAX)),
the assumed efficiency (ETYP) of 85%, and an estimate
of LIR based on the above discussion:
L3 =
VIN3 (-VGOFF2 )
η TYP
I VOFF2(MAX)fSW (VIN3 - VGOFF2 ) LIR
Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC inductor
current at the minimum input voltage VIN3(MIN) and cold
temperature output voltage (VGOFF2_COLD) using conservation of energy and the expected efficiency at that
operating point (EMIN) taken from an appropriate curve
in the Typical Operating Characteristics:
IL3(DC,MAX) =
IGOFF2(MAX) × (-VGOFF2_COLD )
VIN3(MIN) × η MIN
Calculate the ripple current at that operating point and
the peak current required for the inductor:
-VIN3VGOFF2_COLD
IGOFF2_RIPPLE =
L 3 (VIN3 − VGOFF2_COLD )fSW
I
IGOFF2_PEAK = IL3(DC,MAX) + GOFF2_RIPPLE
2
The inductor’s saturation current rating and the MAX17122’s
LX3 current limit should exceed IGOFF2_PEAK and the
inductor’s DC current rating should exceed IL3(DC,MAX).
For good efficiency, choose an inductor with less than
0.1I series resistance.
Considering the typical operating circuit in Figure 1, the
maximum load current (IGOFF2(MAX)) is 450mA with a
-12V typical output and a typical input voltage of 12V.
The estimated efficiency is 85% at this operating point.
Because the inductor is large, so is the series resistance;
choose an LIR of 0.5 to minimize power loss:
L3 =
12V × 12V
85%
= 30FH
0.45A × 750kHz × (12V + 12V) 0.5
A 22FH inductor is used in the typical operating circuit (Figure 1). Using the circuit’s minimum input voltage (8V), cold-temperature output voltage (-20V), and
estimating efficiency of 85% at that operating point:
IL3(DC,MAX) =
450mA × 20V
≈ 1.32A
8V × 85%
The ripple current and the peak current are:
IGOFF2_RIPPLE =
12V × 20V
≈ 0.46A
22FH × (12V + 20V) × 750kHz
IGOFF2_PEAK = 1.32A +
0.46A
≈ 1.55A
2
______________________________________________________________________________________ 29
MAX17122
Temperature-Compensated
Boost-Buck Regulator
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Output Capacitor Selection
The total output-voltage ripple has two components: the
capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due
to the capacitor’s ESR:
VGOFF2_RIPPLE = VGOFF2_RIPPLE(C)
+ VGOFF2_RIPPLE(ESR)
I
(-VGOFF2 )
VGOFF2_RIPPLE(C) ≈ GOFF2 ×
C GOFF2 fSW (VIN3 - VGOFF2 )
and:
VGOFF2_RIPPLE(ESR) ≈ IGOFF2_PEAKR ESR_AVDD
where IGOFF2_PEAK is the peak inductor current (see
the Inductor Selection section). For ceramic capacitors, the output-voltage ripple is typically dominated by
VGOFF2_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be
considered. Note that all ceramic capacitors typically
have large temperature coefficient and bias voltage
coefficients. The actual capacitor value in the circuit is
typically significantly less than the stated value.
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input supply and reduces noise injection into
the IC. A 10FF ceramic capacitor is used in the typical
operating circuit (Figure 1) because of the high source
impedance seen in typical lab setups. Actual applications usually have much lower source impedance since
the step-up regulator often runs directly from the output
of another regulated supply. Typically, the input capacitance can be reduced below the values used in the typical operating circuit.
Rectifier Diode
The MAX17122’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 1A Schottky diode
complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the step-up regulator is temperature
compensated. From the warm temperature range ((3.3V
- VNTC) > 1.65V), the output voltage is set by connecting
a resistive voltage-divider from the output (VGOFF2) to
the 3.3V reference with the center tap connected to FB3
(see Figure 1). Select R4 in the 10kI to 50kI range.
Calculate R3 with the following equation:
V
-V
R3 = R4 × GOFF2_WARM FB3
VFB3 - 3.3V
where VFB3, the step-up regulator’s feedback set point,
is 1.65V. Place R3 and R4 close to the IC.
For cold temperatures ((3.3V - VNTC) < VSET), the output
voltage is set by:
VSET =
R4 × VGOFF2_COLD + R3 × 3.3V
R3 + R4
If the above calculated VSET voltage is larger than
1.65V, then temperature compensation is disabled and
the boost-buck regulator output is VGOFF2_WARM at all
temperatures.
Calculate the SET pin resistor RSET as follows:
R SET =
VSET
100FA
The temperature-compensation network is usually a
thermistor in series with a resistor as in Figure 1. A
parallel resistor is often added to linearize the network’s
resistance-temperature characteristic.
Loop Compensation
Choose RCOMP3 to set the high-frequency integrator
gain for fast-transient response. Choose CCOMP3 to set
the integrator zero to maintain loop stability. Typically, a
low bandwidth is expected for normal operation. In that
case, choosing CCOMP3 = 4.7nF and RCOMP3 between
1kI and 5kI gives a good combination of stability and
startup timing. Using greater than 4.7nF for CCOMP3
can cause an excessive startup delay due to the time
required to charge CCOMP3.
Positive Charge-Pump Linear Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest number
of charge-pump stages that meet the output requirement.
The number of positive charge-pump stages is given by:
V
+ VPNP - VAVDD
n POS = GON
VAVDD - 2 × VD
where nPOS is the number of positive charge-pump
stages, VGON is the output of the positive charge-pump
30 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
The previous equation is derived based on the assumption that the first stage of the positive charge pump is
connected to VAVDD. Sometimes fractional stages are
more desirable for better efficiency. This can be done
by connecting the first stage to another available supply
VINCP. If the first charge-pump stage is powered from
VINCP, then the previous equation becomes:
V
+ VPNP - VINCP
n POS = GON
VAVDD - 2 × VD
Flying Capacitors
Increasing the flying capacitor CFLY (connected to
LX1) value lowers the effective source impedance and
increases the output-current capability. Increasing the
capacitance indefinitely has a negligible effect on output
current capability because the internal switch resistance
and diode impedance place a lower limit on the source
impedance. A 0.1FF ceramic capacitor works well in
most low-current applications. The flying capacitor’s voltage rating must exceed the following:
VCFLY > n POS × VAVDD
where nPOS is the number of stages in which the
flying capacitor appears. It is the same as the number of
charge-pump stages.
Charge-Pump Output Capacitor
Increasing the output capacitance, or decreasing the
ESR, reduces the output-voltage ripple and the peakto-peak transient voltage. With ceramic capacitors, the
output-voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
C GON ≥
IGON
2 × fSW × VRIPPLE_GON
where CGON is the output capacitor of the charge pump, IGON
is the load current of the charge pump, and VRIPPLE_GON is
the peak-to-peak value of the output ripple.
Output-Voltage Selection
Adjust the charge-pump regulator’s output voltage by
connecting a resistive voltage-divider from the VGON
output to AGND with the center tap connected to FBP
(Figure 1). Select the lower resistor of divider R6 in the
10kI to 30kI range. Calculate upper resistor R5 with the
following equation:
V

R5 = R6 ×  GON - 1
V
 FBP 
where VFBP = 1.25V (typical).
Charge-Pump Rectifier Diodes
Use low-cost silicon switching diodes with a current
rating equal to or greater than two times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
Schottky diodes with an equivalent current rating. A
small resistor (RP) in series with charging diode D4 is
usually required to reduce the magnitude of the current
pulses into the step-up regulator switching node LX,
which can cause its current mode control to terminate
LX1 pulses too early. The value of this small resistor is
determined by the available charge-pump headroom
according to the following question:
VHEADROOM = I CP × R P
where ICP is the charging current and RP is the series
resistor. Normally, a 2I to 5I resistor is sufficient for this
purpose.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (hFEP), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
V
I CP(MAX) = (IDRVP - BEP ) × h FEP(MIN)
R BEP
where IDRVP is the minimum guaranteed base-drive
current, VBEP is the pnp transistor’s base-to-emitter forward-voltage drop, and RBEP is the pullup resistor connected between the pnp transistor’s base and emitter.
Furthermore, the transistor’s current gain increases the
linear regulator’s DC loop gain so excessive gain destabilizes the output. Therefore, transistors with current gain
over 100 at the maximum output current can be difficult
to stabilize and are not recommended unless the high
gain is needed to meet the load-current requirements.
______________________________________________________________________________________ 31
MAX17122
regulator, VAVDD is the step-up regulator output and is
also the supply voltage of the charge-pump regulators,
VD is the forward voltage drop of charge-pump diode D4,
and VPNP is the voltage across the pnp transistor P1 emitter and collector. For a doubler configuration, nPOS = 1.
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage differential that the regulator can support. Also, the
package’s power dissipation limits the usable maximum
input-to-output voltage differential. The maximum powerdissipation capability of the transistor’s package and
mounting must exceed the actual power dissipated in
the device. The power dissipated equals the maximum
charge current (ICP_DC(MAX)) multiplied by the maximum input-to-output voltage differential:
where IDRVN is the minimum guaranteed base-drive
current, VBEN is the npn transistor’s base-to-emitter forward voltage drop, and RBEN is the pullup resistor connected between the npn transistor’s base and emitter.
Furthermore, the transistor’s current gain increases the
linear regulator’s DC loop gain, so excessive gain destabilizes the output. Therefore, transistors with current gain
over 100 at the maximum output current can be difficult
to stabilize and are not recommended unless the high
gain is needed to meet the load-current requirements.
P = I CP_DC(MAX) × VPNP
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator can support. Also, the
package’s power dissipation limits the usable maximum
input-to-output voltage differential. The maximum powerdissipation capability of the transistor’s package and
mounting must exceed the actual power dissipated in
the device. The power dissipated equals the maximum
load current (IGOFF1(MAX)) multiplied by the maximum
input-to-output voltage differential:
where VPNP is the voltage across the pnp emitter and
collector and can be calculated as:
VPNP = VINCP - (VGON - η POS (VAVDD - 2VD ))
where ICP_DC(MAX) is the maximum average DC input current of the pnp pass transistor and can be estimated as:
I CP_DC(MAX) ≈
VGON + VD
× ILOAD
VGON - η POS (VAVDD - 2VD ) + VD
where ILOAD is the charge pump average DC load current.
A collector capacitor (CP) can increase the current injection to the step-up regulator switching node, LX1, and
should be avoided unless stable operation of the charge
pump cannot be achieved otherwise. If installed, the
capacitor value should be 0.1FF.
Negative Linear Regulator
Output-Voltage Selection
Adjust the negative linear-regulator output voltage
(GOFF1) by connecting a resistive voltage-divider from
VGOFF1 to 3.3V with the center tap connected to
FBN (Figure 1). Select R8 in the 20kI to 50kI range.
Calculate R7 with the following equation:
V
-V
R7 = R8 × GOFF1 FBN
VFBN - 3.3V
where VFBN = 250mV.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (hFEN), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor’s current gain limits the guaranteed maximum output current to:
V
IGOFF1(MAX) = (IDRVN - BEN ) × h FEN(MIN)
R BEN
P = IGOFF1(MAX) × (-VGOFF1(MAX) )
where IGOFF1(MAX) is the maximum average DC output
of the negative linear regulator, and VGOFF1(MAX) is the
maximum negative output voltage of the linear regulator.
PCB Layout and Grounding
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
U Minimize the area of respective high-current loops by
placing each DC-DC converter’s inductor, diode, and
output capacitors near its input capacitors and its
LX_ and power grounds. For the step-down regulator, the high-current input loop goes from the positive
terminal of the input capacitor to the IC’s IN2 pin, out
of LX2, to the inductor, to the positive terminals of the
output capacitors, reconnecting the output capacitor and input capacitor ground terminals. The highcurrent output loop is from the inductor to the positive
terminals of the output capacitors, to the negative
terminals of the output capacitors, and to the Schottky
diode (D2). For the step-up regulator, the high-current
input loop goes from the positive terminal of the input
capacitor to the inductor, to the IC’s LX1 pin, out of
GND1, and to the input capacitor’s negative terminal. The high-current output loop is from the positive
terminal of the input capacitor to the inductor, to
the output diode (D1), to the positive terminal of the
output capacitors, reconnecting between the output
capacitor and input capacitor ground terminals. For
32 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
U Create an analog ground plane (AGND) consisting
of the AGND pin, all the feedback-divider ground
connections, the COMP1, COMP3, DEL, SS, DLY1,
DLY2, EN1, and EN2 capacitor ground connections,
and the device’s exposed backside pad. Connect
the GND1 and AGND islands by connecting the two
ground pins directly to the exposed backside pad.
Make no other connections between these separate
ground planes.
U Place IN pin, IN2 pin, and VL pin bypass capacitors as close as possible to the device. The ground
connection of the VL bypass capacitor should be
connected directly to the AGND pin with a wide trace.
U Minimize the length and maximize the width of the
traces between the output capacitors and the load for
best transient responses.
U Minimize the size of the LX1, LX2, and LX3 nodes
while keeping them wide and short. Keep the LX1,
LX2, and LX3 nodes away from feedback nodes
(FB1, FB2, FB3, FBP, and FBN) and analog ground.
Use DC traces as a shield if necessary.
Refer to the MAX17122 evaluation kit data sheet for an
example of proper board layout.
IN3
RHVS
FB1
COMP1
VL
N.C.
LX1
LX1
TOP VIEW
GND1
Pin Configuration
GND1
U Create a power ground island for the step-down
regulator, consisting of the input and output capacitor grounds and the diode ground. Connect all these
together with short, wide traces or a small ground
plane. Similarly, create a power ground island (GND1)
for the step-up regulator, consisting of the input and
output capacitor grounds and the GND1 pin. Create
a power ground island for the boost-buck regulator,
consisting of the input and output capacitor grounds
and inductor ground. Connect the step-down regulator ground plane, GND1 ground plane, boost-buck
ground plane, charge-pump power ground, and
negative linear-regulator power ground together with
wide traces. Maximizing the width of the power
ground traces improves efficiency and reduces output voltage ripple and noise spikes.
U Place all feedback voltage-divider resistors as close
as possible to their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX1, LX2, and LX3.
40 39 38 37 36 35 34 33 32 31
30 LX3
GATE 1
IN 2
29 N.C.
+
IN2 3
28 COMP3
27 FB3
IN2 4
26 NTC
AGND 5
MAX17122
LX2 6
25 SET
24 AGND
LX2 7
BST2 8
23 DEL
OUTB 9
22 RESET
21 DRVP
FB2 10
THIN QFN
6mm x 6mm
FBP
DLY2
DRVN
SS
FBN
15 16 17 18 19 20
HVS
EN2
EN1
DLY1
GPGD
11 12 13 14
______________________________________________________________________________________ 33
MAX17122
the boost-buck regulator, the high-current input loop
goes from the positive terminal of the input capacitor
to the IC’s LX3 pin, inductor, out of GND1, and to the
input capacitor’s negative terminal. The high-current
output loop is from the ground terminal to inductor,
to the IC’s LX3 pin, to the output diode (D3), the
negative terminal of the output capacitor, reconnecting between the output capacitor/input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in the
high-current paths. If vias are unavoidable, use many
vias in parallel to reduce resistance and inductance.
MAX17122
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
40 TQFN-EP
T4066+3
21-0141
90-0054
34 ��
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
1
9/09
Initial release
2
11/09
Corrected EC table parameter; only typical is relevant at high temperature
PAGES
CHANGED
—
1, 2, 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009
Maxim Integrated Products 35
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX17122
Revision History

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