ETC PP708A

Timing Controller
for Analog TFT-LCD Module
Data Sheet
V0.01
Data Sheet
V1.4
POINTCHIPS Co., Ltd
4FL., Dabong Tower Bldg. 890-12, Daechi-Dong,
Kangnam-Gu, Seoul 135-839, Korea
Tel : 82-2-508-0591
Fax : 82-2-508-1422
URL : www.pointchips.com
Contact : [email protected]
PP708A
Revision No.
Revision Date
V0.00
Oct. 20.2004
Description
First Draft
1. Change Application Circuit.
V0.01
Oct.31.2004
- Add Schmitt Inverter for Video Decoder Sync. Input for clamp
2. Update panel list can be used.
3. Revise AC Characteristics
2
Contents:
Page
1. Description ---------------------------------------------------------------------------------------- 4
2. Block Diagram -------------------------------------------------------------------------------------- 6
3. DC Characteristics ------------------------------------------------------------------------------- 13
4. AC Characteristics ------------------------------------------------------------------------------- 14
5. Pin Assignment ------------------------------------------------------------------------------------- 18
6. Pin Description (48-Pin) -------------------------------------------------------------------------- 19
7. Display Mode ---------------------------------------------------------------------------------------- 24
8. Screen Display Range ----------------------------------------------------------------------------- 26
9. Vertical Display Method --------------------------------------------------------------------------- 27
10. 48-TQFP Package Dimension ----------------------------------------------------------------- 29
11. Application Diagram ------------------------------------------------------------------------------ 30
12. PLL Description & Circuit ------------------------------------------------------------------------ 31
13. Application Circuit -------------------------------------------------------------------------------- 33
3
1. Description
This timing controller is a CMOS LSI controlling for various analog TFT-LCD panel (Stripe Type: 480x234, 400x234,
320x234, Delta Type: 160x234) at any company panel. It accepts video synchronization signal (composite sync) and
provides all the necessary timing signals to control the LCD source and gate drivers. Built-in PLL sub-function with
external VCO and low pass filter circuits produces system clock which synchronizes input composite synchronization
signal. Especially, the internal noise filter with more than 70 taps is added to separate HSYNC(Horizontal Sync) and
VSYNC(Vertical Sync) signal from CSYNC(Composite Sync) carried noise like TV signal.
It supports any company analog panel ( including sharp panel ) and small size delta type panel.
The panel lists supported is as followings:
Resolution
Company
480x234
(Inch Model Name)
Samsung
7.0"/LTE700WQ
LG
7.0"/LB070W02
6.5"/LB065WQ2
AU
(InnoLux)
7.0"/A070FW02
( 7.0"/AT070TN01 )
6.5”/A065GW01
Toshiba
(ProView)
7.0"/LTA070B410A
( 7.0"/PV07LCM-T )
Sharp
8.0"/LQ080T5GG01S
7.0"/LQ070T3GG003
400x234
(Inch/Model Name)
320x234
(Inch/Model Name)
7.0"/PW070XS1
5.6”/A056DN01
The others
4.0”/A040CN01
3.5"/A035CN02
the same kinds
the same kinds
5.0"/LQ050T3GG01S
5.8"/LQ058T3GG01S
6.5”/LQ065T5GG22
6.5"/PW065XS1
7.0””/PW070XU3
Sanyo
Note
5.0"/LTS500Q1-CF3
8.0"/PW084XS2
PVI
160x234
(Inch/Model Name)
8.0"/TM080WA
7.0"/TM070WA
HanStar
7.0”/HSD070I651
ADT
5.0”/ADT050-C30P
Topsun
TS70WA0105
HanStar
HSD050I551
4
6.4"/PA060XS1
3.5"/PA035XS1
5.0"/PA050XS1
2.5"/PA025XS1
3.5", 2,5" is delta
type panel
Feature
(1) Master clock frequency
28.70 MHz
480x234x3 Pixels
23.97 MHz
400x234x3 Pixels
19.27 MHz
320x234x3 Pixels
19.27 MHz
160x234x3 Pixels
(2) Built-in Phase Comparator for PLL sub-function
- It creates the divide signal compared with CSYNC input.
- It need to use the external OP-Amp for LPF(Loop Filter) and VCO.
(Note) Refer to application circuit (Page 30).
(3) Built-in the Vertical Sync separator to get VSYNC from CSYNC input.
- It need not use the external circuit for Vertical Sync separation (slicer)
- Input is only CSYNC (Composite Sync Signal)
(4) Provides the control timing signal of LCD source and gate drivers.
All the necessary output signals to control the LCD source and gate driver is as follows:
- Source : HCLK1, HCLK2, HCLK3, STH1, STH2, OEH
- Gate
: CPV, STV1, STV2, OEV1, OEV2, OEV3, MOD1, MOD2, FRP
(5) Provides the timing scan signals for Left / Right and Up / Down shift control.
(6) Provides Horizontal and vertical positions adjustment function.
- Horizontal: 1 sign bit and external RC delay
-> It is possible to control the start position on horizontal with detailed and largely
- Vertical
: 3-bit (-4 ~ 3 lines: signed)
(7) Provides the several display mode ( Full, Normal, Zoom etc. ) .
- Full, Normal, Zoom1, Zoom2, Zoom3, Wide, Zoom Wide1, Zoom Wide2
(8) Provides Serial Communication
- CS, CLK, DATA
(9) NTSC/PAL system timing
- It has two types of method to select video (NTSC/PAL)
: Manual NTSC/PAL Selection or Auto NTSC/PAL Detection
- It outputs video detection signal whether video signal exits or not.
(10) It supports RGB pattern signal.
- It can use PLL clock or external clock (dot clock)
(11) Package: 48-TQFP
(12) Single power supply: 5.0Volts.
- Including Regulator (LDO: 5V to 3.3V)
- The output voltage of the signal related with panel will be 3.3V or 5.0V according to panel Logic voltage.
5
2. Block Diagram
PP708A consists of 9 blocks.
1) Clock Divider
- This block divides the VCO clock into 2, 2.5, 3, 3.5, 4 times for horizontal scaling.
2) Sync Separator
- HSYNC_E, VSYNC to be used in internal block is separated from CSYNC input.
- It accepts separated 2 signal HSYNC, VSYNC, CSYNC (all negative)
3) HSYNC Generator
- Horizontal Sync to be referenced in TCON and PLL comparator input.
4) VSYNC Generator
- Vertical Sync to be referenced in TCON.
6
5) Phase Detector
- Compare HSYNC_E separated from CSYNC with internal HSYNC for PLL Locking
6) Horizontal Scaler
- Horizontal scaling according to MODE ( Normal, Wide )
- Normal Mode: 2 -> 4 -> 2 divide
- Wide Mode : 2.5 -> 3 -> 3.5 -> 3 -> 2.5 divide
7) Horizontal Signal Generator
- It generates all the source signal of TFT-LCD panel
8) Vertical Signal Generator
- It generates all the vertical signal of TFT-LCD panel
9) LDO ( Internal Regulator )
- This pin is basically the output of internal regulator (5.0V → 3.3V), and the voltage of the output pin related LCD-panel
interface (Source or Gate signal).
- When logic voltage of TFT-LCD panel is 3.3V, connect 0.1uF to this pin
(Note) This pin can drive 20mA at 3.3V, so you can be used as used as the logic VDD of the LCD Panel if panel
driving current is less than 10mA.
- When logic voltage of TFT-LCD panel is 5.0V, force 5.0 voltage to this pin.
(Note) This pin is the power of the pin related LCD interface, so if you supply this pin with 5.0V, then the voltage of the
pin related LCD interface (source or gate signal) will be 5.0V swing
10) ROM 1024-Byte
- PP708A has ROM-tabled Hardware Architecture
Internal Counter
in each Block
Compare
TCON Timing Signal
Internal Register
ROM Table
(1024 -B yteRO
R OM
(256-Byte
M))
7
- When PP708A is initialized, ROM Data is loaded into all register in each block.
- All signal is generated from comparing counter with register.
- The merit to use ROM Table is easy to revise the TCON output signals by changing the ROM value.
- ROM is the data for various panel support, and as follows:
„
480x234, 400x234, 320x234, 160x234
„
Normal Panel, Sharp Panel
„
NTSC / PAL
Normal
480 x 234
400 x 234
Sharp
320 x 234
160 x 234
480 x 234
400 x 234
320 x 234
160 x 234
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
000
040
080
0C0
100
140
180
1C0
200
240
280
2C0
300
340
380
3C0
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
03F
07F
0BF
0FF
13F
17F
1BF
1FF
23F
27F
2BF
2FF
33F
37F
3BF
3FF
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
64-B
(note) The 320x240 resolution and 160x234 resolution of sharp panel are not tested. But that ROM data is
calculated by ROM data in basic of other panel
8
11) Serial Communication Timing Chart
CS
= MODE2, when TW_EN = "L"
CLK = MODE1, when TW_EN = "L"
DATA = MODE0, when TW_EN = "L"
9
3. Signal Timing
th0
ts0
CS
twL
CLK
twH
th1
ts1
sym
Unit
bol Min. Typ. Max.
Parameter
CS setup time based on CLK rise
ts0 465
ns
DATA setup time based on CLK rise
ts1 220
ns
CS hold time based on CLK rise
th0 165
ns
DATA hold time based on CLK rise
th1 220
ns
CLK LOW LEVEL Pulse Width
twl
330
ns
CLK High LEVEL Pulse Width
twh 330
ns
10
< HOST operation>
CS
CLK
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 D12 D13 D14
D15
D3
D4
D5
D6
D7
D8
D9
D10
D11 D12 D13 D14
D15
< TCON operation >
CS
CLK
DATA
D0
MSB
D1
D2
D15
D8
DATA
D7
D0
COMMAND
LSB
- COMMAND
D0 : if “H”, Write operation.
if “L”, Read operation.
D1~D6 : Address(6 bits)
D7: reserved
< Define Data Transfer Clock >
Read
Operation
External Clock
Internal Clock
Write
Operation
11
3. DC Characteristics
3.1) Absolute maximum ratings
Parameter
Symbol
Rating
Units
Power supply
VDD
-0.3 to 6.0
V
Input voltage
VIN
-0.3 to VDD+0.3
V
Output voltage
VOUT
-0.3 to VDD+0.3
V
Storage temperature
TSTG
-40 to +125
℃
3.2) Recommended operation conditions
Parameter
Symbol
Min
Typ
Max
Units
Power supply
VDD
4.5
5.0
5.5
V
Input voltage
VIN
0
-
VDD
V
Operating temperature
TOPR
-30
-
85
℃
Operating Current (@ Freq=28.7MHz )
ICC
-
-
20
mA
Static Current
ISCC
-
-
5
uA
(Note) When the static current is measured, LDO function is disabled.
3.3) Electrical Characteristics
0℃
100℃
Minimum
Maximum
VDD
Low Level Input Voltage
-0.5V
0.3 x VDD
4.5V to 5.0V
VIH
High Level Input Voltage
0.7 x VDD
VDD + 0.5V
4.5V to 5.0V
VOL
Low Level Output Voltage
VSS + 0.4V
4.5V
IOL = 0.8mA
VOH
Low Level Output Voltage
4.5V
IOH = 0.8mA
Symbol
Parameter
VIL
VDD - 0.4V
Conditions
(Note) The driver capability of STH1, STH2, HCLK1, HCLK2, HCLK3, PDO is 4mA, the others is 2mA.
3.4) Pull-up Characteristics (RESETB)
Min Current(at Pad=0V)
Max Current(at Pad=0V)
-100uA
-230uA
5.0V Pull-up
3.5) LDO Characteristics (V33)
Symbol
V33V
Parameter
Low Level Output Voltage
0℃
Minimum
3.15V
25℃
Typical
3.3V
100℃
Maximum
3.45V
V33I
LDO Current
100uA
140uA
180uA
12
Conditions
VCC
5.0V
Note
Driving Capability
= MAX 20mA
It can support Panel
logic l VDD
4. AC Characteristics
4.1) Input signal characteristics
Parameter
Symbol
VCOI period
(59.94 x 262.5 x H-Count)
tVCO
Min.
Typ.
Max.
Units
Remark
28.60
28.70
28.8
MHz
480x234
23.90
23.97
24.10
MHz
400x234
19.15
19.27
19.25
MHz
320x234
19.15
19.27
19.25
MHz
160x234 (Delta)
63.37
63.5
63.61
us
63.89
64.0
64.10
CSYNC period
tH
CSYNC pulse width
tCSYNC
4
4.7
5.4
us
CSYNC rising time
TCr
-
-
700
ns
CSYNC falling time
tCf
-
-
300
ns
262
262.5
263
line
NTSC
312
312.5
313
line
PAL
Horizontal lines per field
.
4.2) Output signal characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Remark
Rising time
tr
-
-
10
ns
note
falling time
tf
-
-
10
ns
note
Clock high and low level
pulse width
tCPH
2
3
4
tVCO
HCLK1~HCLK3
Clock pulse duty
tCWH
40
50
60
%
HCLK1~HCLK3
tCPH/3 – 0.1* tCPH
tCPH/3
tCPH/3 + 0.1* tCPH
tCPH
From HCLK1 to HCLK2
From HCLK2 to HCLK3
From HCLK3 to HCLK1
tCPH/2
tCPH/2 + 0.1* tCPH
ns
tC12
3 clock phase difference
STH setup time / Hold time
tC23
tC31
tSUH / tHDH tCPH/2 - 0.1* tCPH
STH pulse width
tSTH
0.75
1
1.5
tCPH
HSYNC pulse width
tHS
4.6
4.7
4.8
us
OEH pulse width
tOEH
1.5
1.6
1.7
us
48 * tVCO
Sample & hold disable time
tDIS1
6.5
6.6
6.7
us
192 * tVCO
OEV pulse width
tOEV
5.0
5.1
5.2
us
147 * tVCO
CPV pulse width
tCPV
8.4
8.5
8.6
us
243 * tVCO
Clean enable time
tDIS2
3.2
3.3
3.4
us
96 * tVCO
HSYNC-CPV time
t1
1.1
1.2
1.3
us
36 * tVCO
HSYNC-OEV time
t2
2.0
2.1
2.2
us
59 * tVCO
HSYNC-VCOM time
t3
0.5
0.6
0.4
us
18 * tVCO
STV setup time
tSUV
-
tH/2
tH/2
tH
STV pulse width
tSTV
0.8
1
1.2
tH
Note :For all of the logic signals.
13
4.3)VCO, STH and HCLK timing waveform
4.4) Vertical shift clock timing waveform
(CSYNC)
STV
TSTV
TSUV
CPV
14
4.5) CVS and horizontal control timing waveform
tH
~
~
t CVS
CSYNC
~
~
tH
HSYNC
S
t OEH
~
~
OEH
t ST
H
t DIS
1
~
~
STH
t DIS
2
t1
t CPV
~
~
CPV
t2
t OEV
~
~
OEV
FRP
~
~
PDO
t3
~
~
4.6) CSYNC and vertical control timing waveform
CSYNC
VSYNC
tVS
STV
~
~
~
~
VCOM
(Odd field)
VCOM
(Even field)
15
4.7) Timing waveform between video signal
16
RSEL0
HLO
HLI
SMOD
RSEL1
VPOS0
VPOS1
VPOS2
VDD
VCOI
VCOO
ZMOD
48
47
46
45
44
43
42
41
40
39
38
37
5. Pin Assignment
1
36
PDO
VSYNC_I
2
35
OEV3
HSYNC_O
3
34
OEV2
VSYNC_O
4
33
GND
SYNC_SEL
5
32
CPV
TW_EN
6
31
OEV
GND
7
30
HCLK1
FRP
8
29
STVU
9
28
HCLK2
10
27
STVD
NTSC_PAL
11
26
HCLK3
MODE0
12
25
OEH
TFT-LCD Panel Interface
17
21
22
23
24
VDD
V33
STHL
STHR
17
PEVEN
(HSYNC)
Video Decoder Interface
PSEL1 20
16
UD
PSEL0 19
15
LR
RESETB 18
14
MODE2
SBLK
MODE1 13
VIDEO_DET
TEST1
CSYNC_I
6. Pin Description (48-Pin)
Pin No
Pin Name
I/O
Description
1. Composite Sync Input
- When SYNC_SEL="L", accept composite sync
1
CSYNC_I
[DOT_CLK]
I
2. When PC RGB is used, Dot-Clock signal Input.
(1) When SYNC_SEL="H" and NTSC_PA = “H”, dot-clock is used
(2) When SYNC_SEL="H" and NTSC_PA = “L”, internal clock is used
1. When SYNC_SEL="L", by using this pin you can select whether the NTSC/PAL
input is manual or auto selection.
2
VSYNC_I
I
2. When SYNC_SEL="H"
If PEVEN(HSYNC) is HSYNC(Negative), Vertical Sync Input (Negative Polarity)
If PEVEN(HSYNC) is CSYNC(Negative), VSYNC_I must be “High”
3
HSYNC_O
O
4
VSYNC_O
O
Horizontal Sync Output for Video Decoder Sync (Negative Polarity)
Vertical Sync Output(Positive Polarity)
If panel needs reset signal, use this signal.
SYNC Selection - "L" : CSYNC only,
5
SYNC_SEL
SYNC_SEL
VSYNC_I
L
L
I
H
(PC RGB)
"H":HSYNC(PEVEN), VSYNC
Function
SYNC Input
NTSC/PAL Selection
L
CSYNC
Auto
H
CSYNC
Manual
Dot Clock
input : CSYNC_I
HSYNC input ; PEVEN
VSYNC input : VSYNC_I
(Note) Pin-9 is video detection output ,
TW_EN
whether signal exits or not.
3-Wire Enable
Data In/Out : MODE0 (Pin12)
6
TW_EN
I
L
3-wire clock : MODE1 (Pin13)
3-wire data Enable : MODE2 (Pin14)
H
3-wire Disable
7
GND
G
Ground
8
FRP
O
Toggling signal for RGB / VCOM output at video decoder
9
VIDEO_DET
O
Video detection ("L" : No video, "H" : Video exits).
It can detect whether video signal is existent or not.
18
10
SBLK
O
Side-black control pin only in normal mode (4:3 picture).
If this pin is set to high, video(R,G,B) outputs black level.
19
Pin No
Pin Name
I/O
Description
- NTSC/PAL Auto Detection or NTSC/PAL manual Selection
11
NTSC_PAL
I/O
SYNC_SEL
VSYNC_I
L
Function
NTSC/PAL Selection
Pin Direction
L
Auto
Output
L
H
Manual
Input
H
x
Dot-clock
Input
- NTSC or PAL designation
SYNC_SEL NTSC_PAL
L
H
Designation
L
PAL
H
NTSC
L
PLL Clock (internal clock)
H
Dot clock(External clock)
- Regardless of this pin, VIDEO_DET signal will be output.
12
MODE0
I/O
13
MODE1
I
14
MODE2
I
15
LR
I/O
16
UD
I/O
Screen Display Mode Selection when TW_EN=H.
( Full, Normal, Zoom, Wide ), see 7-2
- If TW_EN=L, then it will enter 3-wire mode.
- Left/Right scan control pin ( L : L → R,
H: R → L )
- when 3-wire mode, this pin is output
- Up/Down scan control pin ( L : U → D,
H: D → U )
- when 3-wire mode, this pin is output
1. When SYNC_SEL = L, how add even signal selection to the odd signal
“L” : ODD = EVEN
17
PEVEN
[HSYNC_I]
I
“H” : ODD = EVEN + 1
2. When PC RGB(SYNC_SEL =H) is used, HSYNC or CSYNC input (Negative Polarity)
If PEVEN(HSYNC) is HSYNC(Negative), Vertical Sync Input (Negative Polarity)
If PEVEN(HSYNC) is CSYNC(Negative), VSYNC_I must be “High”
18
RESETB
I
Reset Signal (Active Low)
Panel Section signal
19
20
PSEL0
PSEL1
I
I
PSEL1
PSEL0
Description
L
L
Sharp Panel
L
H
Normal Signal Samsung, Toshiba
H
L
Inverting OEH Signal for AU InnnoLux, PVI
H
H
Inverting OEV Signal for LG, Sanyo
20
Pin No
Pin Name
I/O
Description
21
VDD
P
Power(5.0V)
This pin is basically the output of internal regulator (5.0V → 3.3V), and the voltage of
the pin related LCD interface (Source or Gate signal).
1. When logic voltage of TFT-LCD panel is 3.3V,
-> Connect 0.1uF to this pin
V33
22
[ V33O ]
[ V50I ]
(Note) This pin can drive 20mA at 3.3V, so you can be used as used as the logic
P
(I/O)
VDD of the LCD Panel if panel driving current is less than 10mA.
2. When logic voltage of TFT-LCD panel is 5.0V,
-> Force 5.0 voltage to this pin.
(Note) This pin is the power of the pin related LCD interface, so if you supply this pin
with 5.0V, then the voltage of the pin related LCD interface (source or gate
signal) will be 5.0V swing
23
STHL
O
Start pulse for Source Driver
STH Output
LR Pin
24
STHR
O
25
OEH [ CTR ]
O
26
HCLK3
O
STHL
STHR
L
STH Output
Hi-Z Output
H
Hi-Z Output
STH Output
1.
Source Driver output Enable control pin
2.
when Sharp panel is used, CTR signal input
Source clock for Shift of Source driver 3
Start pulse for Gate Driver
27
STVD
STV Output
UD Pin
O
STVU
STVD
L
STV Output
Hi-Z Output
H
Hi-Z Output
STV Output
28
HCLK2
O
Source clock for Shift of Source driver 2
29
STVU
O
Start pulse for Gate Driver
30
HCLK1
O
Source clock for Shift of Source driver 1
31
OEV1
O
32
CPV
O
Gate clock for Shift of Gate driver
33
GND
G
Ground
1. Gate Driver output Enable control pin
2. In Sharp panel, Q1H output signal
21
Pin No
34
Pin Name
OEV2
[MODE1]
I/O
Description
O
Gate Driver output Enable control pin for Zoom in NTSC signal
OEV3
35
[MODE2]
O
[Q1H]
1. Gate Driver output Enable control pin for Zoom in NTSC signal
2. In 3’5” panel, Q1H output signal
Phase Comparator output (when no video signal input, high-impedance)
36
PDO
O
It outputs signal compared CSYNC with internal HSYNC.
(Refer to 12-2)
Zoom Mode Control.
ZMOD
37
ZMOD
L
I
H
Zoom Control
OEV1 Signal is only used
OEV1, OEV2, OEV3
is used
MOD1, MODE2 is used when Sharp Panel
Input/Output for PLL VCO oscillation.
38
VCOO
O
39
VCOI
I
(Refer to 12-2)
40
VDD
P
Power (5.0V)
41
VPOS2
I
42
VPOS1
I
43
VPOS0
I
44
RSEL1
I
The frequency is determined by external passive element L and C.
Vertical Display Start Position control pin (from STV-4 to STV+3)
STV Start Position + [VPOS2[(signed),VPOS1,VPOS0]
(Ex) VPOS=100 → STV-4, VPOS=011 → STV+3
Panel Resolution Selection ( Refer Pin48)
Sampling Mode Selection
45
SMOD
I
46
HLI
I
“L” : Sequential Sampling (HCLK1, HCKL2, HCK3)
“H” Simultaneous Sampling(HCLK1 output,HCLK2,3 = L)
HLO
Rx
10K
HLI
Cx
47
HLO
100p
O
- Horizontal Display Start Position is shifted as mush as Rx/Cx delay value.
22
Pin No
Pin Name
I/O
Description
- Panel Selection together RSEL1 signal.
48
RSEL0
I
RSEL0
RSEL1
Resolution
L
H
160 x 234
L
L
320 x 234
H
H
400 x 234
H
L
480 x 234
(note) Sharp Panel Selection will be done by PSEL0, PSEL1 pin
(Note) Where I/O Column,
I = Input, O = Output, I/O = Bi-directional Pin
23
7. Display Mode
7.1) Panel Structure ( when 480x234 resolution )
7.2) Display Mode - 8 display mode
24
7.3) Frequency per pixel about 7" Panel
fH/fVCO freq.
dividing ratio
fVCO(MHz)
PAL
fCPH/fVCO freq.
dividing ratio
9.56
9.49
1/3
14.35
14.24
1/2
7.17
7.12
1/4
11.48
11.47
1/2.5
Periphery
9.56
9.49
1/3
Center
8.20
8.19
1/3.5
NTSC
PAL
Full, Zoom
Black potion
Normal
Picture portion
1/1824 (NTSC)
28.70
Both ends
Wide
fCPH(MHz)
NTSC
Mode
28.68
1/1836 ( PAL )
(Note) 28.70MHz = 1824 x 59.94 x 262.5
28.68MHz = 1836 x 50.00 x 312.5
7.4) Frequency per pixel about 5" Panel
fH/fVCO freq.
dividing ratio
fVCO(MHz)
NTSC
PAL
6.42
6.43
1/3
9.63
9.65
1/2
4.85
4.83
1/4
7.70
7.72
1/2.5
Periphery
6.42
6.43
1/3
Center
5.50
5.52
1/3.5
NTSC
PAL
Full, Zoom
Black potion
Normal
Picture portion
1/1224 (NTSC)
19.26
Both ends
Wide
fCPH(MHz)
fCPH/fVCO freq.
dividing ratio
Mode
1/1236 ( PAL )
(Note) 19.26MHz = 1224 x 59.94 x 262.5
19.31MHz = 1236 x 50.00 x 312.5
7.5) Frequency per pixel about other panel
- 400 x 234 Panel
23.97MHz = 1524 x 59.94 x 262.5
24.00MHz = 1536 x 50.00 x 312.5
- 160 x 234 Panel
It is the same as 320 Pixel Mode
25
19.31
8. Screen Display Range
8.1) Horizontal Display Range (Pixels)
NTSC
Mode
PAL
5-inch
7-inch
5-inch
7-inch
Full
320 pixels
480 pixels
320 pixels
480 pixels
Normal
240 pixels
376 pixels
240 pixels
376 pixels
Wide
320 pixels
480 pixels
320 pixels
480 pixels
320 pixels
480 pixels
320 pixels
480 pixels
Zoom1
Zoom2
Zoom3
(Note) The start time = 1H/2 - ((Pixels/2) * fCPH)
12.96us(NTSC), 13.86us(PAL) at Full, Zoom, Wide Mode
8.83us(NTSC), 9.85us(PAL) at Normal Mode
8.2) Vertical Display Range (H : Lines) - Odd line
Mode
NTSC
PAL
5-inch
7-inch
5-inch
7-inch
Full
240 lines
21H ~ 260H
234 lines
21H ~ 254H
279 lines
23H ~ 301H
273 lines
23H ~ 295H
Normal
240 lines
21H ~ 260H
234 lines
21H ~ 254H
279 lines
23H ~ 301H
273 lines
23H ~ 295H
Wide
240 lines
21H ~ 260H
234 lines
21H ~ 254H
279 lines
23H ~ 301H
273 lines
23H ~ 295H
Zoom1
188 lines
41H ~ 228H
182 lines
41H ~ 222H
240 lines
45H ~ 284H
234 lines
45H ~ 278H
Zoom2
214 lines
45H ~258H
208 lines
45H ~252H
258H
50H ~ 307H
252H
50H ~ 301H
Zoom3
214 lines
33H ~ 246H
208 lines
33H ~ 240H
258H
36H ~ 293H
252H
36H ~ 287H
(Note) The start position of even line is odd line + 263(NTSC), 313(PAL)
(Note) In Zoom mode, it is different to handle line insertion(NTSC), line drop(PAL).
1. NTSC Zoom (Page 18)
- Add the CPV signal between CPV interval time.
2. PAL Zoom (Page 19)
- Eliminate the CPV, OEH, OEV on the line to be removed.
- At that time, FRP Signal is not changed
26
9. Vertical Display Method
9.1) Vertical Display Wave form at NTSC
Video
STV
CPV
OEV
OEH
FRP
Video
STV
CPV
OEV
OEH
FRP
20
21
22
23
24
25
26
27
28
41
42
43
44
45
46
47
48
49
29
Wave form for Normal Dispaly Method in NTSC Vertical
19
30
Wave form for Zoom Dispaly Method in NTSC Vertical
39
30
40
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
60
27
9.2) Vertical Display Wave form at PAL
Video
STV
CPV
OEV
OEH
FRP
Video
STV
CPV
OEV
OEH
FRP
22
23
24
25
26
27
28
29
30
45
46
47
48
49
40
51
52
53
31
Wave form for Normal Dispaly Method in PAL Vertical
21
44
Wave form for Zoom Dispaly Method in PAL Vertical
43
32
54
33
55
34
56
35
57
36
58
37
59
38
60
39
61
40
62
41
63
42
64
28
10. 48-TQFP Package Dimension
29
VDD
VEE
GND
VBS
VSS
VGON
VCOM
Power
3-WIRE
- The external input related with TCON function is only CSYNC signal.
(except RESET, option pin).
11.2) Video Decoder
- Analog video decoder must be used, and the tested video decoders are as follows:
Sharp - RB5P006AM, IR3Y29BM
JRC - NJM2529
- If you use another company's video decoder, please contact us.
11.3) Power
The power of LCD module is various, so you have to select suitable DC-DC converter.
Refer to application circuit (Page 25)
30
DC / AC
Converter
LCD Module
Interface
PLL / VCO
R
G
B
CSYNC
VSYNC
HSYNC
FRP
11.1) PP708A input
DC / DC
Converter
11. Application Diagram
12. PLL Description & Circuit
12.1) PLL Construction
CSYNC
HSYNC HSYNC_R
Separator
Phase
Comparator
PDO
Loop
Filter
LPO
VCO
HSYNC_C
VCOI
HSYNC Generator
(Freq. Divider)
Internal Logic
of PP708
12.2) PLL Circuit
-The following circuit is the PLL using the TCON of PointChips
PP708
1M
R19
L2
VCO2
1K
C8
C5
1000p
C6
100p
150p
Q6
KTC3876
1.5uH(2520)
R18
1M
VCOO
L1
VCOI
R17
RGND
R5V
R12
VCOI
10K
50K
RGND
0.1u
(option)
0
VR1
C4
100
RGND1
0
D8
R15
RGND
R5V1
R5V
VCO1
5.1V
D5.0V
GND
RGND
-10V
R11
0.1u
VCOO
1M
47p
10K
330
C1
R8
4
NJM2107F
R14
3 -
2.7K
1 +
LPI
3.3K
LPR
47K
R16
5
68K
R5
R21
C9
DZ1
4.7K
R3
R4
LPO
R10
47K
U9
2
R1
PDO
3.3uH : 960, 480
2.2uH : 1200
1.5uH : 1440
VCOI
1M
1.5uH(2520)
1M
R5V
R20
2200
R13
R7
C5
R5V
0.1u
MA335
BB132
C3
10K
680p
R2
PDO
C2
82K
R9
R6
10K
R5V
4.7K
Loop Filter
C7
100p
PP708
31
12.3) PLL Adjustment
- How to adjust PLL circuit ?
The CSYNC signal, which is Composite Sync generated from analog video decoder, must be stable.
You may use any VCO circuit out of two VCO circuits on above PLL circuit.
1) The frequency of VCO must be set to 28.7MHz(7"panel) without PDO signal
→ Pull out video signal from video jack in order to separate between PDO and PLL.
(When video signal is not existent, the PDO of PP708A is high impedance output)
→ L1=1.5uH, C7=100pF (at VCO2 circuit)
L2=1.5uH, C9= 47pF (at VCO1 circuit)
→ Probe VCOO node, then adjust VR1 so that the frequency is 28.7MHz.
(note) 1. Depend on PCB artwork, you need to change the capacitor value(C7or C9) to be desired frequency.
2. In 400 panel, the VCOO frequency is 24MHz ( L1,L2 = 2.2uH )
3. In 320, 260 panel, the VCOO frequency is 19.3MHz ( L1,L2 = 3.3uH )
Close
Power Separation
PP708
PLL Circuit
Put all PLL circuit together
→ Above is the PCB pattern of PLL Circuit. Please draw closely.
2) Input video signal related with PLL block
→ PDO signal is the input signal of PLL circuit.
(When video signal is existent, the PDO of PP707 is output)
→ Adjust VR1 to be PLL locking between CSYNC and internal HSYNC.
→ Probe PDO node, examine the PDO wave form to be the following wave.
32
13. Application Circuit
13.1) PP708A Circuit
VC+5V
4
8
C
22uH
C83
3
8
R
0
0
1
6
8
R
F
u
7
4
V
6
1
7
K
2
L
G
V
F
u
7
4
V
6
1
6
9
R
K
0
1
L
G
V
BA4560
5
8
C
K
6
.
5
SHARP == 5K
F
u
1
.
0
8
1 K
R 0
V 1
VCOM
0
9
3
9
8
C
8
0
1
R
M
1
VCOM DC
N
E
P
O
N
E
P
O
E
C
A
F
R
E
T
N
I
L
E
N
A
P
F
p
0
0
1
0
3
3
VC_G
PANEL Interface
K
7
.
4
P_G
P_G
P1
VCOM
P2
1
1
1
R
n
e
p
o
0
3
1
1
R
D
N
G
4
0
1
C
3
0
1
C
2
0
1
C
1
0
1
C
n
e
p
o
n
e
p
o
n
e
p
o
n
e
p
o
P26
P27
P28
P29
SRESET
P_LR
P_UD
P_FRP
N
E
P
O
MODE2
N
E
P
O
5V == OPEN
3.3V == 2K
PANEL Interface
8
6
1
R
7
6
1
R
6
6
1
R
3WIRE
UD
LR
T_G
D10
JP18
SW1
OEV2
TA_SW
D
N
G
F
u
0
1
V
6
1
F
u
1
.
0
T_G
N
E
P
O
7
0
1
C
n
e
p
o
K
1
0
1
1
C
K
1
4
3
9
6
1
R
F
p
0
0
1
1
2
INVERTR_SYNC
Timing Controller(PP708A)
1
2
P02
T_G
T_G
5
5
1
R
N
E
P
O
K
7
.
4
8
0
1
C
F
u
1
.
0
F
u
1
.
0
F
u
1
.
0
VPOS0
RESETB
T_G
P_SMOD
2
6
1
R
0
6
1
R
K
1
n
e
p
o
n
e
p
o
0
2 K
R 0
V 1
4
1
1
C
3
1
1
C
2
1
1
C
V
5
+
VPOS2
N
E
P
O
K
1
T_G
KDS160
T_G
HLO
T_G
P30
5
6
1
R
HLI
4
6
1
R
MODE1
0
8
1
1
R
n
e
p
o
D
N
G
000
670
223
111
RRR
P_STVD
P_STVU
P_OEV1
P_OEV2
P_OEV3
P_CPV
5V == OPEN
3.3V == 2K
SMOD
P
3
T+5V
1
6
1
R
1
2
3
T+5V
3
6
1
R
MODE0
6
1
1
R
0
D
N
G
P20
P21
P22
P23
P24
P25
T+5V
5
1
P
J
T+5V
4
5
1
R
T_G
N
E
P
O
T_G
LR
3
5
1
R
2
5
1
R
F
u
1
.
0
T_G
F
u
1
.
0
T_G
6
1
1
C
T_G
P
3
T_G
VSYNC
LR
UD
FRP
5
1
1
C
9
1
P
J
T_G
C109
16V 10uF
P_STHL
P_STHR
P_OEH
P_HCLK1
P_HCLK2
P_HCLK3
T_G
KKKK
1111
T_G
T+5V
L = COMPSITE
8901
4455
1111
RRRR
P
3
K
1
K
1
K
1
K
1
T_G
UD
1
2
3
22uH
B5
SYNC_SEL
9
5
1
R
8
5
1
R
7
5
1
R
6
5
1
R
ZMO0
PEVEN
T+5V
L17
B_OUT
G_OUT
R_OUT
0
2
P
J
n
e
p
o
n
e
p
o
n
e
p
o
n
e
p
o
VPOS1
T_G
T_G
P14
P15
P16
P17
P18
P19
7
4
1
R
6
4
1
R
5
4
1
R
4
4
1
R
1
2
3
SMOD
T+5V
NPC
P
3
P
3
T_G
0 Ohm
1
2
3
P
3
1
2
3
7
1
1
R
V
5
+
T+5V
T+5V
MODE2
P11
P12
P13
T+5V
4
1
P
J
P
3
T_G
n
e
p
o
T+5V
7
1
P
J
6
1
P
J
1
2
3
T+5V
H = PC R/G/B
T+5V
RSEL1
STVD
STVU
OEV1
OEV2
OEV3
CPV
L == OEV 1CH
H == OEV 3CH
T_G
3
1
P
J
P
3
P
3
T_G
T+5V
1
2
3
PSEL1
T+5V
VSYNC_I
T_G
T+5V
2
1
P
J
1
2
3
MODE1
1
2
3
P
3
T_G
T+5V
1
1
P
J
1
2
3
T+5V
RSEL0
P
3
P
3
P
3
T_G
T+5V
1
2
3
0
0
1
C
n
e
p
o
T+5V
PSEL0
0
1
P
J
1
2
3
MODE0
9
P
J
1
2
3
8
P
J
T+5V
7
P
J
T+5V
9
9
C
VIDEO Processing
3.3V/5V
C102 AU7" == 0.001uF
T_G
T_G
H == HCLK1
L == HCLK1,2,3
000000
000000
111111
RO
890123
334444
111111
RRRRRR
GO
P8
000000
222222
PP708A
RO
STHL
STHR
OEH
HCLK1
HCLK2
HCLK3
T+5V
F
u
1
BO
GO
AGND
0 Ohm
6
0
1
C
7
33
BO
GO
RO
124567
333333
111111
RRRRRR
1
2
P02
F
u
1
.
0
GND
GND
RESETB
A+5V
B8
3.3V/5V
3.3V/5V
JP6
F
u
1
.
0
18
RESETB
21
40
C96
5V == 100 ohm
3.3V == 20 ohm
T+5V
VDD
VDD
22uH
16V 10uF
V3.3
8
9
C
T_G
OSD_CON
BO
22
7
9
C
K
2
.
2
OSD_CON
V33
P6
0
F
p
0
7
4
Schmit Inverter
S_BLK
8
2
1
R
2
9
C
HSYNC_O
9
7
1
R
NPC
0
FRP
3
3
1
R
FRP
NPC
SBLK
2
U8
VGOFF1
L16
STHL
STHR
OEH
HCLK1
HCLK2
HCLK3
STVD
STVU
OEV1
OEV2
OEV3
CPV
LR
UD
FRP
F
u
1
.
0
K
6
.
5
TC7S14
4
23
24
25
30
28
26
27
29
31
34
35
32
15
16
8
5
9
C
8
7
1
R
HSYNC_V
SYNC_SEL
3WIRE
MODE0
MODE1
MODE2
PEVEN
PSEL0
PSEL1
ZMO0
VPOS0
VPOS1
VPOS2
RSEL0
RSEL1
SMOD
HLI
HLO
VDL
D
N
G
0
T+5V
CSYNC
5
6
12
13
14
17
19
20
37
43
42
41
48
44
45
46
47
SYNC_SEL
3WIRE
MODE0
MODE1
MODE2
PEVEN
PSEL0
PSEL1
ZMO0
VPOS0
VPOS1
VPOS2
RSEL0
RSEL1
SMOD
HLI
HLO
COM
STHL
STHR
OEH
HCLK1
HCLK2
HCLK3
STVD
STVU
OEV1
OEV2
OEV3
CPV
LR
UD
FRP
CSYNC_I
VSYNC_I
HSYNC_O
VSYNC_O
VIDEO_DET
SBLK
NTSC_PAL
P5
VGOFF
D
N
G
00
5
2
1
R
VSYNC
CSYNC
1
2
3
4
9
10
11
CSYNC_I
VSYNC_I
HSYNC_O
VSYNC_O
V_DET
S_BLK
NPC
HSYNC_O
VSYNC_O
NPC
V_DET
PDO
VCCO
VCCI
VGL1
0
00
34
22
11
RR
VSYNC_I
PEVEN
T_G
36
38
39
PDO
VCOO
VCOI
0
2
1
R
12
22
11
RR
HSYNC
VSYNC
NPC
VIEDO_DET
OSD_CON
16V 10uF
K
0
1
N
E
P
O
0
9
1
1
R
U6
CSYNC_I
JP5
P06
P4
C94
5
1
1
R
4
1
1
R
T_G
CSYNC
1
2
3
4
5
6
1N4733(5.1V)
0
ZD2
OPEN
T_G
P04
PANEL VOLT VALUE
2
1
1
R
DOT_CLK
VSYNC_A
HSYNC_I
R
E
L
L
O
R
T
N
O
C
G
N
I
M
M
I
T
9 N
1 E
R P
V O
C93
VGH
0
0
1
1
R
0
9
0
1
R
P3
T+5V
JP4
VCOM
VGH
L
G
V
Should draw PLL circuit very close to TCON
P_G
1
2
3
4
VGOFF
A
4
1
4
3
M
J
N
1
9
R
6
1
8
C
VC+5V
BA4560
VC_G
VCOO
P_G
TP23
5
A
4
1
4
3
M
J
N
3
9
R
T
I
U
C
R
I
C
_
M
O
C
V
5
0
1
R
0
7
0
1
R
K
3
.
3
0 K
0
1 0
R 1
F
u
1
.
0
P_G
B
:
4
U
K
0
1
8
7
C
A
:
4
U
K
0
1
K
0
3
VC_G
VCOI
4
0
1
R
2
2
2
2
T
B
M
M
6
0
1
R
F
p
0
0
1
H
u
5
.
1
2
8
C
3
0
1
R
P_G
2
9
R
L
G
V
6
8
C
6
Q
8
8
C
K
0
1
7
9
R
P_G
K
7
4
9
9
R
2
P_G
F
p
0
5
1
0
0
1
7
8
C
F
p
0
0
0
1
4
1
L
5
U
K
8
6
5
9
R
4
3
0
9
R
8
9
R
K
2
.
6
K
7
.
2
0
=
2
V
P_G
4
P+5V
2
0
1
R
1
0
1
R
F
u
1
.
0
9 K
8 0
R 1
7
0
1
2
M
J
N
P_G
1
2
10V 10uF
N
E
P
O
N
E
P
O
5.1V
M
1
8
8
R
K
7
.
4
K
7
4
4
9
R
5
P+5V
TP22
3
COM
P_G
ZD1
0
8
C
6
7
C
F
u
1
.
0
F
p
0
8 K
6 2
8
P+5V
P+5V
1
PDO
7 K
1 0
R 5
V
5
7
C
5
8
R
7
8
R
TP24
C79
BB132
8
K
0
1
D
N
G
VC_G
D9
P+5V
VC+5V
16V 10uF
2
8
R
F
u
1
.
0
B3
VC+5V
0 Ohm
VCOO
F
p
7
4
D
N
G
P_G
K
0
5
0
0
1
1
8
R
M
1
7
7
C
4 K
8 7
R 4
0 Ohm
VCOI
0
8
R
H
u 2
5
. 1
1 L
F
u
1
.
0
16V 10uF
VCOM AC
6
1
R
V
L13
4
7
C
F
p
0
0
2
2
C90
B4
VC+5V
7" == 1.5uH
L
G
V
1
9
C
22uH
V
5
+
T
I
U
C
R
I
C
_
L
L
P
V
5
+
5" == 3.3uH
6" == 2.2uH
L12
change
P+5V
L15
1.0
T_G
T_G
2005.10.29
T_G
TCON(PP708A)
33
3
4
K
0
1
F
u
1
0
.
0
K
0
1
F
u
1
0
.
0
K
0
1
F
u
1
0
.
0
K
0
1
F
u
1
0
.
0
K
0
1
F
u
1
0
.
0
G
_
V
AGC
CMA
PCI
COR
CNT
SBR
SBB
BRT
RGB
GM0
GM2
3
4
R
7
3
C
2
4
R
6
3
C
1
4
R
5
3
C
0
4
R
4
3
C
3
3
C
9
3
R
0
4
C
V
5
+
V
5
7
7
4
R
V
5
+
V
8
4
R
K
0
1
G
_
V
K
6
.
5
9
4
R
47
37
48
6
2
31
30
29
28
27
26
K
0
1
V
2
2
.
2
3 K
1 0
R 5
V
2 K
1 0
R 5
V
V
3
0
.
1
1 K
1 0
R 5
V
V
5
3
.
2
V
2
1
.
2
0 K
1 0
R 5
V
9 K
R 0
V 5
8
3
R
K
0
1
K
0
1
F
u
1
0
.
0
7
3
R
2
3
C
6
3
R
K
7
2
F
u
1
0
.
0
1
3
C
K
0
1
F
u
1
0
.
0
K
0
1
F
u
1
0
.
0
8
3
C
F
u
1
.
0
F
F
u
u
1
1
. 9.
0 30
C
6
4
R
5
7
G
_
V
G
_
V
G
_
V
K
1
0
5
R
2
4
C
AGCOUT
COM_ADJ
PICTURE
COLOR
CONTRAST
R_BRIGHT
B_BRIGHT
BRIGHT
RGB_AMP
GAMMA0
GAMMA2
1
3
R
K
0
1
K
0
1
K
0
1
K
0
1
V
7
0
.
2
8 K
R 0
V 5
V
9
0
.
2
7 K
R 0
V 5
V
1
3
.
2
0
3
C
5
3
R
9
2
C
4
3
R
8
2
C
3
3
R
K
3
3
F
u
1
0
.
0
K
0
3
3
5
4
R
5
7
F
u
1
0
.
0
K
2
.
8
4
4
C
3
4
C
n
e
p
o
n
e
p
o
000
000
111
345
555
RRR
2
U
F
p
8
1
5
4
C
7
5
R
K
3
2
Y
F
p
8
1
0
5
C
8
5
R
K
5
.
1
6
4
C
G
_
V
9
4
C
F
F
u7u
14
1
C
F
u
1
V
5
.
7
+
6
5
C
B
9
2
Y
3
R
I
G
_
V
V
5
+
V
2
5
C
1
5
C
F
u
1
0
.
0
F
u
7
4
V
6
1
F
u
1
.
0
4
5
C
F
u
1
.
0
5
5
C
9
5
R
G
_
V
N
E
P
O
N
E
P
O
G
_
V
G
_
V
0
6
R
0
G
_
V
9
L
F
p
2
8
0
6
C
7
5
C
9
5
C
F
u
1
0
.
0
F
u
1
0
.
0
3
U
H0
u1
2
2L
V
5
+
V
5
6
R
VCO
H
u
2
2
K
6
.
5
3
6
C
1
6
C
7
6
R
V
5
+
V
F
p
3
4
F
p
6
5
0
3
3
G
_
V
0
7
R
5
6
C
4
6
C
G
_
V
K
6
.
5
F
u
7
4
0
.
0
F
u
1
0
.
0
D
3
5
0
4
C
H
4
7
G
_
V
G
_
V
6
6
C
H
u
2
2
3
7
R
2
7
R
1
7
R
F
u
1
.
0
1
1
L
M
0
1
0
%
1
K
8
1
8
6
C
9
6
C
0
7
C
5
7
R
Q5
4
7
R
MMBT2907
L
G
V
G
_
V
M
1
7
6
C
K
5
.
1
5
1
R
V
F
p
0
8
6
n
e
p
o
2
6
R
8
7
R
G
_
V
1
7
C
F
p
6
3
K
0
5
F
p
0
0
8
6
0
9
3
V
5
+
V
V
5
+
V
9
7
R
G
_
V
G
_
V
G
_
V
G
_
V
F
u
1
.
0
G
_
V
G
_
V
9
3
G
_
V
6
7
R
K
0
6
5
G
_
V
7
7
R
2
7
C
F
u
1
K
1
3
7
C
n
e
p
o
G
_
V
G
_
V
4
2
TCON(PP708A)
00
12
55
RR
G
_
V
1
Y
V
1
2
.
3
K
0
5
F_ADJ
CLAMP
AGC_FILTER
IDENT_FILTER
BURST_OUT
KILLER_FILTER
ACC_FILTER
R_Y
B_Y
CHROMA
V
5
+
V
0
3
R
9
2
R
8
2
R
7
2
R
4
Q
2
2
2
2
T
B
M
M
V
7
1
.
3
6 K
R 0
V 5
5 K
R 0
V 5
V
3
.
2
4 K
R 0
V 1
2
3
R
4
4
R
4
1
R
V
BB132
CSYNC
HSYNC_V
FRP
K
0
1
1
J
34
K
0
1
K
0
1
K
0
1
K
0
1
K
9
3
K
0
8
6
G
_
V
6
5
R
10V 10uF
6
2
R
5
2
R
4
2
R
3
2
R
2
2
R
1
2
R
F
u
0
0
1
V
6
1
D
N
G
G
_
V
Y
TINT
TP15 TP16 TP17
K
0
1
1
6
2
C
F
u
1
.
0
1
6
R
TP21
C58
TP20
GND1
GND2
NPC
V
5
+
V
COMPOSITE VIDEO
16
VCC
7
8
VEE
GND
A
B
C
11
10
9
4
Z
15
Y
BO
GO
RO
C53
17
18
TP19
14
X
X0
X1
Y0
Y1
Z0
Z1
E
12
13
2
1
5
3
6
43
VCC1
16V 10uF
C
25
22
20
B_DC_DET
G_DC_DET
R_DC_DET
4.43MHz
23
VCC2
C43 AU7" == 0.01uF
B_OUT
G_OUT
R_OUT
TINT
APC_FILTER
VCO_OUT
VCO_IN
TRAP
VCOP
C_IN
VIEDO_IN
SYNC_SEP
5
3
36
24
21
19
VCON
SW
39
B_IN
G_IN
R_IN
40
41
42
3.58MHz
TP18
13
15
16
14
1
TIN
TP13
38
35
34
33
32
COM_OUT
SYNC_OUT
SYNC_IN
FRP
COM_FRP
NPC
C41
TP12
0.47uF
KDS160
SBLK
D7
OSD_CON
KDS160
VIDEO SIGNAL R,G,B INPUT
TP10
V
5
+
V
7
2
C
COR
D6
P
3
2
CNT
B2
GM2
GM0
RGB
TP9
TP8
TP7
TP6
TP5
BRT
SBB
SBR
TP11
COR
PCI
TP4
TP3
TP2
V
5
+
3
P
J
CVS/Y
3
0 Ohm
VIDEO Processing
BIN
GIN
RIN
1
2
3
TP1
L7
CMA
AGC
22uH
44
45
46
4
7
8
11
9
10
12
T
I
U
C
R
I
C
_
O
E
D
I
V
BRT
D8
NPC
13.2) Video Decoder Circuit
PANEL Interface
Video Amplifier(IR3Y29B)
2005.10.29
1.0
13.4) LCD-Panel Interface
BOARD 1
BOARD 2
TRANS +17V / -15V
+17V
-11.5V
AGND
P_OEV2
P_OEV1
P_CPV
P_STVU
P_UD
P_OEV3
3.3V/5V
3.3V/5V
+3.3V
+3.3V
n
e
p
o
VGH
VGOFF1
n
e
p0
o
A+5V
A+5V
AGND
AGND
P_OEV3
3
7
1
R
AGND
R_OUT
G_OUT
B_OUT
T_G
12
77
11
RR
-15V
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
1
C
VCOM
VGL1
P_STHR
P_HCLK3
P_HCLK2
P_HCLK1
P_OEH
SRESET
P_LR
P_SMOD
P_STHL
P_OEV2
F
u
1
.
0
J3
0
0
7
1
R
TRANS +17V / -15V
P_STVD
VGH
C_OEV2
C_OEV3
P_UD
P_STVU
P_CPV
VGL1
VGOFF1
VCOM
P_HCLK1
P_STHL
P_OEH
SRESET
+3.3V
3.3V/5V
+3.3V
3.3V/5V
A+5V
J4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-14V
-11V !
P_LR
P_OEV1
G_OUT
R_OUT
B_OUT
A+5V
AGND
AGND
G_OUT
R_OUT
B_OUT
AGND
P_STHR
G_OUT
R_OUT
B_OUT
FCC30
TRANS +13V / -16V
J2
+15V
+13V
32
31
30
29
28
27
26
25
-10.9V(-9.5V) 24
23
22
21
-16V
20
19
18
-10V
17
16
AGND
15
14
13
12
3.3V/5V
11
10
9
AGND
8
7
6
5
AGND
4
A+5V
3
A+5V
2
+5V
3.3V/5V
1
+5V
VGH
VGOFF1
P_OEV3
P_OEV2
P_UD
P_STVU
P_CPV
VDL
VGL1
VGOFF1
VCOM
P_HCLK1
P_STHR
P_OEH
P_LR
P_STHL
B_OUT
G_OUT
R_OUT
3.3V/5V
FCC32_A
LG 7""
FCC32
SANYO 7"
SHARP 6.5",7",8"
LG 6.5"
BOARD 5
BOARD 3
BOARD 4
TRANS +17V / -15V
5
7
1
R
K
9
.
3
4
7
1
R
K
8
.
6
TRANS +17V / -15V
AGND
F
u
1
.
0
7
1
1
C
3.3V/5V
VBS
J5
J6
TRANS +15V / -10V
AGND
A+5V
AGND
3.3V/5V
+3.3 - +5V
VGH
VGH
+15V
+15V
AGND
P_OEV3
P_SMOD
+5V
P_HCLK1
P_HCLK2
P_HCLK3
P_STHL
P_STHR
P_OEH
OEV3/SMOD
P_LR
VCOM
VCOM
P_OEV1
P_UD
P_CPV
P_STVU
P_STVD
+15V
VGH
-10V
VGL1
+5V
3.3V/5V
AGND
AU 3.5"
AU
3.3V/5V
A+5V
AGND
B_OUT
G_OUT
R_OUT
AGND
P_STHL
VCOM
P_OEV1
P_OEV2
P_OEV3
P_UD
P_CPV
P_STVU
P_STVD
VGH
VGL1
FCC26
FCC30
P_LR
P_HCLK3
P_HCLK2
P_HCLK1
4", 5.6", 7"
HANSTAR 7"
+17V
-15V(4.5")
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J10
HANSTAR
VDL -10V
HANSTAR
VDL -10V
3.3V/5V
AGND
P_STVD
P_CPV
VGOFF1
-15V
VGL1
P_OEV1
AGND
3.3V/5V
VGH
P_UD
P_STVU
VCOM
P_STHR
3.3V/5V
AGND
A+5V
AGND
P_LR
R_OUT
G_OUT
B_OUT
P_HCLK1
P_HCLK2
P_HCLK3
P_STHL
P_OEH
)
"
4
.
8
/
"
7
/
"
5
.
6
(
V
2
1
-
3.3V/5V
AGND
+15V
-9.5V
+3.3 - +5V
AGND
3.3V/5V
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
)
)"
"4
5.
.8
4/
("
V7
3/
"
.5
3.
+6
(
V
5
+
VCOM
VCOM
P_OEV1
P_UD
P_CPV
P_STVU
P_STVD
VGH
VGL1
B_OUT
G_OUT
R_OUT
"
7
R"
A6
.
0
T5
"S
7NO
N
UAN
7 AHI
7
1
R
AGND
P_STHR
P_OEH
J7
AGND
A+5V
""
66
..
55 0
,
"
A
4T
UA
AD 6
7
1
R
P_HCLK1
P_HCLK2
P_HCLK3
P_STHL
P_STHR
P_OEH
P_OEV3
P_LR
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TRANS +17V / -15V
J9
)
)"
"4
5.
.8
4/
("
V7
3/
."
35
.
+6
(
V
5
+
B_OUT
G_OUT
R_OUT
TRANS +17V / -15V
TRANS +15V / -10V
J8
FCC30
+3.3V
+17V
+3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A+5V
AGND
VCOM
P_STVU
P_OEV3
P_OEV2
P_OEV1
P_CPV
P_UD
P_STVD
VGL1
-13V
AGND
3.3V/5V
VGH
+3.3V
+17V
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCOM
AGND
P_STHL
VBS
AGND
R_OUT
G_OUT
B_OUT
AGND
P_OEH
3.3V/5V
P_SMOD
AGND
P_HCLK1
P_HCLK2
P_HCLK3
AGND
A+5V
A+5V
P_STVU
P_OEV1
P_CPV
AGND
VDL
AGND
3.3V/5V
VGH
AGND
VCOM
-10V
+17V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FCC30_A
FCC30_A
FCC30_A
PVI 5"/(HANSTAR 5")/ADT 5"
PVI (4.5")/6.5"/7"/8.4"
VCOM
P_STHR
VBS
R_OUT
G_OUT
B_OUT
P_OEH
3.3V/5V
P_SMOD
P_HCLK1
P_HCLK2
P_HCLK3
P_LR
P_STHL
SAMSUNG 7"
SAMSUNG 5"
TOSHIBA 7"
INNOLUX 5.6"
DATA MODUL 5.6"
LCD Panel
1.0
2005.10.29
TCON(PP708A)
35
4
4
13.2) DC-DC Converter Circuit
R
E
W
O
P
C
D
/
C
D
INVERTER CON.
JP1
B7
1
2
3
0 Ohm
2
C
+5V
F
u
7
4
V
5
2
1
CO03
B6
F1
3
2
1
1 K
R 0
V 5
JP2
2
0 Ohm
1
C
FUSE 2A
3
C
2
R
F
u
7
4
V
5
2
F
u
1
0
.
0
K
0
1
DC 12V
T1 DC/DC TRANS
BOARD 1
TRANS 'B'
+5V / +7.5V / +17V / -15V
BOARD 2
TRANS 'C'
+5V / +7.5V / +13V / -16V
BOARD 3
TRANS 'A'
+5V / +7.5V / +15V / -10V
BOARD 4
TRANS 'B'
+5V / +7.5V / +17V / -15V
BOARD 5
TRANS 'B'
+5V / +7.5V / +17V / -15V
+5V
L2
D1
7
R
150uH
7
C
8
C
K
0
2
2
SS14
+5V
0
3
3
F
u
0
0
1
V
6
1
F
u
1
.
0
F
u
0
0
1
V
6
1
D
N
G
D
N
G
D
N
G
4
C
3
R
F
u
7
4
.
0
K
1
16
15
14
13
12
11
10
9
0
REF
SCP
IN2+
IN2FB2
DTC2
OUT2
VCC
1
1
R
1
1
C
0
1
R
K
2
2
F
p
0
7
4
CT
RT
IN1+
IN1FB1
DTC1
OUT1
GND
1
R
K
9
3
9
R
8
R
9
C
1
2
3
4
5
6
7
8
6
C
U1
D2
F
p
0
7
4
D
N
G
K
9
3
TL1451/BA9741
2
1
C
2
1
R
L3
F
u
7
4
.
0
4
1
R
4
1
C
3
1
C
3
1
R
K
8
1
68uH
+7.5V
L4
D3
22uH
F
u
1
.
0
F
u
7
4
V
6
1
F
u
7
4
V
6
1
5
1
R
8
1
C
6
1
R
0
1
+7.5V
4
5
VGH
22uH
C21
25V 10uF
D
N
G
-10V/-15V/-16V
BAT750
VGH
L5
D4
3
D
N
G
NC
+13V/+15V/+17V
2
F
u
1
.
0
GND
1
D
N
G
2
2
2
2
T
B
M
M
6
+5V
NC
2
2
C
7
VIN
NC
F
u
7
4
V
5
2
N
E
P
O
3
Q
2SD1119//D1766
8
PULSE
0
2
C
9
1
C
K
3
3
F
p
0
7
4
7
1
R
9
D
N
G
T1
10
Q2
D
N
G
D
N
G
K
3
3
MMBT2907
Q1
+7.5V
6
1
C
7
1
C
5
1
C
F
u
7
4
V
5
2
F
u
1
0
2
1
0
6
5
BAT750
8
1
R
DC/DC TRANS
L
G
V
9
1
R
K
3
3
K
1
5
L6
D5
3
2
C
4
2
C
BAT750
VGL
22uH
C25
F
u
1
.
0
F
u
7
4
V
5
2
2
R
V
25V 10uF
D
N
G
D
N
G
D
N
G
K
0
1
0
2
R
K
5
1
D
N
G
B1
D
N
G
0 Ohm
DC / DC POWER
1.0
2005.10.29
TCON(PP708A)
36
1
4