19-0737; Rev 0; 2/07 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs The MAX8784 generates supply rails for the thin-film transistor (TFT) liquid-crystal display (LCD) panels in TVs and monitors. It includes a step-up regulator, a regulated positive and a negative charge-pump, three high-current operational amplifiers, and Dual Mode™, logic-controlled, high-voltage switch control block. HVS mode automatically increases the output voltages of the boost regulator and the positive charge-pump to stress test display panels during production. The MAX8784 can operate from input voltages of 4V to 5.5V and is optimized for LCD TV panel and LCD monitor applications. The step-up DC-DC regulator provides a regulated supply voltage for TFT source drivers. The step-up regulator is a high-frequency (1.2MHz), high-efficiency, currentmode regulator. The step-up regulator has a built-in 110mΩ (typ) power MOSFET. The high-switching frequency allows the use of ultra-small inductors and ceramic capacitors. The current-mode architecture provides fast transient response and easy compensation. The step-up regulator features output undervoltage protection, soft-start, internal current limit, and adjustable output voltage by an external resistive divider. The three operational amplifiers drive the LCD backplane and the gamma-correction-divider string. Each operational amplifier has a fast slew rate (45V/µs), a wide bandwidth (20MHz), and a high-output short-circuit current (200mA). Each op amp has rail-to-rail input and rail-to-rail output operation. The positive charge-pump regulator and the negative charge-pump regulator provide regulated supply voltages for the TFT gate drivers. The positive charge pump is a two-stage charge pump, which requires no external diodes. The output voltages of both charge pumps are resistor adjustable. The logic-controlled high-voltage switch allows the manipulation of the positive TFT gate-driver supply. Features o Step-Up Regulator Supply for LCD Panel Source Driver Fast Transient Response to Pulsed Load Built-In 18V, 4A, 0.11Ω n-Channel Power MOSFET with Lossless Current Sensing Cycle-by-Cycle Current-Limit Comparator 90% Efficiency (5V In to 15V Out) 1.2MHz Switching Frequency o Three High-Current 19V Operational Amplifiers 180mA Output Short-Circuit Current 45V/µs Slew Rate 20MHz Bandwidth Rail-to-Rail Input and Output Operation o Regulated Charge-Pump Tripler with Integrated Diodes for TFT Gate-On Supply o Regulated Charge Pump for TFT Gate-Off Supply o Built-In Sequencing Internal Digital Soft-Start 36V Gate-On Switch Startup Timing Capacitors for AVDD and GON o Undervoltage and Thermal Protection o 4V to 5.5V Input Operating Range Simplified Operating Circuit STEP-UP OUTPUT VIN LX VCC POS1 TO VCOM STEP-UP OUTPUT TO VCOM PGND NEG1 OUT1 FB POS2 NEG2 COMP OUT2 TO VCOM The MAX8784 is available in a small (5mm x 5mm), lowprofile (0.8mm), 40-pin thin QFN package and operates over the -40°C to +85°C temperature range. VIN POS3 RSET OUT3 GDEL ADEL HVS REF MAX8784 CTL AGND Applications SHDN FBN LCD TVs and LCD Monitors Ordering Information GON TCON ON/OFF VGON DRN VGOFF POUT DRVN PART MAX8784ETL+ TEMP RANGE -40°C to +85°C PINPACKAGE 40 Thin QFN 5mm x 5mm PKG CODE PGND FBP T4055-1 +Denotes a lead-free package. SUP C1N C1P C2N STEP-UP OUTPUT C2P STEP-UP OUTPUT Dual Mode is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8784 General Description MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs ABSOLUTE MAXIMUM RATINGS VCC, CTL, HVS, SHDN, ADEL, GDEL to AGND ....-0.3V to +7.5V REF, COMP, FB, FBN, FBP to AGND .........-0.3V to (VCC + 0.3V) POS1, NEG1, POS2, NEG2, POS3, OUT1, OUT2, OUT3 to AGND .......................................-0.3V to (VSUP + 0.3) PGND, BGND to AGND.........................................-0.3V to +0.3V LX, RSET to PGND .................................................-0.3V to +22V SUP to AGND .........................................................-0.3V to +22V DRVN to AGND.........................................-0.3V to (VSUP + 0.3V) C1N, C2N to AGND ..................................-0.3V to (VSUP + 0.3V) C1P to AGND .........................................................-0.3V to +30V POUT to C2P, C1P to C2P......................................-0.3V to +22V C2P, POUT to AGND..............................................-0.3V to +40V GON, DRN to AGND ..............................................-0.3V to +40V DRN to GON............................................................-30V to +30V REF Short Circuit to AGND.........................................Continuous RMS VCC Current ................................................................50mA RMS DRVN Current...........................................................400mA LX, PGND RMS Current Rating.............................................2.4A Continuous Power Dissipation (TA = +70°C) 40-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS VCC Input Supply Range VCC Undervoltage Lockout Threshold MIN VCC rising, typical hysteresis = 50mV 2.4 VFB = 1.3V, not switching VCC Quiescent Current TYP 4.0 2.6 MAX UNITS 5.5 V 2.8 V 6 mA 1.0 VFB = 1.1V, switching, no load, VSUP disconnected, VFBP = VCC, VFBN = 0V 4 SHDN = GND 0.05 SHDN Input Low Voltage SHDN Input High Voltage 1.8 SHDN Input Current -1 0.8 V +1 µA V REFERENCE REF Output Voltage No external load REF Load Regulation 0 < ILOAD < 50µA REF Sink Current In regulation REF Undervoltage Lockout Threshold Rising edge, typical hysteresis = 200mV 1.238 1.250 1.262 V 10 mV 10 µA 1.0 1.15 V kHz OSCILLATOR and TIMING Frequency 1000 1200 1400 Oscillator Maximum Duty Cycle 87 90 93 % Duration to Trigger Fault Condition 47 55 65 ms ADEL, GDEL Capacitor Charge Current 4 ADEL, GDEL Turn-On Threshold 5 6 µA 1.25 1.32 V STEP-UP REGULATOR FB = COMP, CCOMP = 1nF 1.235 1.246 1.256 FB = COMP, CCOMP = 1nF, +25°C to +85°C 1.238 1.246 1.256 FB Fault-Trip Level Falling edge 0.96 1.00 1.04 FB Load Regulation 0 < ILOAD < full -1 % FB Line Regulation VCC = 4.5V to 5.5V 0.25 %/V FB Input Bias Current VFB = 1.25V 100 FB Regulation Voltage 2 _______________________________________________________________________________________ 200 V V nA Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) MIN TYP MAX UNITS FB Transconductance PARAMETER ΔICOMP = ±2.5µA, FB = COMP CONDITIONS 75 160 280 µS LX Current Limit VFB = 1.1V, duty cycle = 75% 3.5 LX On-Resistance ILX = 1.0A Current-Sense Transresistance Soft-Start Period 0.10 7-bit current ramp 4.0 4.6 A 0.10 0.19 Ω 0.20 0.26 V/A 3 ms POSITIVE CHARGE-PUMP REGULATOR VSUP Input Supply Range VSUP Overvoltage Charge-Pump Inhibit 6 VSUP = rising, typical hysteresis = 200mV FBP Regulation Voltage FBP Line Regulation Error VSUP = 10V ~ 19V, VPOUT = 28V FBP Input Bias Current VFBP = 1.5V POUT Output-Voltage Range IVGON = 0mA POUT Fixed Output Voltage HVS = VCC, IPOUT = 0mA POUT Output Current Limit Not in dropout, VSUP = 9V, VPOUT = 24V 19 V V 20 21 22 1.225 1.25 1.275 0.1 -100 29.1 30 20 50 V %/V +100 nA 36 V 30.9 V mA C1N, C2N High-Side On-Resistance 9.0 Ω C1N, C2N Low-Side On-Resistance 6.0 Ω C1P Switch On-Resistance 15.0 Ω C2P Switch On-Resistance 10.0 Ω POUT Switch On-Resistance 10.0 Ω FBP Fault-Trip Level Falling edge 0.96 Positive Charge-Pump Soft-Start Period 7-bit voltage ramp 1.00 1.04 3 V ms NEGATIVE CHARGE-PUMP REGULATOR FBN Regulation Voltage VREF - VFBN FBN Input Bias Current VFBN = 250mV FBN Line Regulation Error VSUP = 11V to 19V, VGOFF = -9V, IVGOFF = -20mA 0.985 1.00 -50 1.015 V +50 nA 0.1 %/V DRVN PCH On-Resistance 10 Ω DRVN NCH On-Resistance 6 Ω FBN Fault-Trip Level Rising edge Negative Charge-Pump Soft-Start Period 7-bit voltage ramp 450 mV 3 ms POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES CTL Input-Low Voltage CTL Input-High Voltage CTL Input Current 0.8 V +1 µA 1.8 CTL = 0V or VCC V -1 CTL-to-GON Rising Propagation Delay 200 CTL-to-GON Falling Propagation Delay 200 GON-to-POUT Switch On-Resistance VGDEL = 1.5V, CTL = VCC GON-to-POUT Switch Saturation Current VPOUT - VGON > 5V GON-to-DRN Switch On-Resistance VGDEL = 1.5V, CTL = 0V GON-to-DRN Switch Saturation Current VGON - VDRN > 5V GON-to-PGND Switch On-Resistance VGDEL = 1.0V 10 ns ns 20 180 Ω mA 60 35 Ω mA 100 kΩ _______________________________________________________________________________________ 3 MAX8784 ELECTRICAL CHARACTERISTICS (continued) MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 19 V 20 21.0 V OPERATIONAL AMPLIFIERS SUP Supply Range SUP Overvoltage Fault Threshold 6 (Note 1) 19.1 SUP Supply Current Buffer configuration, VPOSx = VSUP / 2, no load Input Offset Voltage VNEGx, VPOSx = VSUP / 2, Input Bias Current VNEGx, VPOSx = VSUP / 2 Input Common-Mode Voltage Range Input Common-Mode Rejection Ratio -1 0 1V < VNEGx, VPOSx < (VSUP - 1) 15 mA 12 mV +1 µA VSUP 80 IOUTx = 1mA VSUP 50 IOUTx = 25mA VSUP 300 Output Voltage-Swing High Output Voltage-Swing Low 11 V dB mV IOUTx = -1mA 50 IOUTx = -25mA 300 Large-Signal Voltage Gain VOUTx = 1V to VSUP - 1V Slew Rate CLOAD = 20pF 45 V/µs -3dB Bandwidth CLOAD = 20pF 20 MHz Short to VSUP / 2, sourcing 140 Short to VSUP / 2, sinking 220 Short-Circuit Current 80 mV dB mA HVS FUNCTION HVS Input-Low Voltage HVS Input-High Voltage 0.8 V 10 50 kΩ 5 20 Ω 1 µA MAX UNITS 1.8 HVS Input Pulldown Resistance 5 RSET Output On-Resistance HVS = VCC RSET Output Leakage HVS = AGND V ELECTRICAL CHARACTERISTICS (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS VCC Input Supply Range VCC Undervoltage Lockout Threshold VCC rising, typical hysteresis = 50mV VCC Quiescent Current VFB = 1.1V, switching, no load, AVDD isolated from SUP, VFBP = VCC, VFBN = 0V MIN TYP 4.0 5.5 V 2.4 2.8 V 6 SHDN = GND SHDN Input-Low Voltage SHDN Input-High Voltage 4 mA 0.05 0.8 1.8 _______________________________________________________________________________________ V V Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS REFERENCE REF Output Voltage No external load REF Load Regulation 0 < ILOAD < 50µA REF Sink Current In regulation REF Undervoltage Lockout Threshold Rising edge, typical hysteresis = 200mV 1.232 1.262 V 10 mV 10 µA 1.15 V kHz OSCILLATOR AND TIMING Frequency 950 1400 Oscillator Maximum Duty Cycle 87 93 % Duration-to-Trigger Fault Condition 47 69 ms ADEL, GDEL Capacitor Charge Current ADEL, GDEL Turn-On Threshold 4 6 µA 1.18 1.32 V STEP-UP REGULATOR FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.230 1.262 V FB Fault Trip Level Falling edge 0.96 1.04 V FB Transconductance ΔICOMP = ±2.5µA, FB = COMP 75 280 µS LX Current Limit VFB = 1.1V, duty cycle = 75% 3.0 LX On-Resistance ILX = 1.0A Current-Sense Transresistance 5.0 A 0.19 Ω 0.10 0.26 V/A POSITIVE CHARGE-PUMP REGULATOR VSUP Input Supply Range VSUP Overvoltage Charge-Pump Inhibit VSUP = rising, typical hysteresis = 200mV FBP Regulation Voltage 6 19 V 20 22 V 1.225 1.275 nA POUT Output-Voltage Range IPOUT = 0mA VSUP 36 V POUT Fixed-Output Voltage HVS = VCC, IPOUT = 0mA 29.1 30.9 V POUT Output-Current Limit Not in dropout, VSUP = 9V VPOUT = 24V 20 mA C1N, C2N High-Side On-Resistance 9 Ω C1N, C2N Low-Side On-Resistance 6 Ω C1P Switch On-Resistance 15 Ω CP2 Switch On-Resistance 10 Ω POUT Switch On-Resistance 10 Ω 0.96 1.04 V 0.985 1.015 V FBP fault trip level Falling edge NEGATIVE CHARGE-PUMP REGULATOR FBN Regulation Voltage VREF - VFBN DRVN PCH On-Resistance 10 Ω DRVN NCH On-Resistance 6 Ω _______________________________________________________________________________________ 5 MAX8784 ELECTRICAL CHARACTERISTICS (continued) MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES CTL Input-Low Voltage 0.8 CTL Input-High Voltage 1.8 GON-to-POUT Switch On-Resistance GON-to-POUT Switch Saturation GDEL = 1.5V, CTL = VCC VPOUT - VGON > 5V GON-to-DRN Switch On-Resistance GDEL = 1.5V, CTL = 0V GON-to-DRN Switch Saturation Current VGON - VDRN > 5V V V 20 180 Ω mA 60 35 Ω mA OPERATIONAL AMPLIFIERS SUP Supply Range SUP Overvoltage Fault Threshold (Note 1) 6 19 V 19.1 21.0 V SUP Supply Current Buffer configuration, VPOS = VSUP / 2, no load 15 mA Input Offset Voltage VNEG, VPOS = VSUP / 2 13 mV VSUP V Input Common-Mode Voltage Range 0 IOUT = 1mA VSUP 50 IOUT = 25mA VSUP 300 mV Output-Voltage Swing High Output-Voltage Swing Low IOUT = -1mA 50 IOUT = -25mA 300 mV HVS FUNCTION HVS Input-Low Voltage 0.8 HVS Input-High Voltage 1.8 HVS Input Pulldown Resistance RSET Output On-Resistance 5 HVS = VCC Note 1: Step-up regulator switching is disabled above the threshold. This fault is not latched. Note 2: -40°C specs are guaranteed by design, not production tested. 6 _______________________________________________________________________________________ V V 50 kΩ 20 Ω Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs 83 79 5 0.2 4 IVCC (mA) AVDD ERROR (%) 0.6 87 -0.2 75 200 400 800 600 3 NOT SWITCHING 2 0 -1.0 0 200 LOAD CURRENT (mA) 400 600 4.0 800 4.4 4.8 VCC QUIESCENT CURRENT vs. TEMPERATURE 5.2 5.6 6.0 VCC (V) LOAD CURRENT (mA) STEP-UP REGULATOR SOFT-START (HEAVY LOAD) MAX8784 toc05 5 4 MAX8784 toc04 0 SWITCHING 1 -0.6 IVCC (mA) EFFICIENCY (%) 91 1.0 MAX8784 toc02 FOSC = 1.2MHz VIN = 5.0V MAX8784 toc01 95 VCC QUIESCENT CURRENT vs. VCC STEP-UP REGULATOR LOAD REGULATION MAX8784 toc03 STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT SWITCHING LX 3 ILOAD 2 NOT SWITCHING IL 1 AVDD 0 -40 -15 10 35 60 10ms/div 85 TEMPERATURE (°C) IL: 20A/div AVDD: 10V/div LX: 10V/div ILOAD: 500mA/div STEP-UP REGULATOR PULSED LOAD TRANSIENT RESPONSE STEP-UP REGULATOR LOAD TRANSIENT RESPONSE MAX8784 toc07 MAX8784 toc06 AVDD ILOAD IL IL 0A AVDD IAVDD 0A 20μs/div ILOAD: 200mA/div IL: 1A/div AVDD: 100mV/div (AC-COUPLED) 10μs/div AVDD : 200mV/div (AC-COUPLED) IL : 1A/div IAVDD : 1A/div IAVDD : 0.3A TO 1.3A, 2μs PULSE _______________________________________________________________________________________ 7 MAX8784 Typical Operating Characteristics (Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25°C, unless otherwise noted.) TIMER-DELAY LATCH RESPONSE TO OVERLOAD SWITCHING FREQUENCY vs. VCC MAX8784 toc08 LX AVDD MAX8784 toc09 SWITCHING FREQUENCY (MHz) 1.5 IL 1.4 1.3 1.2 1.1 1.0 10ms/div 4.0 4.4 4.8 8.6 1.2502 8.2 10 50 40 12 14 1 0 -1 18 MAX8784 toc12 6 20 9 12 15 18 21 VSUP (V) NEGATIVE CHARGE-PUMP REGULATOR LINE REGULATION NEGATIVE CHARGE-PUMP REGULATOR LOAD REGULATION MAX8784 toc114 2 OUTPUT-VOLTAGE ERROR (%) MAX8784 toc13 2 -1 VSUP (V) IREF (μA) POSITIVE CHARGE-PUMP REGULATOR LOAD REGULATION 16 1 0 -1 2 OUTPUT-VOLTAGE ERROR (%) 30 0 -2 8.0 1.2500 1 MAX8784 toc15 1.2504 8.4 20 6.0 2 OUTPUT-VOLTAGE ERROR (%) 8.8 ISUP (mA) 1.2506 ALL OUTPUTS ENABLED MAX8784 toc11 1.2508 VREF (V) 9.0 MAX8784 toc10 1.2510 10 5.6 POSITIVE CHARGE-PUMP REGULATOR LINE REGULATION SUP SUPPLY CURRENT vs. SUP VOLTAGE REFERENCE LOAD REGULATION 0 5.2 VCC (V) AVDD: 10V/div LX: 10V/div IL: 5A/div OUTPUT VOLTAGE ERROR (%) MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs 1 VSUP = 16.0V 0 -1 VSUP = 13.5V 0 10 20 30 IPOUT (mA) 8 -2 -2 -2 40 50 60 8 10 12 14 VSUP (V) 16 18 20 0 50 100 150 IVGOFF (mA) _______________________________________________________________________________________ 200 250 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs HIGH-VOLTAGE SWITCH CONTROL FUNCTION OPERATIONAL AMPLIFIER FREQUENCY RESPONSE MAX8784 toc16 MAX8784 toc17 6 CGON = 1.5nF RDRN = 1kΩ TO AVDD 3 CTL GAIN (dB) CLOAD = 15pF 0 -3 GON -6 CLOAD = 56pF CLOAD = 33pF -9 10μs/div CTL: 5V/div 0.1 GON: 10V/div 1 10 100 FREQUENCY ( MHz) OPERATIONAL AMPLIFIER RAIL-TO-RAIL OPERATION OPERATIONAL AMPLIFIER LOAD-TRANSIENT RESPONSE MAX8784 toc18 MAX8784 toc19 VOUT1 OUT1 POS1 ILOAD 2μs/div POS1: 5V/div 2μs/div OUT1: 5V/div VOUT1: 200mV/div ILOAD: 100mA/div OPERATIONAL AMPLIFIER SMALL-SIGNAL STEP RESPONSE OPERATIONAL AMPLIFIER LARGE-SIGNAL RESPONSE MAX8784 toc21 MAX8784 toc20 POS1 OUT1 OUT1 POS1 100ns/div 200ns/div OUT1: 5V/div POS1: 5V/div POS1: 50mV/div (AC-COUPLED) OUT1: 50mV/div (AC-COUPLED) _______________________________________________________________________________________ 9 MAX8784 Typical Operating Characteristics (continued) (Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25°C, unless otherwise noted.) Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784 Pin Description PIN NAME 1 C1N Negative Terminal of Flying Capacitor C1 FUNCTION 2 C1P Positive Terminal of Flying Capacitor C1 3 BGND 4 SUP Operational Amplifier and Charge-Pump Supply Ground Operational Amplifier and Charge-Pump Supply Input. Connect SUP to AVDD. Bypass SUP to BGND with 0.1µF capacitor. 5 POS1 Operational Amplifier Noninverting Input 6 NEG1 Operational Amplifier Inverting Input 7 OUT1 Operational Amplifier Output 8 OUT2 Operational Amplifier Output 9 NEG2 Operational Amplifier Inverting Input 10 POS2 Operational Amplifier Noninverting Input 11 POS3 Operational Amplifier Noninverting Input 12 OUT3 Operational Amplifier Output 13, 19, 20, 26 N.C. No Connection. Not internally connected. 14 ADEL Step-Up Regulator Delay Input. Connect a capacitor from ADEL to AGND to set the delay time. A 5µA current source charges CADEL. ADEL is internally pulled to AGND by a 20Ω resistor in shutdown. For details, see the Power-Up Sequence section. 15 GDEL Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input. Connect a capacitor from GDEL to AGND to set the delay time. A 5µA current source charges CGDEL. GDEL is internally pulled to AGND by a 20Ω resistor in shutdown. For details, see the Power-Up Sequence section. 16 CTL High-Voltage Switch Control Input. When CTL is high, the switch between GON and POUT is turned on and the switch between GON and DRN is turned off. When CTL is low, the switch between GON and DRN is turned on and the switch between GON and POUT is turned off. For details, see the High-Voltage Switch Control section. 17 HVS HVS Mode Input. Connect HVS to VCC to enable HVS mode. For details, see the HVS Mode section. 18 DRVN Negative Charge-Pump Regulator Output. Connect DRVN to the negative charge-pump flying capacitor(s). FBN Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-divider between the negative output and REF. Place the resistive voltage-divider within 5mm of FBN. For details, see the Output-Voltage Selection section. 22 REF Reference Output. Connect a 0.22µF capacitor from REF to AGND. 23 AGND 24 VCC 25 SHDN 27, 28 PGND 21 29, 30 10 LX Analog Ground VCC Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage and bypass VCC to AGND with a minimum 1µF ceramic capacitor. Active-Low Shutdown. When SHDN is low, the device enters its low-power shutdown mode. Power Ground Step-Up Regulator Switching Node. Connect inductor and Schottky diode to LX and minimize trace area for lowest EMI. ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs PIN NAME 31 AGND Analog GND FUNCTION 32 RSET Open-Drain HVS Mode Output. For details, see the HVS Mode section. 33 COMP Error-Amplifier Output. Connect a series RC network from COMP to AGND for compensation. 34 FB 35 GON 36 DRN High-Voltage Switch Drain. Drain of the internal low-side, back-to-back p-channel MOSFET. 37 FBP Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-divider between POUT and AGND. Place the resistive voltage-divider within 5mm of FBP. For details, see the OutputVoltage Selection section. 38 POUT 39 C2P Positive Terminal of Flying Capacitor C2 40 C2N Negative Terminal of Flying Capacitor C2 Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the stepup regulator output and AGND. Place the resistive voltage-divider within 5mm of FB. For details, see the Output-Voltage Selection section. Internal High-Voltage Switch Common Terminal. GON common terminal between the high-side p-channel MOSFET and back-to-back p-channel MOSFET. GON is internally pulled to PGND by a 100kΩ resistor in shutdown. Positive Charge-Pump Output and High-Voltage Switch Source Input ______________________________________________________________________________________ 11 MAX8784 Pin Description (continued) MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs VIN = 4.5V TO 5.5V C14 10μF L1 3μH C15 10μF PGND POS1 NEG1 OUT1 VCOM AVDD VCOM FB R9 100kΩ OUT2 R8 82kΩ RSET VCOM OUT3 BGND GDEL MAX8784 C10 0.01μF ADEL C9 0.1μF HVS REF R3 20kΩ R10 20kΩ C11 330pF POS3 R2 10kΩ AVDD 14V, 0.75A R11 204kΩ COMP POS2 NEG2 R1 10kΩ C13 10μF LX VCC C1 1μF D1 C12 10μF C2 0.22μF CTL AGND SHDN TCON VIN VGON 28V, 20mA GON FBN DRN R4 187kΩ D2 VGOFF -9V, 20mA POUT C4 1μF R6 428kΩ DRVN C3 10μF SUP AVDD C1N C5 0.1μF C1P C2N C6 0.1μF C2P R7 1kΩ AVDD FBP PGND C8 1μF R5 20kΩ C7 0.1μF BGND Figure 1. Typical Operating Circuit Typical Operating Circuit The typical operating circuit (Figure 1) of the MAX8784 is a power-supply system for TFT LCD panels in monitors and TVs. The circuit generates a +14V source-driver supply, a +28V positive gate-driver supply, and a -9V negative gate-driver supply from a 5V ±10% input supply. Table 1 lists the selected components and Table 2 lists the contact information of the component suppliers. Table 1. Component List C1 C14, C15 10µF ±20%, 6.3V X5R ceramic capacitors (0603) TDK C1608X5R0J106M C12, C13 10µF ±20%, 16V X5R ceramic capacitors (1206) TDK C3216X5R1C106M D1 3A, 30V Schottky diode (M-flat) Toshiba CMS02 (top mark S2) D2 220mA, 100V dual diode (SOT23) Fairchild MMBD4148SE (top mark D4) L1 3.0µH, 3ADC inductor Sumida CDRH6D28-3R0 Detailed Description The MAX8784 is a multiple-output power supply designed primarily for TFT LCD panels used in monitors 12 1µF ±10%, 6.3V X5R ceramic capacitor (0402) TDK C1005X5R0J105K ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs SUPPLIER PHONE FAX Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com Sumida 847-545-6700 847-545-6720 www.sumida.com TDK 847-803-6100 847-390-4405 www.component.tdk.com Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec MAX8784 Table 2. Component Suppliers WEBSITE VIN POS1 SHDN SUP NEG1 LX AVDD OSC OUT1 BOOST POS2 NEG2 PGND FB OUT2 COMP POS3 100kΩ 330pF MAX8784 RSET OUT3 HVS VIN BGND HVS CONTROL BLOCK ADEL SEQUENCE CONTROL GDEL VCC CTL REF REF HV SWITCH BLOCK GON DRN FROM TCON VGON AGND POUT FBN VGOFF DRVN NEGATIVE REGULATOR POSITIVECHARGE PUMP BGND SUP C1N C1P AVDD FBP C2N C2P AVDD Figure 2. Functional Diagram and TVs. It has a step-up switching regulator to generate the source-driver supply, two charge-pump regulators to generate the positive and negative gate-driver supplies, and three high-current operational amplifiers. Each regulator features an adjustable output voltage and digital soft-start. The step-up regulator has cycleby-cycle current limiting and uses a fixed-frequency current-mode control architecture with fast transient response and excellent line regulation. The MAX8784 features a high-voltage switch-control block, a very stable reference output, well-defined power-up and power-down sequences, and thermaloverload protection. Figure 2 shows the MAX8784 functional block diagram. ______________________________________________________________________________________ 13 MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Step-Up Regulator The step-up regulator employs a current-mode, fixedfrequency PWM architecture to maximize loop bandwidth and to provide fast-transient response to pulsed loads typical of TFT LCD panel source drivers. The integrated MOSFET and the built-in digital soft-start function reduce the number of external components required to control inrush currents. The output voltage can be set from VIN to 19V with an external resistive voltage-divider. The regulator controls the output voltage and output power by modulating the duty cycle (D) of the internal power MOSFET in each switching cycle. The duty cycle of the MOSFET is approximated by: LX CLOCK LOGIC AND DRIVER SOFTSTART PWM Control Block Figure 3 is the block diagram of the step-up regulator controller. On the rising edge of the internal oscillator clock, the controller sets a flip-flop, turning on the nchannel MOSFET, which applies the input voltage across the inductor. The current through the inductor ramps up linearly. The transconductance error amplifier compares the FB voltage with the reference voltage. The error amplifier changes the COMP voltage by charging or discharging the COMP capacitor. The COMP voltage is compared with a ramp, which is the sum of the current-sense signal and a slope compensation signal. Once the ramp signal exceeds the COMP voltage, the controller resets the flip-flop and turns off the MOSFET. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the Schottky diode (D1 in Figure 1). The voltage across the inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp down, transferring the energy stored in the magnetic field to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle. 14 ILIMIT SS SLOPE COMP V −V D ≈ AVDD IN VAVDD where VAVDD is the output voltage of the step-up regulator. PGND CURRENT-LIMIT COMPARATOR PWM COMPARATOR CURRENT SENSE OSCILLATOR TO FAULT LOGIC 1.0V ERROR AMP UNDERVOLTAGE COMPARATOR FB 1.25V COMP FREQ Figure 3. Step-Up Regulator PWM Control Block Diagram Soft-Start and Fault Protection The step-up regulator achieves soft-start by linearly ramping up its internal current limit. The soft-start terminates when the output reaches regulation or the full current limit has been reached. The current limit rises from zero to the full current limit in approximately 3ms. The soft-start feature effectively limits the inrush current during startup (see the Step-Up Regulator Soft-Start waveforms in the Typical Operating Characteristics). The MAX8784 monitors FB for undervoltage conditions. If the voltage is continuously below 80% of the nominal regulation point for approximately 55ms, the MAX8784 sets the fault latch, shutting down all outputs except the reference and the operational amplifier. ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs SUP Ø2 Ø1 P1 01 GND C1N Ø2 P2 Ø1 P3 C6 C1P C2P POUT C7 C8 C2N LCD DISABLE COMPARATOR Ø1 CONTROLLER DISABLE Ø2 1.1*REF ERROR AMPLIFIER FBP REF Figure 4. Positive Charge-Pump Regulator Control Block Diagram (Figure 4) is charged by the charge-pump supply input and the second stage flying capacitor C7 is discharged into the reservoir capacitor C8. After a fixed period, P2 is turned on and P1 and P3 are turned off while C1N is pulled to SUP and C2N is pulled to GND. C7 is charged by C6 in preparation for the next pump cycle. The MAX8784 implements a digital variable-resistance algorithm to control the current delivered to the output. The algorithm sets the on-resistance of the positive charge-pump drivers according to the load current. The on-resistance of the drivers is set by counting the number of charging pulses in the previous 12 oscillator cycles. As the number of charging pulses in the previous 12 oscillator cycles increases, the on-resistance of the switch is reduced. The number of charging pulses in the previous 12 oscillator cycles is a measure of the load current. The period of C1N and C2N switching is 1.66µs. The positive charge-pump regulator’s startup can be delayed by connecting an external capacitor from GDEL to GND. An internal constant-current source begins charging the GDEL capacitor when the negative charge pump reaches regulation. When the GDEL voltage exceeds VREF, the positive charge-pump regulator is enabled. Each time it is enabled, the positive chargepump regulator goes through a soft-start routine by ramping up its internal reference voltage from 0 to VREF in 128 steps. The soft-start period is 3ms (typ) and FBP fault detection is disabled during this period. The softstart feature effectively limits the inrush current during startup. The MAX8784 monitors the FBP and SUP voltage to detect fault conditions. If VFBP is continuously below 80% of its nominal regulation point for approximately 55ms, the MAX8784 sets a fault latch, shutting down all outputs except the reference and operational amplifiers. If SUP exceeds the SUP overvoltage faut threshold (20V, typ), LX switching is inhibited until SUP decreases. Further, If SUP exceeds its overvoltage charge-pump inhibit level (21V, typ), positive charge-pump switching is inhibited until SUP decreases to prevent damage to the charge pump. ______________________________________________________________________________________ 15 MAX8784 Positive Charge-Pump Regulator The positive charge-pump regulator is typically used to generate the positive supply rail for the TFT LCD gate driver ICs. The positive charge pump is a two-stage charge pump with external pump and reservoir capacitors. The output voltage is set with an external resistive voltage-divider from its output to GND with the midpoint connected to FBP. The charge pump includes internal switches with drivers to control the power transfer. Figure 4 shows the block diagram of the positive charge pump. The controller regulates the positive charge-pump output voltage such that VFBP = VREF. If VFBP goes below the reference, P1 and P3 are turned on when the rising edge of the oscillator arrives, while the drivers pull C1N to GND and C2N to SUP. The first stage flying capacitor C6 MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Negative Charge-Pump Regulator The negative charge-pump regulator (see Figure 5) generates the negative supply rail for the TFT LCD gate driver ICs. The output voltage is set with an external resistive voltage-divider from its output to REF with the midpoint connected to FBN. The number of chargepump stages and the setting of the feedback divider determine the output voltage of the negative chargepump regulator. The charge-pump controller includes a high-side p-channel MOSFET (P4) and a low-side nchannel MOSFET (N4) to control the power transfer as shown in Figure 7. The error comparator compares the feedback signal (FBN) with a 250mV internal reference. If the feedback signal is above the reference, the charge-pump regulator turns on N4 and turns off P4 when the rising edge of the oscillator clock arrives, level shifting C(NEG) in parallel with the reservoir capacitor COUT(NEG). If the voltage across COUT(NEG) minus a diode drop (VNEG VDIODE) is higher than the level-shifted flying capacitor voltage (-V C(NEG) ), charge flow from C OUT(NEG) to C(NEG) until the diode D2-B turns off. The falling edge of the oscillator clock turns off N4 and turns on P4, allowing VSUP to charge up flying capacitor C(NEG) through diode D2-A. If the feedback signal is below the reference when the rising edge of the oscillator comes, the regulator ignores this clock edge and keeps P4 on and N4 off. The negative charge-pump regulator is enabled when the step-up regulator reaches regulation. Each time it is enabled, the negative charge-pump regulator goes through a soft-start routine by ramping down its internal reference voltage from 1.25V to 250mV in 128 steps. The soft-start period is 3ms (typ) and FBN fault detection is disabled during this period. The soft-start feature effectively limits the inrush current during startup. The MAX8784 monitors FBN voltage for undervoltage conditions. If V FBN is continuously above 450mV for approximately 55ms, the MAX8784 sets a fault latch, shutting down all outputs except the reference and the operational amplifiers. High-Voltage Switch Control The MAX8784’s high-voltage switch control block (Figure 6) consists of three high-voltage p-channel MOSFETs: Q1, between POUT and GON, Q2 and Q3 between GON and DRN. Q2 and Q3 are arranged back-to-back so that GON can be either above or below DRN. The switch control block is enabled when VGDEL goes above VREF. VCC SWITCH CONTROL 5μA GDEL Q4 ERROR COMPARATOR FAULT SHDN FBN SOFT-START DONE POUT SUP 0.25V Q1 VREF GON P4 OSC A C Q2 DRVN D2 B 100kΩ N4 VGOFF GND1 Q3 COUT DRN CTL Q5 FBN Figure 5. Negative Charge-Pump Regulator Block Diagram 16 REF Figure 6. High-Voltage Switch Control Block Diagram ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Operational Amplifier The MAX8784 has three operational amplifiers that are typically used to drive the LCD backplane (VCOM) or the gamma-correction divider string. Each operational amplifier features 140mA/220mA (source/sink) output short-circuit current, 45V/µs slew rate, and 20MHz bandwidth. While the op amp is a rail-to-rail input and output design, its accuracy is significantly degraded for input voltages within 1V of its supply rails (SUP, BGND). Short-Circuit Current Limit The operational amplifier limits short-circuit current to approximately 140mA if the output is shorted to AGND and to approximately -220mA if the output is shorted to AVDD. If the short-circuit condition persists, the junction temperature of the IC rises until it reaches the thermal-shutdown threshold (+160°C typ). Once the junction temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately sets the thermal-fault latch, shutting off the main step-up regulator, the charge pumps, the high-voltage switch control block, and the operational amplifier. Those portions of the device remain inactive until the input voltage is cycled. Driving Pure Capacitive Loads The operational amplifier is typically used to drive the LCD backplane (VCOM). The LCD backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. However, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. As the operational amplifier’s capacitive load increases, the amplifier’s bandwidth decreases and gain peaking increases. A 5Ω to 50Ω small resistor placed between VCOM and the capacitive load reduces peaking, but also reduces the gain. An alternative method of reducing peaking is to place a series RC network (snubber) in parallel with the capacitive load. The RC network does not continuously load the output or reduce the gain. Reference Voltage The reference voltage is nominally 1.246V, and can source at least 50µA (see the Typical Operating Characteristics). VCC is the input of the internal reference block. Bypass REF with a 0.22µF ceramic capacitor connected between REF and GND. Power-Up Sequence The MAX8784 operational amplifier and internal reference are enabled when VCC exceeds its UVLO threshold. A 5µA current charges ADEL after the internal reference reaches regulation. The step-up regulator starts the soft-start sequence after ADEL is charged to VREF. The FB fault-detection circuit is enabled and the negative charge-pump regulator starts up after the step-up regulator reaches regulation. The FBN faultdetection circuit is enabled and a 5µA current charges GDEL after the negative charge pump reaches regulation. The positive charge pump starts its soft-start sequence after GDEL is charged to 1.25V (typ). The FBP fault-detection circuit is enabled after the positivecharge pump reaches regulation. Power-Down Control The MAX8784 disables the step-up regulator, positive charge-pump regulator, negative charge-pump regulator, and high-voltage switch control block when SHDN is logic low. The operational amplifier depends only upon the supply voltage at SUP. Fault Protection During steady-state operation, if any output of the three regulators (step-up regulator, positive charge-pump regulator, and negative charge-pump regulator) is not above its respective fault-detection threshold, the MAX8784 activates an internal fault timer. If any condition or a combination of conditions indicates a continuous fault for the fault-timer duration (55ms typ), the MAX8784 sets the fault latch. The MAX8784 shuts down all the outputs except the reference and operational amplifiers after the fault latch is set. Toggle SHDN or cycle the input voltage to clear the fault latch and restart the IC. Thermal-Overload Protection The thermal-overload protection prevents excessive power dissipation from overheating the MAX8784. When the junction temperature exceeds TJ = +160°C (typ), a thermal sensor immediately sets its fault latch, which shuts down all the outputs. After the device cools down, input voltage has to be recycled to restart. The thermal-overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute junction temperature rating of TJ = +150°C. ______________________________________________________________________________________ 17 MAX8784 When CTL is logic high, Q1 turns on and Q2 and Q3 turn off, connecting GON to POUT. When CTL is logic low, Q1 turns off and Q2 and Q3 turn on, connecting GON to DRN. GON can be discharged through a resistor connected between DRN and GND. The switch control block is enabled when GDEL is charged to VREF. GDEL is charged by a 5µA current after the negative charge pump reaches regulation. The switch control block is disabled during fault mode and during shutdown. When the switch control block is disabled, GON is pulled to PGND with an internal 100kΩ resistor. MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs HVS Mode open-drain RSET pin is pulled to GND. In Figure 1, resistor R8 becomes parallel to R10, which reduces the feedback resistance during HVS operation. This special feature allows the customer to select a resistor that sets an appropriate HVS voltage according to the panel requirements. The negative charge pump operates normally. Figure 7 shows the typical application circuit in HVS mode. HVS mode is designed as a special operating mode for end-of-line panel testing. In HVS mode, higher than normal voltages are forced to the power-supply outputs to expose faults in the LCD panel. HVS pin is forced logic high to enable HVS mode. In HVS mode operation, FBP is ignored and the positive charge-pump regulates to a fixed-output voltage of 30V. To raise the step-up regulator output voltage in HVS operation, the 3μH AVDD 17V, 0.65A VIN = 5V 10μF 10μF 10μF LX VCC 1μF PGND 205kΩ POS1 NEG1 OUT1 VCOM AVDD FB COMP POS2 NEG2 10kΩ VCOM 20kΩ 100kΩ 330pF OUT2 POS3 82kΩ VCOM OUT3 10kΩ RSET RSET = LOW GDEL VIN HVS MAX8784 0.01μF ADEL 0.1μF REF 0.22μF 11kΩ CTL AGND SHDN FBN 102kΩ VGOFF -9V, 20mA FROM TCON FROM SYSTEM VGON 30V, 20mA GON DRN C4 1μF POUT VPOUT = 30V DRVN 1μF 10μF 432kΩ PGND SUP AVDD FBP C1N C1P C2N 0.1μF 0.1μF C2P FBP IGNORED AVDD 20kΩ 0.1μF Figure 7. HVS Mode Operation 18 ______________________________________________________________________________________ 10μF Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Step-Up Regulator Inductor Selection The inductance value, peak-current rating, and series resistance are factors to consider when selecting the inductor. These factors influence the converter’s efficiency, maximum output-load capability, transient response time, and output voltage ripple. Physical size and cost are also important factors to be considered. The maximum output current, input voltage, output voltage, and switching frequency determine the inductor value. Very high-inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and I2R losses in the entire power path. However, large inductor values also require more energy storage and more turns of wire, which increase physical size and can increase I2R losses in the inductor. Low-inductance values decrease the physical size but increase the current ripple and peak current. Finding the best inductor involves choosing the best compromise between circuit efficiency, inductor size, and cost. The equations used here include a constant LIR, which is the ratio of the inductor peak-to-peak ripple current to the average DC inductor at the full-load current. The best trade-off between inductor size and circuit efficiency for step-up regulators generally has an LIR between 0.3 to 0.5. However, depending on the AC characteristics of the inductor core material and ratio of inductor resistance to the other power-path resistances, the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. If the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. If extremely thin high-resistance inductors are used, as is common for LCD applications, the best LIR can increase to between 0.5 and 1.0. Once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficiency improvements in typical operating regions. Calculate the approximate inductor value using the typical input voltage (VIN), the maximum output current (IAVDD(MAX)), the expected efficiency (ηTYP) taken from an appropriate curve in the Typical Operating Characteristics, and an estimate of LIR based on the above discussion: Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage VIN(MIN) using conservation of energy and the expected efficiency at that operating point (ηMIN) taken from an appropriate curve in the Typical Operating Characteristics: IIN(DCMAX , )= IAVDD(MAX) × VAVDD VIN(MIN) × ηMIN Calculate the ripple current at that operating point and the peak current required for the inductor: ILI _ RIPPLE = VIN(MIN) × (VAVDD − VIN(MIN) ) LI × VAVDD × fSW IAVDD _ PEAK = IIN(DCMAX , )+ ILI _ RIPPLE 2 The inductor’s saturation current rating and the MAX8784’s LX current limit should exceed ILI_PEAK and the inductor’s DC current rating should exceed IIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1Ω series resistance. Considering the typical operating circuit in Figure 1, the maximum load current (IAVDD(MAX)), with charge-pump loads, is 820mA with a 14V output and a typical input voltage of 5V. Choosing an LIR of 0.35 and estimating efficiency of 85% at this operating point: 2 14V − 5V ⎛ 5V ⎞ ⎛ ⎞ ⎛ 0.85 ⎞ LI = ⎜ ⎟ ⎜ ⎟⎜ ⎟ ≈ 3.0μH ⎝ 14V ⎠ ⎝ 0.82A × 1.2MHz ⎠ ⎝ 0.35 ⎠ Using the circuit’s minimum input voltage (4.5V) and estimating efficiency of 85% at that operating point: IIN(DCMAX , )= 0.82A × 14V ≈ 3.00A 4.5V × 0.85 The ripple current and the peak current are: ILI _ RIPPLE = 4.5V × (14V − 4.5V ) 3.0μH × 14V × 1.2MHz ILI _ PEAK = 3.0A + ≈ 0.69A 0.69A ≈ 3.35A 2 2 ⎛ VIN ⎞ ⎛ VAVDD − VIN ⎞ ⎛ ηTYP ⎞ LI = ⎜ ⎜ ⎟ ⎟ ⎜ ⎝ VAVDD ⎠ ⎝ IAVDD(MAX) × fSW ⎟⎠ ⎝ LIR ⎠ ______________________________________________________________________________________ 19 MAX8784 Design Procedure MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Output-Capacitor Selection The total output-voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due to the capacitor’s equivalent series resistance (ESR): Loop Compensation Choose RCOMP (R9 in Figure 1) to set the high-frequency integrator gain for fast transient response. Choose CCOMP (C11 in Figure 1) to set the integrator zero to maintain loop stability. VAVDD _ RIPPLE = VAVDD _ RIPPLE(C) + VAVDD _ RIPPLE(ESR) For low-ESR output capacitors, use the following equations to obtain stable performance and good transient response: VAVDD _ RIPPLE(C) ≈ IAVDD ⎛ VAVDD − VIN ⎞ ⎜ ⎟ C AVDDT ⎝ VAVDD × fSW ⎠ and: VAVDD _ RIPPLE(ESR) ≈ IAVDD _ PEAK × RESR _ AVDD RCOMP ≈ 251× VIN × VAVDD × C AVDD LI × IAVDD(MAX) CCOMP ≈ VAVDD × C AVDD 10 × IAVDD(MAX) × RCOMP where IAVDD_PEAK is the peak inductor current (see the Inductor Selection section). For ceramic capacitors, the output-voltage ripple is typically dominated by VAVDD_RIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. To further optimize transient response, vary RCOMP in 20% steps and CCOMP in 50% steps while observing transient response waveforms. If additional noise rejection is desired, add a high-frequency pole by placing a 10pF to 47pF capacitor from COMP to GND. Input-Capacitor Selection The input capacitor reduces the current peaks drawn from the input supply and reduces noise injection into the IC. Two 10µF ceramic capacitors are used in the Typical Operating Circuit (Figure 1) because of the high source impedance seen in the typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. Typically, the input capacitance can be reduced below the values used in the Typical Operating Circuit. Charge-Pump Regulators Rectifier Diode The MAX8784’s high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 2A Schottky diode complements the internal MOSFET well. Output-Voltage Selection The output voltage of the step-up regulator can be adjusted by connecting a resistive voltage-divider from the output (AVDD) to AGND with the center tap connected to FB1 (see Figure 1). Select R10 in the 10kΩ to 50kΩ range. Calculate R11 with the following equation: ⎛V ⎞ R11 = R10 × ⎜ AVDD − 1⎟ ⎝ VFB ⎠ where V FB is the step-up regulator’s feedback set point. Place R10 and R11 close to the IC. 20 Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meet the output requirement. The number of negative charge-pump stages is given by: nNEG = −VGOFF + VDROPOUT VSUP − 2 × VD where nNEG is the number of negative charge-pump stages, VGOFF is the output of the negative chargepump regulator, V SUP is the supply voltage of the charge-pump regulators, VD is the forward voltage drop of the charge-pump diode, and V DROPOUT is the dropout margin for the regulator. Use VDROPOUT = 0.6V. The above equations are derived based on the assumption that the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VIN or another available supply. If the first-stage charge pump is powered from VIN, then the above equation becomes: nNEG = −VGOFF + VDROPOUT + VIN VSUP − 2 × VD The MAX8784’s positive charge-pump regulator is a fixed two-stage charge pump with built-in switches. ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs VCX > n × VSUP where n is the stage number in which the flying capacitor appears. For the positive charge pump, the pump capacitor’s voltage rating must exceed the following: Adjust the negative charge-pump regulator’s output voltage by connecting a resistive voltage-divider from VGOFF to REF with the center tap connected to FBN (Figure 1). Select R3 in the 20kΩ to 68kΩ range. Calculate R4 with the following equation: V −V R4 = R3 × FBN GOFF VREF − VFBN where VREF - VFBN is the negative charge-pump regulator’s feedback set point. Note that REF can only source up to 50µA. Using a resistor less than 20kΩ for R2 results in higher bias current than REF can supply. PCB Layout Grounding Careful PCB layout is important for proper operation. Use the following guidelines for good PCB layout: • Minimize the area of respective high-current loops by placing step-up regulator’s inductor, diode, and output capacitors near its input capacitors and its LX and PGND pins. For the step-up regulator, the high-current input loop goes from the positive terminal of the input capacitor to the inductor, to the IC’s LX pins, out of PGND, and to the input capacitor’s negative terminal. The high-current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (D1), to the positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor ground terminals. Connect these loop components with short, wide connections. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. • Create a power ground island (PGND) for the stepup regulator, consisting of the input and output capacitor grounds and the PGND pin. Connect all these together with short, wide traces or a small ground plane. Create an analog ground plane (AGND) consisting of the AGND pin, all the feedback-divider ground connections, the COMP, ADEL, and GDBL capacitor ground connections, and the device’s exposed backside pad. • Place all feedback voltage-divider resistors as close as possible to their respective feedback pins. The divider’s center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Care should be taken to avoid running any feedback trace near LX, DRVN, C1N, C1P, C2N, or C2P. VC6 > VSUP VC7 > 2 x VSUP Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output-voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: COUT _ CP ≥ ILOAD _ CP 2fOSCVRIPPLE _ CP where COUT_CP is the output capacitor of the charge pump, I LOAD _ CP is the load current of the charge pump, and VRIPPLE_CP is the peak-to-peak value of the output ripple. Output-Voltage Selection Adjust the positive charge-pump regulator’s output voltage by connecting a resistive voltage-divider from POUT to GND with the center tap connected to FBP (Figure 1). Select the lower resistor of divider R5 in the 10kΩ to 30kΩ range. Calculate upper resistor R6 with the following equation: ⎛V ⎞ R6 = R5 × ⎜ POUT − 1⎟ ⎝ VFBP ⎠ where VFBP is the positive charge-pump regulator’s feedback set point. ______________________________________________________________________________________ 21 MAX8784 Pump Capacitors Increasing the pump capacitor value (C4, C6, and C7) lowers the effective source impedance and increases the output-current capability. Increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. A 0.1µF ceramic capacitor works well in most low-current applications. For the negative charge pump, the flying capacitor’s voltage rating must exceed the following: FBN REF VCC AGND SHDN PGND N.C. PGND LX LX AGND 31 20 N.C. RSET 32 19 N.C. COMP 33 18 DRVN 17 HVS FB 34 16 CTL GON 35 MAX8784 DRN 36 15 GDEL 14 ADEL FBP 37 1 2 3 4 5 6 7 8 9 10 POS2 11 POS3 NEG2 12 OUT3 C2N 40 OUT2 13 N.C. C2P 39 OUT1 POUT 38 NEG1 Refer to the MAX8784 evaluation kit for an example of proper board layout. 30 29 28 27 26 25 24 23 22 21 SUP Minimize the size of the LX node while keeping it wide and short. Keep the LX and charge-pump nodes away from feedback nodes (FB, FBP, and FBN) and analog ground. Use DC traces as a shield if necessary. TOP VIEW POS1 • Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. Pin Configuration BGND • Place VCC pin and REF pin bypass capacitors as close as possible to the device. The ground connection of the V CC bypass capacitor should be connected directly to the AGND pin with a wide trace. C1P • C1N MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Chip Information TRANSISTOR COUNT: 11,424 PROCESS: BiCMOS 22 ______________________________________________________________________________________ Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs QFN THIN.EPS ______________________________________________________________________________________ 23 MAX8784 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX8784 Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.