Alaska® 88E1240 Technical Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Doc. No. MV-S103821-00, Rev. A May 4, 2011 Document Classification: Proprietary Information Marvell. Moving Forward Faster Alaska® 88E1240 Technical Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Advance Technical Publications: 1.10 For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2011. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S103821-00 Rev. A Page 2 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver O VERVIEW F EATURES Alaska® The Quad family of single-chip devices contains four independent Gigabit Ethernet transceivers on a single monolithic IC. Each transceiver performs all the physical layer functions for 100BASE-TX and 1000BASE-T full or half-duplex Ethernet on CAT 5 twisted pair cable, and 10BASET full or half-duplex Ethernet on CAT 3, 4, and 5 cable. The Alaska 88E1240 device supports the Serial Gigabit Media Independent Interface (SGMII) for direct connection to a MAC/Switch port. The 88E1240 device is fully compliant with the IEEE 802.3 standard. The 88E1240 device includes the PMD, PMA, and PCS sublayers. The 88E1240 device performs PAM5, 8B/10B, 4B/5B, MLT-3, NRZI, and Manchester encoding/decoding; digital clock/data recovery; stream cipher scrambling/descrambling; digital adaptive equalization for the receiver data path as well as digital filtering for pulse-shaping for the line transmitter; and AutoNegotiation and management functions. • • • • • • • • • • • • • • The 88E1240 device support Auto-MDI/MDIX at all • three speeds to enable easier installation and • reduced installation costs. • The 88E1240 device integrates MDI interface termi- • nation resistors into the PHY. This resistor integration facilitates board layout and reduces board cost by reducing the number of external components. The new Marvell® calibrated resistor scheme will achieve and exceed the accuracy requirements of the IEEE 802.3 return loss specifications. 10/100/1000BASE-T IEEE 802.3 compliant Highly integrated 4-port physical interface Supports Serial Gigabit Media Independent Interface (SGMII) Integrated MDI interface termination resistors Integrated Advanced Virtual Cable Tester® (VCT™) cable diagnostic feature Programmable current source LED drivers "Downshift" mode for two-pair cable installations User programmable individual/group MDC/MDIO support Innovative power management design to reduce onchip power by as much as 50% Fully integrated digital adaptive equalizers, echo cancellers, and crosstalk cancellers Automatic MDI/MDIX crossover for all 3 speeds of operation including 100BASE-TX and 10BASE-T Automatic polarity correction IEEE 802.3u compliant Auto-Negotiation Direct drive LED support Loopback mode for diagnostics Supports IEEE 1149.1 JTAG and 1149.6 AC JTAG Available in RoHS 6/6 compliant package Manufactured in a 15 x 15 mm 196-Pin TFBGA package The 88E1240 device uses advanced mixed-signal processing to perform equalization, echo and crosstalk cancellation, data recovery, and error correction at a gigabit per second data rate. The device achieves robust performance in noisy environments with very low power dissipation. The 88E1240 device is supported with an integrated Advanced Virtual Cable Tester® (VCT™) enabling fault detection and advanced cable performance monitoring. Copyright © 2011 Marvell May 4, 2011, Advanced Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 3 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver 10/100/1000 Mbps Ethernet MAC 10/100/1000 Mbps Ethernet MAC 88E1240 Device 10/100/1000 Mbps Ethernet MAC 10/100/1000 Mbps Ethernet MAC Integrated Passive Termination RJ45 M a g n e t i c s RJ45 RJ45 Media Types: - 10BASE-T - 100BASE-TX - 1000BASE-T RJ45 SGMII 88E1240 Device Application Doc. No. MV-S103821-00, Rev. A Page 4 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advanced Table of Contents SECTION 1. 1.1 SIGNAL DESCRIPTION ...................................................................6 Pin Description............................................................................................................... 6 1.1.1 Pin Type Definitions............................................................................................................ 6 1.2 88E1240 176-Pin TQFP Package................................................................................... 7 1.3 88E1240 196-Pin TFBGA Package ................................................................................ 8 SECTION 2. MECHANICAL DRAWINGS.............................................................26 2.1 88E1240 176-Pin TQFP Package Drawing.................................................................. 26 2.2 88E1240 196-Pin TFBGA Package Drawing............................................................... 28 Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 5 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Section 1. Signal Description The 88E1240 device is a 10/100/1000BASE-T Gigabit Ethernet transceiver. 1.1 Pin Description 1.1.1 Pin Type Definitions Pi n Ty pe De fin iti on H Input with hysteresis I/O Input and output I Input only O Output only PU Internal pull-up PD Internal pull-down D Open drain output Z Tri-state output mA DC sink capability Doc. No. MV-S103821-00, Rev. A Page 6 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 176-Pin TQFP Package 1.2 88E1240 176-Pin TQFP Package 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 MDC MDIO NC DVDD NC VDDOR DVDD NC NC NC DVDD NC INTn NC DVDD NC NC VDDOR DVDD NC NC DVDD TDO TDI TMS DVDD TCK TRSTn VDDOR DVDD XTAL2 XTAL1 VDDC TSTCLK TSTPT HSDACP HSDACN VSS VSS VSS VSS VSS AVDDH RSET Figure 1: 88E1240 176-Pin TQFP Package (Top View) 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 0 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VSS 88E1240 Top View P3_MDIP[0] P3_MDIN[0] AVDDH AVDDH P3_MDIP[1] P3_MDIN[1] P3_MDIP[2] P3_MDIN[2] AVDDH P3_MDIP[3] P3_MDIN[3] P2_MDIN[3] P2_MDIP[3] AVDDH P2_MDIN[2] P2_MDIP[2] P2_MDIN[1] P2_MDIP[1] AVDDH AVDDH P2_MDIN[0] P2_MDIP[0] P1_MDIP[0] P1_MDIN[0] AVDDH AVDDH P1_MDIP[1] P1_MDIN[1] P1_MDIP[2] P1_MDIN[2] AVDDH P1_MDIP[3] P1_MDIN[3] P0_MDIN[3] P0_MDIP[3] AVDDH P0_MDIN[2] P0_MDIP[2] P0_MDIN[1] P0_MDIP[1] AVDDH AVDDH P0_MDIN[0] P0_MDIP[0] RESETn P0_LED[0] P0_LED[1] DVDD P0_LED[2] P0_LED[3] DVDD VDDOL NC NC P1_LED[0] DVDD P1_LED[1] P1_LED[2] P1_LED[3] DVDD NC NC P2_LED[0] P2_LED[1] DVDD VDDOL P2_LED[2] P2_LED[3] DVDD NC NC P3_LED[0] P3_LED[1] P3_LED[2] P3_LED[3] NC NC VDDOL P0_CONFIG[0] P0_CONFIG[1] P1_CONFIG[0] P1_CONFIG[1] P2_CONFIG[0] P2_CONFIG[1] P3_CONFIG[0] P3_CONFIG[1] GCONFIG[0] GCONFIG[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DVDD DVDD V25_R P3_S_INP P3_S_INN AVDDH P3_S_CLKP P3_S_CLKN AVDDT P3_S_OUTP P3_S_OUTN P2_S_OUTN P2_S_OUTP AVDDT P2_S_CLKN P2_S_CLKP AVDDH P2_S_INN P2_S_INP TSTPTF DVDD DVDD DVDD DVDD VSS P1_S_INP P1_S_INN AVDDH P1_S_CLKP P1_S_CLKN AVDDT P1_S_OUTP P1_S_OUTN P0_S_OUTN P0_S_OUTP AVDDT P0_S_CLKN P0_S_CLKP AVDDH P0_S_INN P0_S_INP V25_L DVDD DVDD Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 7 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver 1.3 88E1240 196-Pin TFBGA Package Due to the large number of pins, the 196-pin TFBGA package is depicted graphically over two facing pages. 1 2 A NC P0_S_INN P0_S_CLKN P0_S_OUTN P1_S_OUTP P1_S_CLKP P1_S_INN A B NC P0_S_INP P0_S_CLKP P0_S_OUTP P1_S_OUTN P1_S_CLKN P1_S_INP B C P1_LED[0] P0_LED[1] P0_LED[0] AVDDH V25_L VSS AVDDH C D P1_LED[1] RESETn P0_LED[3] P0_LED[2] AVDDT AVDDT DVDD D E P1_LED[3] P1_LED[2] NC VDDOL VSS VSS VSS E F NC P2_LED[0] DVDD DVDD VSS VSS VSS F G P2_LED[1] P2_LED[2] DVDD DVDD VSS VSS VSS G H P2_LED[3] NC VDDOL VSS VSS VSS VSS H J NC P3_LED[1] P3_LED[0] VSS VSS VSS VSS J K P3_LED[2] P3_LED[3] VDDOL VSS VSS VSS K L NC AVDDH AVDDH AVDDH AVDDH L M NC GCONFIG[1] GCONFIG[0] P0_MDIP[3] P0_MDIN[3] P1_MDIN[0] M P0_MDIP[0] P0_MDIP[1] P0_MDIN[2] P1_MDIP[3] P1_MDIP[2] N P0_MDIN[0] P0_MDIN[1] P0_MDIP[2] P1_MDIN[3] P1_MDIN[2] P 3 4 5 6 7 N P 3 4 P0_ CONFIG[0] P2_ P1_ CONFIG[0] CONFIG[0] P3_ CONFIG[1] P0_ P3_ CONFIG[1] CONFIG[0] P1_ P2_ CONFIG[1] CONFIG[1] 1 2 5 6 7 (Top View) Figure 2: Pin A1 Location Pin A1 location 88E1240-BAM Doc. No. MV-S103821-00, Rev. A Page 8 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package 8 9 10 11 12 13 14 A P2_S_INP P2_S_CLKP P2_S_OUTP P3_S_OUTN P3_S_CLKN P3_S_INN NC A B P2_S_INN P2_S_CLKN P2_S_OUTN P3_S_OUTP P3_S_CLKP P3_S_INP NC B C TSTPTF AVDDH V25_R AVDDH NC NC NC C D DVDD AVDDT AVDDT DVDD MDIO INTn NC D E VSS VSS VSS VDDOR MDC NC NC E F VSS VSS VSS DVDD DVDD NC NC F G VSS VSS VSS DVDD DVDD TDO NC G H VSS VSS VSS VDDOR VDDOR TDI TMS H J VSS VSS VSS VSS TCK TRSTn XTAL2 J K VSS VSS VSS VSS VDDC TSTPT XTAL1 K L AVDDH AVDDH AVDDH AVDDH AVDDH RSET TSTCLK L M P1_MDIP[0] P2_MDIP[3] P2_MDIN[3] P3_MDIN[1] P3_MDIP[1] HSDACN HSDACP M N P1_MDIP[1] P2_MDIN[0] P2_MDIN[1] P2_MDIN[2] P3_MDIP[3] P3_MDIP[2] P3_MDIP[0] N P P1_MDIN[1] P2_MDIP[0] P2_MDIP[1] P2_MDIP[2] P3_MDIN[3] P3_MDIN[2] P3_MDIN[0] P 8 9 10 11 12 13 14 (Top View) Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 9 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Table 1: Media Dependent Interface Port 0 17 6-TQFP Pin # 19 6-TF BGA Pin # Pin Name Pin Type De scr ip tio n 45 46 N3 P3 P0_MDIP[0] P0_MDIN[0] I/O Media Dependent Interface[0]. In 1000BASE-T mode in MDI configuration, MDIP/ N[0] correspond to BI_DA±. In MDIX configuration, MDIP/N[0] correspond to BI_DB±. In 100BASE-TX and 10BASE-T modes in MDI configuration, MDIP/N[0] are used for the transmit pair. In MDIX configuration, MDIP/N[0] are used for the receive pair. NOTE: Unused MDI pins must be left floating. The 88E1240 device contains an internal 100 ohm resistor between the MDIP/N[0] pins. 49 50 N4 P4 P0_MDIP[1] P0_MDIN[1] I/O Media Dependent Interface[1]. In 1000BASE-T mode in MDI configuration, MDIP/ N[1] correspond to BI_DB±. In MDIX configuration, MDIP/N[1] correspond to BI_DA±. In 100BASE-TX and 10BASE-T modes in MDI configuration, MDIP/N[1] are used for the receive pair. In MDIX configuration, MDIP/N[1] are used for the transmit pair. NOTE: Unused MDI pins must be left floating. The 88E1240 device contains an internal 100 ohm resistor between the MDIP/N[1] pins. 51 52 P5 N5 P0_MDIP[2] P0_MDIN[2] I/O Media Dependent Interface[2]. In 1000BASE-T mode in MDI configuration, MDIP/ N[2] correspond to BI_DC±. In MDIX configuration, MDIP/N[2] correspond to BI_DD±. In 100BASE-TX and 10BASE-T modes, MDIP/ N[2] are not used. NOTE: Unused MDI pins must be left floating. The 88E1240 device contains an internal 100 ohm resistor between the MDIP/N[2] pins. 54 55 M5 M6 P0_MDIP[3] P0_MDIN[3] I/O Media Dependent Interface[3]. In 1000BASE-T mode in MDI configuration, MDIP/ N[3] correspond to BI_DD±. In MDIX configuration, MDIP/N[3] correspond to BI_DC±. In 100BASE-TX and 10BASE-T modes, MDIP/ N[3] are not used. NOTE: Unused MDI pins must be left floating. The 88E1240 device contains an internal 100 ohm resistor between the MDIP/N[3] pins. Doc. No. MV-S103821-00, Rev. A Page 10 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package Table 2: Media Dependent Interface Port 1 1 76-TQF P Pin # 196 -TF BGA Pin # Pin Name Pin Typ e Des cription 66 65 M8 M7 P1_MDIP[0] P1_MDIN[0] I/O Media Dependent Interface[0] for Port 1. Refer to P0_MDI[0]P/N. 62 61 N8 P8 P1_MDIP[1] P1_MDIN[1] I/O Media Dependent Interface[1] for Port 1. Refer to P0_MDI[1]P/N. 60 59 N7 P7 P1_MDIP[2] P1_MDIN[2] I/O Media Dependent Interface[2] for Port 1. Refer to P0_MDI[2]P/N. 57 56 N6 P6 P1_MDIP[3] P1_MDIN[3] I/O Media Dependent Interface[3] for Port 1. Refer to P0_MDI[3]P/N. Table 3: Media Dependent Interface Port 2 176 -TQFP Pin # 1 96-TFBGA Pin # Pin Name Pin Typ e Des cription 67 68 P9 N9 P2_MDIP[0] P2_MDIN[0] I/O Media Dependent Interface[0] for Port 2. Refer to P0_MDI[0]P/N. 71 72 P10 N10 P2_MDIP[1] P2_MDIN[1] I/O Media Dependent Interface[1] for Port 2. Refer to P0_MDI[1]P/N. 73 74 P11 N11 P2_MDIP[2] P2_MDIN[2] I/O Media Dependent Interface[2] for Port 2. Refer to P0_MDI[2]P/N. 76 77 M9 M10 P2_MDIP[3] P2_MDIN[3] I/O Media Dependent Interface[3] for Port 2. Refer to P0_MDI[3]P/N. Table 4: Media Dependent Interface Port 3 176 -TQFP Pin # 1 96-TFBGA Pin # Pin Name Pin Typ e Des cription 88 87 N14 P14 P3_MDIP[0] P3_MDIN[0] I/O Media Dependent Interface[0] for Port 3. Refer to P0_MDI[0]P/N. 84 83 M12 M11 P3_MDIP[1] P3_MDIN[1] I/O Media Dependent Interface[1] for Port 3. Refer to P0_MDI[1]P/N. 82 81 N13 P13 P3_MDIP[2] P3_MDIN[2] I/O Media Dependent Interface[2] for Port 3. Refer to P0_MDI[2]P/N. 79 78 N12 P12 P3_MDIP[3] P3_MDIN[3] I/O Media Dependent Interface[3] for Port 3. Refer to P0_MDI[3]P/N. Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 11 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Table 5: SGMII Interface Port 0 176-T QF P Pin # 1 96-TFBGA Pin # Pin Name Pin Type Des cription 173 172 B2 A2 P0_S_INP P0_S_INN I SGMII Transmit Data. 1.25 GBaud input - Positive and Negative. 170 169 B3 A3 P0_S_CLKP P0_S_CLKN O SGMII 625 MHz Receive Clock output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0. The P0_S_CLKP/N pins should be left floating if not used. 167 166 B4 A4 P0_S_OUTP P0_S_OUTN O SGMII Receive Data. 1.25 GBaud output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0. Table 6: SGMII Interface Port 1 176-T QF P Pin # 1 96-TFBGA Pin # Pin Name Pin Type Des cription 158 159 B7 A7 P1_S_INP P1_S_INN I SGMII Transmit Data. 1.25 GBaud input - Positive and Negative. 161 162 A6 B6 P1_S_CLKP P1_S_CLKN O SGMII 625 MHz Receive Clock output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0 The P1_S_CLKP/N pins should be left floating if not used. 164 165 A5 B5 P1_S_OUTP P1_S_OUTN O SGMII Receive Data. 1.25 GBaud output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0. Doc. No. MV-S103821-00, Rev. A Page 12 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package Table 7: SGMII Interface Port 2 17 6-TQFP Pin # 196-T FB GA Pin # Pin Name Pi n Typ e De scrip tio n 151 150 A8 B8 P2_S_INP P2_S_INN I SGMII Transmit Data. 1.25 GBaud input - Positive and Negative. 148 147 A9 B9 P2_S_CLKP P2_S_CLKN O SGMII 625 MHz Receive Clock output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0 The P2_S_CLKP/N pins should be left floating if not used. 145 144 A10 B10 P2_S_OUTP P2_S_OUTN O SGMII Receive Data. 1.25 GBaud output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0. Table 8: SGMII Interface Port 3 17 6-TQFP Pin # 196-T FB GA Pin # Pin Name Pi n Typ e De scrip tio n 136 137 B13 A13 P3_S_INP P3_S_INN I SGMII Transmit Data. 1.25 GBaud input - Positive and Negative. 139 140 B12 A12 P3_S_CLKP P3_S_CLKN O SGMII 625 MHz Receive Clock output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0 The P3_S_CLKP/N pins should be left floating if not used. 142 143 B11 A11 P3_S_OUTP P3_S_OUTN O SGMII Receive Data. 1.25 GBaud output - Positive and Negative. Output amplitude can be adjusted via register 26_2.2:0. Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 13 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Table 9: Management Interface/Control 1 76- T QF P Pin # 19 6-TF BGA Pin # Pin Name Pin Ty pe Desc rip t ion 132 E12 MDC I Management Clock pin. MDC is the management data clock reference for the serial management interface. A continuous clock stream is not expected. The maximum frequency supported is 8.3 MHz. 131 D12 MDIO I/O Management Data pin. MDIO is the management data. MDIO transfers management data in and out of the device synchronously to MDC. This pin requires a pull-up resistor in a range from 1.5 kohm to 10 kohm. 120 D13 INTn OD Interrupt pin. Table 10: JTAG 1 76- T QF P Pin # 19 6-TF BGA Pin # Pin Name Pin Ty pe Desc rip t ion 109 H13 TDI I, PU Boundary scan test data input. TDI contains an internal 150 kohm pull-up resistor. 108 H14 TMS I, PU Boundary scan test mode select input. TMS contains an internal 150 kohm pull-up resistor. 106 J12 TCK I, PU Boundary scan test clock input. TCK contains an internal 150 kohm pull-up resistor. 105 J13 TRSTn I, PU Boundary scan test reset input. Active low. TRSTn contains an internal 150 kohm pull-up resistor. For normal operation, TRSTn should be pulled low with a 4.7 kohm pull-down resistor. 110 G13 TDO O Boundary scan test data output. Doc. No. MV-S103821-00, Rev. A Page 14 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package Table 11: LED/Configuration 1 76-TQF P Pin # 196 -TF BGA Pin # Pin Name Pin Typ e D escr ip tio n 6 5 3 2 D3 D4 C2 C3 P0_LED[3] P0_LED[2] P0_LED[1] P0_LED[0] O Parallel LED Output port 0 15 14 13 11 E1 E2 D1 C1 P1_LED[3] P1_LED[2] P1_LED[1] P1_LED[0] O Parallel LED Output port 1 24 23 20 19 H1 G2 G1 F2 P2_LED[3] P2_LED[2] P2_LED[1] P2_LED[0] O Parallel LED Output port 2 31 30 29 28 K2 K1 J2 J3 P3_LED[3] P3_LED[2] P3_LED[1] P3_LED[0] O Parallel LED Output port 3 36 35 N1 K3 P0_CONFIG[1] P0_CONFIG[0] I Hardware configuration Port 0 38 37 P1 L3 P1_CONFIG[1] P1_CONFIG[0] I Hardware configuration Port 1 40 39 P2 L2 P2_CONFIG[1] P2_CONFIG[0] I Hardware configuration Port 2 42 41 M2 N2 P3_CONFIG[1] P3_CONFIG[0] I Hardware configuration Port 3 44 43 M3 M4 GCONFIG[1] GCONFIG[0] I Global hardware configuration 174 C5 V25_L I VDDOL voltage control. Tie to VSS = VDDOL operating at 2.5V/3.3V Floating = VDDOL operating at 1.8V 135 C10 V25_R I VDDOR voltage control. Tie to VSS = VDDOR operating at 2.5V/3.3V Floating = VDDOR operating at 1.8V Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 15 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Table 12: Clock/Reset 17 6-TQFP Pin # 196 -T FB GA Pin # Pin Name Pi n Typ e De scrip tio n 101 K14 XTAL1 I 25 MHz Clock Input 25 MHz ± 50 ppm tolerance crystal reference or oscillator input. The XTAL1 input voltage should not exceed 1.8V+5%. 102 J14 XTAL2 O 25 MHz Crystal Output. 25 MHz ± 50 ppm tolerance crystal reference. When the XTAL2 pin is not connected, it should be left floating. 99 L14 TSTCLK I Test Clock. Must be tied to XTAL1. 1 D2 RESETn I Hardware reset. XTAL1 must be active for a minimum of 10 clock cycles before the rising edge of RESETn. RESETn must be in inactive state for normal operation. 1 = Normal operation 0 = Reset Table 13: Test 17 6-TQFP Pin # 196 -T FB GA Pin # Pin Name Pi n Typ e De scrip tio n 97 96 M14 M13 HSDACP HSDACN O AC Test Point. Positive and Negative. These pins are also used to bring out a differential TX_TCLK. These pins can be connected to VSS through a 50 ohms termination resistor for IEEE testing and debug purposes. These pins maybe left floating if debug and IEEE testing are not of importance. 98 K13 TSTPT O DC Test Point. The TSTPT pin should be left floating if not used. 152 C8 TSTPTF O DC test point. The TSTPTF pin should be left floating if not used. Table 14: Reference 17 6-TQFP Pin # 196 -T FB GA Pin # Pin Name Pi n Typ e De scrip tio n 89 L13 RSET I Resistor Reference External 5.0 kohm 1% resistor connected to ground. Doc. No. MV-S103821-00, Rev. A Page 16 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package Table 15: Power & Ground 176 -TQFP Pin # 1 96-TFBGA Pin # Pin Name Pin Typ e Des cription 4 7 12 16 21 25 103 107 111 114 118 122 126 129 133 134 153 154 155 156 175 176 D7 D8 D11 F3 F4 F11 F12 G3 G4 G11 G12 DVDD Power 1.0V or 1.2V Digital Supply 47 48 53 58 63 64 69 70 75 80 85 86 90 138 149 160 171 C4 C7 C9 C11 L4 L5 L6 L7 L8 L9 L10 L11 L12 AVDDH Power 1.8V Analog Supply. 100 K12 VDDC Power 1.8V XTAL Supply. The maximum input voltage is 1.8V +5%. 141 146 163 168 D5 D6 D9 D10 AVDDT Power SGMII Output Supply 8 22 34 E4 H3 K4 VDDOL Power 1.8V, 2.5V, or 3.3V I/O Supply1. 104 115 127 E11 H11 H12 VDDOR Power 1.8V, 2.5V, or 3.3V I/O Supply2. Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 17 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Table 15: Power & Ground (Continued) 1 76- T QF P Pin # 19 6-TF BGA Pin # Pin Name Pin Ty pe Desc rip t ion EPAD -- VSS Ground Ground to device. The 176-TQFP package contains an exposed die pad (E-PAD) at its base. The EPAD must be soldered to VSS. The location and dimensions of the EPAD can be found in Section 2.1 and Table 19, respectively. 91 92 93 94 95 157 C6 E5 E6 E7 E8 E9 E10 F5 F6 F7 F8 F9 F10 G5 G6 G7 G8 G9 G10 H4 H5 H6 H7 H8 H9 H10 J4 J5 J6 J7 J8 J9 J10 J11 K5 K6 K7 K8 K9 K10 K11 VSS Ground Ground 1. VDDOL supplies digital I/O pins for RESETn, LED, CONFIG, and GCONFIG. 2. VDDOR supplies digital I/O pins for MDC, MDIO, INTn, TDO, TDI, TMS, TCK, and TRST. Doc. No. MV-S103821-00, Rev. A Page 18 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 88E1240 196-Pin TFBGA Package Table 16: No Connect 1 76-TQF P Pin # 196 -TF BGA Pin # Pin Name Pin Typ e D escr ip tio n 9 10 17 18 26 27 32 33 112 113 116 117 119 121 123 124 125 128 130 A1 B1 F1 J1 L1 M1 H2 E3 C12 C13 E13 A14 B14 C14 D14 E14 F13 F14 G14 NC NC These pins are not bonded to the die. Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 19 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver 1.4 88E1240 176-TQFP Pin Assignment List—by Signal Name Table 17: Package Pin List—Alphabetical by Signal Name Pin Number Pin Name 47 AVDDH 48 AVDDH 53 AVDDH 58 AVDDH 63 AVDDH 64 AVDDH 69 AVDDH 70 AVDDH 75 AVDDH 80 AVDDH 85 AVDDH 86 AVDDH 90 AVDDH 138 AVDDH 149 AVDDH 160 AVDDH 171 AVDDH 141 AVDDT 146 AVDDT 163 AVDDT 168 AVDDT 4 DVDD 7 DVDD 12 DVDD 16 DVDD 21 DVDD 25 DVDD 103 DVDD 107 DVDD 111 DVDD 114 DVDD 118 DVDD Pin Number Pin Name 122 DVDD 126 DVDD 129 DVDD 133 DVDD 134 DVDD 153 DVDD 154 DVDD 155 DVDD 156 DVDD 175 DVDD 176 DVDD 43 GCONFIG[0] 44 GCONFIG[1] 96 HSDACN 97 HSDACP 120 INTn 132 MDC 131 MDIO 9 NC 10 NC 17 NC 18 NC 26 NC 27 NC 32 NC 33 NC 112 NC 113 NC 116 NC 117 NC 119 NC 121 NC Doc. No. MV-S103821-00 Rev. A Page 20 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description Pin Number Pin Name Pin Number Pin Name 123 NC 66 P1_MDIP[0] 124 NC 62 P1_MDIP[1] 125 NC 60 P1_MDIP[2] 128 NC 57 P1_MDIP[3] 130 NC 162 P1_S_CLKN 35 P0_CONFIG[0] 161 P1_S_CLKP 36 P0_CONFIG[1] 159 P1_S_INN 2 P0_LED[0] 158 P1_S_INP 3 P0_LED[1] 165 P1_S_OUTN 5 P0_LED[2] 164 P1_S_OUTP 6 P0_LED[3] 39 P2_CONFIG[0] 46 P0_MDIN[0] 40 P2_CONFIG[1] 50 P0_MDIN[1] 19 P2_LED[0] 52 P0_MDIN[2] 20 P2_LED[1] 55 P0_MDIN[3] 23 P2_LED[2] 45 P0_MDIP[0] 24 P2_LED[3] 49 P0_MDIP[1] 68 P2_MDIN[0] 51 P0_MDIP[2] 72 P2_MDIN[1] 54 P0_MDIP[3] 74 P2_MDIN[2] 169 P0_S_CLKN 77 P2_MDIN[3] 170 P0_S_CLKP 67 P2_MDIP[0] 172 P0_S_INN 71 P2_MDIP[1] 173 P0_S_INP 73 P2_MDIP[2] 166 P0_S_OUTN 76 P2_MDIP[3] 167 P0_S_OUTP 147 P2_S_CLKN 37 P1_CONFIG[0] 148 P2_S_CLKP 38 P1_CONFIG[1] 150 P2_S_INN 11 P1_LED[0] 151 P2_S_INP 13 P1_LED[1] 144 P2_S_OUTN 14 P1_LED[2] 145 P2_S_OUTP 15 P1_LED[3] 41 P3_CONFIG[0] 65 P1_MDIN[0] 42 P3_CONFIG[1] 61 P1_MDIN[1] 28 P3_LED[0] 59 P1_MDIN[2] 29 P3_LED[1] 56 P1_MDIN[3] 30 P3_LED[2] Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00 Rev. A Document Classification: Proprietary Information Page 21 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Pin Number Pin Name Pin Number Pin Name 31 P3_LED[3] 92 VSS 87 P3_MDIN[0] 93 VSS 83 P3_MDIN[1] 94 VSS 81 P3_MDIN[2] 95 VSS 78 P3_MDIN[3] 157 VSS 88 P3_MDIP[0] 101 XTAL1 84 P3_MDIP[1] 102 XTAL2 82 P3_MDIP[2] 79 P3_MDIP[3] 140 P3_S_CLKN 139 P3_S_CLKP 137 P3_S_INN 136 P3_S_INP 143 P3_S_OUTN 142 P3_S_OUTP 1 RESETn 89 RSET 106 TCK 109 TDI 110 TDO 108 TMS 105 TRSTn 99 TSTCLK 98 TSTPT 152 TSTPTF 174 V25_L 135 V25_R 100 VDDC 8 VDDOL 22 VDDOL 34 VDDOL 104 VDDOR 115 VDDOR 127 VDDOR 91 VSS Doc. No. MV-S103821-00 Rev. A Page 22 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description 1.5 88E1240 196-TFBGA Pin Assignment List—by Signal Name Table 18: Package Pin List—Alphabetical by Signal Name Pin Number Pin Name C11 AVDDH C4 AVDDH C7 AVDDH C9 AVDDH L10 AVDDH L11 AVDDH L12 AVDDH L4 AVDDH L5 AVDDH L6 AVDDH L7 AVDDH L8 AVDDH L9 AVDDH D10 AVDDT D5 AVDDT D6 AVDDT D9 AVDDT C5 C25_L D11 DVDD D7 DVDD D8 DVDD F11 DVDD F12 DVDD F3 DVDD F4 DVDD G11 DVDD G12 DVDD G3 DVDD G4 DVDD M4 GCONFIG[0] M3 GCONFIG[1] M13 HSDACN Pin Number Pin Name M14 HSDACP D13 INTn E12 MDC D12 MDIO A1 NC A14 NC B1 NC B14 NC C12 NC C13 NC C14 NC D14 NC E13 NC E14 NC E3 NC F1 NC F13 NC F14 NC G14 NC H2 NC J1 NC L1 NC M1 NC K3 P0_CONFIG[0] N1 P0_CONFIG[1] C3 P0_LED[0] C2 P0_LED[1] D4 P0_LED[2] D3 P0_LED[3] P3 P0_MDIN[0] P4 P0_MDIN[1] N5 P0_MDIN[2] Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00 Rev. A Document Classification: Proprietary Information Page 23 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Pin Number Pin Name Pin Number Pin Name M6 P0_MDIN[3] G2 P2_LED[2] N3 P0_MDIP[0] H1 P2_LED[3] N4 P0_MDIP[1] N9 P2_MDIN[0] P5 P0_MDIP[2] N10 P2_MDIN[1] M5 P0_MDIP[3] N11 P2_MDIN[2] A3 P0_S_CLKN M10 P2_MDIN[3] B3 P0_S_CLKP P9 P2_MDIP[0] A2 P0_S_INN P10 P2_MDIP[1] B2 P0_S_INP P11 P2_MDIP[2] A4 P0_S_OUTN M9 P2_MDIP[3] B4 P0_S_OUTP B9 P2_S_CLKN L3 P1_CONFIG[0] A9 P2_S_CLKP P1 P1_CONFIG[1] B8 P2_S_INN C1 P1_LED[0] A8 P2_S_INP D1 P1_LED[1] B10 P2_S_OUTN E2 P1_LED[2] A10 P2_S_OUTP E1 P1_LED[3] N2 P3_CONFIG[0] M7 P1_MDIN[0] M2 P3_CONFIG[1] P8 P1_MDIN[1] J3 P3_LED[0] P7 P1_MDIN[2] J2 P3_LED[1] P6 P1_MDIN[3] K1 P3_LED[2] M8 P1_MDIP[0] K2 P3_LED[3] N8 P1_MDIP[1] P14 P3_MDIN[0] N7 P1_MDIP[2] M11 P3_MDIN[1] N6 P1_MDIP[3] P13 P3_MDIN[2] B6 P1_S_CLKN P12 P3_MDIN[3] A6 P1_S_CLKP N14 P3_MDIP[0] A7 P1_S_INN M12 P3_MDIP[1] B7 P1_S_INP N13 P3_MDIP[2] B5 P1_S_OUTN N12 P3_MDIP[3] A5 P1_S_OUTP A12 P3_S_CLKN L2 P2_CONFIG[0] B12 P3_S_CLKP P2 P2_CONFIG[1] A13 P3_S_INN F2 P2_LED[0] B13 P3_S_INP G1 P2_LED[1] A11 P3_S_OUTN Doc. No. MV-S103821-00 Rev. A Page 24 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Signal Description Pin Number Pin Name Pin Number Pin Name B11 P3_S_OUTP G10 VSS D2 RESETn G5 VSS L13 RSET G6 VSS J12 TCK G7 VSS H13 TDI G8 VSS G13 TDO G9 VSS H14 TMS H10 VSS J13 TRSTn H4 VSS L14 TSTCLK H5 VSS K13 TSTPT H6 VSS C8 TSTPTF H7 VSS C10 V25_R H8 VSS K12 VDDC H9 VSS E4 VDDOL J10 VSS H3 VDDOL J11 VSS K4 VDDOL J4 VSS E11 VDDOR J5 VSS H11 VDDOR J6 VSS H12 VDDOR J7 VSS C6 VSS J8 VSS E10 VSS J9 VSS E5 VSS K10 VSS E6 VSS K11 VSS E7 VSS K5 VSS E8 VSS K6 VSS E9 VSS K7 VSS F10 VSS K8 VSS F5 VSS K9 VSS F6 VSS K14 XTAL1 F7 VSS J14 XTAL2 F8 VSS F9 VSS Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00 Rev. A Document Classification: Proprietary Information Page 25 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver Section 2. Mechanical Drawings 2.1 88E1240 176-Pin TQFP Package Drawing D 1 D 2 1 4 89 132 133 O2 88 O1 D2 R1 B E2 A E1 E 2 1 R2 GAUGE PLANE .25 A O B S L O3 L1 45 176 PIN 1 IDENTIFIER 1 44 e SECTION A-A 4X 4X WITH PLATING 5 A A2 SEATING PLANE A1 6 b b 5 3 c c1 BASE METAL b1 5 5 SECTION B-B NOTE : 1. TO BE DETERMINED AT SEATING PLANE . 2. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 4. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 5. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. 6. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. 7. CONTROLLING DIMENSION : MILLIMETER. Doc. No. MV-S103821-00, Rev. A Page 26 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Mechanical Drawings 88E1240 176-Pin TQFP Package Drawing Table 19: 176-Pin TQFP Package Dimensions (mm) Symbol A A1 A2 b b1 c c1 Dimension in mm Nom Min 1.00 1.10 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.13 0.18 0.23 0.13 0.16 0.19 0.20 0.09 0.16 0.09 D D1 E E1 e L L1 R1 R2 S O O1 O2 O3 aaa bbb ccc ddd Max 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.40 BSC 0.45 0.60 0.75 1.00 REF 0.08 0.08 0.20 0.20 0° 3.5° 7° 11° 12° 13° 11° 12° 13° 0° 0.20 0.20 0.08 0.07 Symbol Dimension in mm D2 4.01 BSC E2 6.86 BSC Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 27 Alaska® 88E1240 Product Brief Integrated 10/100/1000 Gigabit Ethernet Transceiver 2.2 88E1240 196-Pin TFBGA Package Drawing D PIN #1 A1 E A c A2 CAVITY SOLDER BALL SEATING PLANE (NOTE 2) DETAIL : A "A" D1 e P N M Øb E1 A (NOTE 3) B L K J H G 1 F E D 2 DETAIL : B C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 "B" Doc. No. MV-S103821-00, Rev. A Page 28 Copyright © 2011 Marvell Document Classification: Proprietary Information May 4, 2011, Advance Mechanical Drawings 88E1240 196-Pin TFBGA Package Drawing Table 20: 196-Pin TFBGA Package Dimensions (mm) Symbol A A1 Dimension in mm MAX MIN NOM ----1.50 0.30 --- 0.40 0.50 0.89 0.36 ----- 15.00 15.10 A2 c --- D 14.90 E 14.90 15.00 15.10 D1 --- 13.00 --- E1 --- 13.00 --- e b --0.40 1.00 0.50 --0.60 aaa 0.20 bbb ccc 0.25 ddd eee fff MD/ME 0.35 0.12 0.25 0.10 14/14 NOTE : 1. CONTROLLING DIMENSION : MILLIMETER. 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. Copyright © 2011 Marvell May 4, 2011, Advance Doc. No. MV-S103821-00, Rev. A Document Classification: Proprietary Information Page 29 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.988.8279 www.marvell.com Marvell. Moving Forward Faster