DS32EV100
Programmable Single Equalizer
General Description
Features
The DS32EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channel. The
DS32EV100 is optimized for operation up to 3.2 Gbps for both
cables and FR4 traces. The equalizer channel has eight levels of input equalization that can be programmed by three
control pins.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs, and is available
in a 3 mm x 4 mm 14-pin leadless LLP package. Power is
supplied from either a 2.5V or 3.3V supply.
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Equalizes up to 14 dB loss at 3.2 Gbps
8 levels of programmable equalization
Operates up to 3.2 Gbps with 40” FR4 traces
0.12 UI residual deterministic jitter at 3.2 Gbps with 40”
FR4 traces
Single 2.5V or 3.3V power supply
Supports AC or DC-Coupling with wide input commonmode
Low power consumption: 100 mW Typ at 2.5V
Small 3 mm x 4 mm 14-pin LLP package
>8 kV HBM ESD
-40 to 85°C operating temperature range
Simplified Application Diagram
20206501
© 2007 National Semiconductor Corporation
202065
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DS32EV100 Programmable Single Equalizer
November 5, 2007
DS32EV100
Pin Diagram
20206503
Top View
3mm x 4mm 14-Pin LLP Package
Order number DS32EV100
See NS Package Number SQA14A
Pin Descriptions
Pin Name
I/O,
Type
Pin Number
Description
HIGH SPEED DIFFERENTIAL I/O
IN−
IN+
4
3
I, CML
OUT−
OUT+
11
12
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT+ to VDD and OUT− to VDD.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating
resistor is connected between IN+ and IN−.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
14
7
8
I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength for EQ channel 1. BST_2 is internally
pulled high. BST_1 and BST_0 are internally pulled low.
POWER
VDD
5
Power
VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
GND
Exposed
Pad
2, 6, 9, 10,
13
Power
Ground reference. GND should be tied to a solid ground plane through a low impedance path.
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
OTHER
RSVD
1
Reserved. Leave no Connect.
Note: I = Input, O = Output
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2
HBM, 1.5 kΩ, 100 pF
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
CMOS Input Voltage
CMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temperature
Soldering, 4 sec
>8 kV
EIAJ, 0Ω, 200 pF
>250V
Thermal Resistance, θJA,
No Airflow
−0.5V to +4.0V
−0.5V to +4.0V
–0.5V to +4.0V
–0.5V to +4.0V
+150°C
−65°C to +150°C
40 °C/W
Recommended Operating
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
3.0
3.3
3.6
V
−40
25
+85
°C
Supply Voltage
VDD2.5 to GND
+260°C
VDD3.3 to GND
Ambient Temperature
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2,3)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
Units
POWER
P
N
Power Supply
Consumption
VDD2.5
100
150
mW
VDD3.3
140
200
mW
Supply Noise
Tolerance (Note 3)
50 Hz – 100 Hz
100 Hz – 10 MHz
10 MHz – 1.6GHz
100
40
10
mVP-P
mVP-P
mVP-P
LVTTL DC SPECIFICATIONS
VIH
High Level Input
Voltage
VDD2.5
1.6
VDD
V
VDD3.3
2.0
VDD
V
−0.3
0.8
V
VIL
Low Level Input
Voltage
VOH
High Level Output
Voltage
IOH = –3mA, VDD2.5
2.0
V
IOH = –3mA, VDD3.3
2.4
V
VOL
Low Level Output
Voltage
IOL = 3mA
IIN
Input Current
VIN = VDD
IIN-P
Input Leakage Current VIN = VDD, with internal pull-down resistors
with Internal PullVIN = GND, with internal pull-up resistors
Down/Up Resistors
+1.8
VIN = GND
−15
0.4
V
+15
µA
0
µA
+95
µA
–20
µA
CML RECEIVER INPUTS (IN+, IN−)
VINTRE
Input Threshold
Voltage
Differential measurement at point B
(FIgure 1)
VIN
Input Voltage Swing
AC-Coupled or DC-Coupled Requirement
(Figure 1)
VDDTX
Supply Voltage of
Transmitter to EQ
DC-Coupled Requirement
VICMDC
Input Common-Mode DC-Coupled Requirement
Voltage
Differential measurement at point A
(Figure 1)
(Note 7)
RLI
Differential Input
Return Loss
100 MHz – 1.6 GHz, with fixture’s effect deembedded
3
mVP-P
120
400
1600
mVP-P
1.6
VDD
V
VDDTX-0.8
VDDTX-0.2
V
10
dB
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DS32EV100
ESD Rating
Absolute Maximum Ratings (Note 1)
DS32EV100
Symbol
RIN
Parameter
Input Resistance
Conditions
Differential Across IN+ and IN-
Min
Typ
(Note 2)
Max
Units
85
100
115
Ω
550
725
mVP-P
VDD-0.2
VDD-0.1
V
60
ps
58
Ω
CML OUTPUTS (OUT+, OUT−)
VO
VOCM
tR, tF
Output Voltage Swing Differential measurement with OUT+ and OUTterminated by 50Ω to GND, AC-Coupled
(Figure 2)
Output CommonMode Voltage
Single-ended measurement DC-Coupled with
50Ω terminations
(Note 7)
Transition Time
20% to 80% of differential output voltage,
measured within 1” from output pins.
(Figure 2)
(Note 7)
20
42
RO
Output Resistance
Single-ended to VDD
RLO
Differential Output
Return Loss
100 MHz – 1.6 GHz, with fixture’s effect deembedded. IN+ = static high.
tPLHD
Differential Low to
High Propagation
Delay
Propagation delay measurement at 50% VO
between input to output, 100 Mbps
(Figure 3)
(Note 7)
tPHLD
Differential High to
Low Propagation
Delay
50
10
dB
240
ps
240
ps
EQUALIZATION
DJ1
DJ2
DJ3
RJ
Residual
Deterministic Jitter at
3.2 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x06,
PRBS-7 (27-1) pattern
(Note 5, 6)
0.12
0.2
UIP-P
Residual
Deterministic Jitter at
2.5 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x06,
PRBS-7 (27-1) pattern
(Note 5, 6)
0.1
0.16
UIP-P
Residual
Deterministic Jitter at
1 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x06,
PRBS-7 (27-1) pattern
(Note 5, 6)
0.05
UIP-P
Random Jitter
(Note 7, 8)
0.5
psrms
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in psrms, see point C of Figure 1;
JIN is the random jitter at the input of the equalizer in psrms, see point B of Figure 1.
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4
DS32EV100
20206504
FIGURE 1. Test Setup Diagram
20206505
FIGURE 2. CML Output Transition Times
20206506
FIGURE 3. Propagation Delay Timing Diagram
5
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DS32EV100
tions. The equalizer channel consists of an equalizer stage,
a limiting amplifier, a DC offset correction block, and a CML
driver as shown in Figure 4.
DS32EV100 Application Information
The DS32EV100 is a programmable equalizer optimized for
operation up to 3.2 Gbps for backplane and cable applica-
20206507
FIGURE 4. Simplified Block Diagram
EQUALIZER BOOST CONTROL
The equalizer channel supports eight programmable levels of
equalization boost, and is controlled by the Boost Set pins
(BST_[2:0]) in accordance with Table 1. The eight levels of
boost settings enables the DS32EV100 to address a wide
range of media loss and data rates.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML lines
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for additional information on LLP packages.
TABLE 1. EQ Boost Control Table
6 mil
Microstrip
FR4 Trace
Length (in)
24 AWG
Twin-AX
Cable
Length (m)
Channel
Loss 1.6 GHz
(dB)
[BST_2,
BST_1,
BST_0]
0
0
0
000
5
2
3
001
10
3
6
010
15
4
7
011
20
5
8
100
25
6
10
101
30
7
12
110
40
10
14
110
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS32EV100 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS32EV100.
Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS32EV100.
GENERAL RECOMMENDATIONS
The DS32EV100 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner’s
Manual for more detailed information on high-speed design
tips to address signal integrity design issues.
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6
DS32EV100
Typical Performance Eye Diagrams and Curves
20206508
20206509
Figure 5. Equalized Signal
(40 in FR4, 1 Gbps, PRBS 7, 0x07 Setting)
Figure 6. Equalized Signal
(40 in FR4, 2.5 Gbps, PRBS 7, 0x07 Setting)
20206510
20206511
Figure 7. Equalized Signal
(40 in FR4, 3.2Gbps, PRBS 7, 0x07 Setting)
Figure 8. Equalized Signal
(10m 24 AWG Twin-AX Cable, 3.2 Gbps, PRBS 7, 0x07
Setting)
20206512
Figure 9. Equalized Signal
(32 in Tyco XAUI Backplane, 3.125 Gbps, PRBS 7, 0x07
Setting
20206513
Figure 10. DJ vs. EQ Setting (3.2 Gbps)
7
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DS32EV100
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin Leadless LLP Package
Order Number DS32EV100
NS Package Number SDA14A
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8
DS32EV100
Notes
9
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DS32EV100 Programmable Single Equalizer
Notes
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