RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DFP,VP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is f abricated using high-perf ormance 3 poly silicon CMOS technology . The use of resistiv e load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough f or battery back-up application. It is ideal f or the memory sy stems which require simple interf ace. Especially the M5M5256DVP are packaged in a 28-pin thin small outline package. FEATURE Ty pe Power supply current Access Oprating time Temperature Activ e Stand-by (max) (max) (max) PIN CONFIGURATION (TOP VIEW) A14 A12 1 28 2 A7 A6 A5 A4 3 27 26 4 25 A3 A2 A1 A0 DQ1 DQ2 7 A13 A8 24 A9 23 A11 22 /OE 8 21 9 20 5 6 Vcc /W 10 19 11 18 12 17 13 16 A10 /S DQ8 DQ7 DQ6 DQ5 15 DQ4 DQ3 GND 14 Outline 28P2W-C (FP) 20µA M5M5256DFP,VP (Vcc= 5.5V) 70ns -70G 0~70 °C 12µA (Vcc= 3.6V) 45mA (Vcc= 5.5V) M5M5256DFP,VP 70ns -70GI 40µA (Vcc= 5.5V) -40~85 °C 24µA 25mA (Vcc= 3.6V) (Vcc= 3.6V) 5µA (Vcc= 5.5V) M5M5256DFP,VP -70XG 70ns 0~70 °C •Single 3.0~5.5V power supply •No clocks, no ref resh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •/OE prev ents data contention in the I/O bus •Common Data I/O •Battery backup capability •Low stand-by current .......... 0.05µA(ty p.) 2.4µA (Vcc= 3.6V) 22 /OE 23 A11 24 25 26 27 28 1 2 3 4 0.05µA 5 (Vcc= 3.0V Typical) 6 7 A9 A8 A13 /W Vcc A14 A12 A7 A6 A5 A4 A3 M5M5256DVP Outline A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8 28P2C-A (VP) PACKAGE M5M5256DFP M5M5256DVP : 28 pin 450 mil SOP 2 : 28pin 8 X 13.4 mm TSOP APPLICATION Small capacity m emory units 1 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM The operation mode of the M5M5256DFP,VP is determined by a combination of the dev ice control inputs /S, /W and /OE. Each mode is summarized in the f unction table. A write cy cle is executed whenev er the low lev el /W ov erlaps with the low lev el /S. The address must be set up bef ore the write cy cle and must be stable during the entire cy cle. The data is latched into a cell on the trailing edge of /W, /S, whichev er occurs f irst, requiring the setup and hold time relativ e to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high lev el,the output stage is in a high-impedance state, and the data bus contention problem in the write cy cle is eliminated. A read cy cle is executed by setting /W at a high lev el and /OE at a low lev el while /S are in an activ e state. When setting /S at a high lev el, the chip is in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specif ied as Icc3 or Icc4, and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the nonselected mode. FUNCTION TABLE /S /W /OE Mode DQ Icc H X X Non selection High-impedance Stand-by L L X Write D IN Activ e L H L Read D OUT Activ e High-impedance Activ e L H H Note • "H" and "L" in this table mean VIH and VIL, respectiv ely . • "X" in this table should be "H" or "L". BLOCK DIAGRAM ADDRESS INPUT A8 25 A 13 26 A 14 1 A 12 22 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 A 10 21 A 11 23 A9 24 WRITE CONTROL INPUT /W 27 CHIP SELECT INPUT 20 /S OUTPUT ENABLE /OE INPUT 22 32768 WORD X 8BIT 11 DQ1 12 DQ2 13 DQ3 15 DQ4 16 DQ5 17 DQ6 18 DQ7 19 DQ8 28 VCC (5V) 14 GND (0V) (512 ROWS X 512 COLUMNS) DATA I/O CLOCK GENERATOR 2 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Conditions Symbol Parameter Supply voltage Vcc VI Input voltage Output voltage VO Pd Power dissipation T opr Operating temperature T stg Storage temperature Ratings -0.3 * ~7.0 -0.3 * ~Vcc+0.3 With respect to GND Unit V V V mW (Max 7.0) 0~Vcc 700 0~70 -40~85 -65~150 Ta=25°C -G,-XG -GI °C °C _ 30ns ) * -3.0V in case of AC ( Pulse width < DC ELECTRICAL CHARACTERISTICS Limits2 Limits1 Symbol Parameter (Vcc=3.3±0.3V) Test conditions (Vcc=5.0±0.5V) Unit Min Typ Max Min Typ Max V IH High-level input voltage 2.0 V IL Low-level input voltage -0.3* V OH1 High-level output voltage 1 V OH2 V OL II IO Icc1 Icc2 IOH=-1mA IOH=-0.5mA IOH=-0.1mA High-level output voltage 2 IOH=-0.05mA IOL=2mA Low-level output voltage IOL=1mA (Vcc=5.0±0.5V) (Vcc=3.3±0.3V) (Vcc=5.0±0.5V) (Vcc=3.3±0.3V) (Vcc=5.0±0.5V) (Vcc=3.3±0.3V) Input current V I =0 ~ Vcc Output current in off-state /S=V IH or or /OE=V IH, V I/O =0 ~ Vcc Active supply current _ /S<0.2V, Output-open (AC, MOS lev el ) Other inputs<0.2V or >Vcc-0.2V Active supply current /S=V IL, Output-open other inputs=VIH or V IL (AC, TTL lev el ) ~25°C Icc3 Icc4 Stand-by current Stand-by current Vcc +0.3 Vcc +0.3 2.2 0.6 -0.3* V 0.8 V 2.4 2.4 V Vcc -0.5 Vcc -0.5 V 0.4 0.4 V ±1 ±1 ±1 ±1 µA 70ns 13 25 25 40 1MHz 1.5 3 2 4 70ns 14 25 25 45 1MHz 1.5 3 1.2 4 8 2 -G,-GI -XG 0.05 0.3 -G,-GI _ /S>Vcc-0.2V, ~40°C -XG other inputs =0~Vcc -G,-GI ~70°C -XG ~85°C -GI /S=V IH,other inputs=0~ Vcc µA mA mA 0.1 0.4 3.6 6 0.8 1.2 12 20 2.4 24 5 40 0.33 3 µA mA * -3.0V in case of AC ( Pulse width _ < 30ns ) CAPACITANCE Symbol CI CO Parameter Input capacitance Output capacitance Test conditions V I =GND, V I =25mVrms, f=1MHz V O =GND,V O =25mVrms, f=1MHz Min Limits Typ Max 6 8 Unit pF pF Note 0: Direction f or current f lowing into an IC is positiv e (no mark). 1: Ty pical v alue is one at Ta = 25°C. 2: C I , C O are periodically sampled and are not 100% tested. 3 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address Limits1 Limits2 Vcc=3.3±0.3V Vcc=5.0±0.5V Min 70 Max Min 70 70 70 35 25 25 5 5 10 Unit Max 70 70 35 25 25 5 5 10 ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE Symbol Parameter tCW Write cycle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect to /W high tsu(S) Chip select setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recovery time tdis(W) Output disable time from /W low tdis(OE) Output disable time from /OE high ten(W) Output enable time from /W high ten(OE) Output enable time from /OE low Limits1 Limits2 Vcc=3.3±0.3V Vcc=5.0±0.5V Min 70 55 0 65 65 30 0 0 Max Min 70 50 0 65 65 30 0 0 25 25 5 5 Max 25 25 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 4 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM (3) TIMING DIAGRAMS Read cycle tCR A 0~ 14 ta(A) tv (A) ta (S) /S (Note 3) ta (OE) tdis(S) (Note 3) tdis (OE) (Note 3) ten (OE) /OE (Note 3) ten (S) DATA VALID DQ1~ 8 /W = "H" lev el Write cycle (/W control mode) tCW A 0~ 14 t su (S) /S (Note 3) (Note 3) tsu (A-WH) /OE tsu (A) tw (W) trec (W) /W tdis (W) tdis (OE) ten (W) ten(OE) DATA IN STABLE DQ1~ 8 (Note 3) (Note 3) tsu (D) th (D) 5 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM Write cycle ( /S control mode) tCW A 0~ 14 tsu (A) tsu (S) trec (W) /S (Note 5) /W (Note 4) (Note 3) tsu (D) (Note 3) th (D) DATA IN STABLE DQ1~ 8 (4) MEASUREMENT CONDITIONS Limits1:Vcc=3.3±0.3V Input pulse level .............. V IH=2.4V,V IL=0.4V Input rise and fall time ..... 5ns Reference level ................ V OH=V OL=1.5V Output load ...................... Fig.1, CL=30pF CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) DQ CL (Including scope and JIG) Fig.1 Output load Limits2:Vcc=5.0±0.5V Input pulse level .............. V IH=2.4V,V IL=0.6V Input rise and fall time ..... 5ns Reference level ................ V OH=V OL=1.5V Output load ...................... Fig.2, CL=100pF CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) Vcc 1.8k Ω DQ 990Ω CL (Including scope and JIG) Fig.2 Output load Note 3 4 5 6 7 : : : : : Hatching indicates the state is "don't care". Writing is executed in ov erlap of /S and /W low. If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state. Don't apply inv erted phase signal externally when DQ pin is output mode. ten, tdis are periodically sampled and are not 100% tested. 6 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc (PD) VI (/S) Parameter Test conditions Power down supply v oltage _ VCC(PD) 2.2V < _ VCC(PD) < _ 2.2V 2V< Chip select input /S (PD) Power down supply current _ Vcc -0.2V, Vcc = 3V, /S > Other inputs=0~Vcc V VCC(PD) ~40°C ~70°C ~85°C -G,-GI 0.05 -XG -G,-GI Unit V 2.2 ~25°C Icc Limits Typ Max Min 2 V 1 0.2 3 0.6 -XG -G,-GI µA 10 2 20 -XG -GI (2) TIMING REQUIREMENTS Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recov ery time Min Limits Typ Max Unit ns ns 0 tCR (3) POWER DOWN CHARACTERISTICS /S control mode Vcc tsu (PD) 3.0V 3.0V 2.2V 2.2V /S trec (PD) _ Vcc - 0.2V /S > 7 RENESAS LSIs M5M5256DFP,VP -70G,-70GI,-70XG 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! · Renesas T echnology Corporation puts the m axim um effort int o m a k ing sem iconductor products better and more reliable, but there is always the possibility that trouble m ay occur with them . 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