MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Those are summarized in the part name table below. DESCRIPTION FEATURES The M5M5V416C is a f amily of low v oltage 4-Mbit static RAMs organized as 262144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5V416C is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416CWG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards. Version, Operating temperature I-version -40 ~ +85°C Power Supply Part name M5M5V416CWG -70HI 2.7 ~ 3.0V Access time max. 70ns - Single 2.7~3.0V power supply Small stand-by current: 0.1µA (2.85V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.18µm CMOS Package: 48ball 7.0mm x 8.5mm CSP Stand-by c urrent (Vcc=3.0V) Ratings (max.) * Ty pical 25°C 40°C 25°C 40°C 70°C 85°C 0.2 0.4 1 2 10 20 Activ e current Icc1 (3.0V, ty p.) 40mA (10MHz) 5mA (1MHz) * Typical parameter indicates the value for the center of distribution, and not 100% tested. PIN CONFIGURATION (TOP VIEW) Pin A0 ~ A17 Function Address input DQ1 ~ DQ16 Data input / output S1 S2 W OE Chip select input 1 Chip select input 2 Write control input Output enable input BC1 Lower By te (DQ1 ~ 8) BC2 Upper By te (DQ9 ~ 16) Vcc Power supply GND Ground supply Outline: 48FJA NC: No Connection MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5V416CWG is organized as 262144-words by 16-bit. These dev ices operate on a single +2.7~3.0V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lower- When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply c urrent is reduced as low as 0.1µA(25°C, ty pical), and the memory data can be held at +1V power supply , enabling battery back-up operation during power FUNCTION TABLE S1 S2 BC1 BC2 X L X X H H X X X X H H H L H L L H L H L H L H L H H L L H H L L H H L L H L L L H L L L L H L W OE X X X X X X L X H L H H L X H L H H L X H L H H Mode Non selection Non selection Non selection Write Read Write Read Write Read DQ1~8 DQ9~16 High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z Icc Standby Standby Standby Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e BLOCK DIAGRAM A0 DQ 1 A1 MEMORY ARRAY DQ 8 262144 WORDS x 16 BITS A 16 - DQ 9 A 17 S1 CLOCK GENERATOR DQ 16 S2 BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Parameter With respect to GND Output v oltage With respect to GND Operating temperature Storage temperature T stg Units Ratings Supply v oltage Input v oltage Power dissipation Ta Conditions -0.5 * ~ +3.6 -0.2 * ~ Vcc + 0.2 0 ~ Vcc 700 With respect to GND Ta=25°C I-v ersion V mW - 40 ~ +85 °C - 65 ~ +150 °C * -3.0V in case of AC (Pulse width < = 30ns) DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH V OL II IO ( Vcc=2.7 ~ 3.0V, unless otherwise noted) Parameter Limits Conditions Min 2.2 -0.2 * 2.4 High-lev el input v oltage Low-lev el input v oltage High-level output voltage Low-lev el output v oltage Input leakage current Output leakage current I OH= -0.5mA I OL=2mA V I =0 ~ Vcc f = 10MHz 40 5 40 f = 1MHz - 5 10 ~ +25°C - 0.1 1 f = 10MHz Activ e supply c urrent Icc 2 ( AC,TTL lev el ) BC1 and BC2=V IL , S1=V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) Icc 3 Stand by s upply current ( MOS lev el ) > Vcc - 0.2V, S2 = other inputs = 0 ~ Vcc (2) S2 <= 0.2V, other inputs = 0 ~ Vcc (3) BC1 and BC2 => Vcc - 0.2V > S1 < = 0.2V, S2= Vcc - 0.2V other inputs = 0 ~ Vcc f = 1MHz - ~ +40°C Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) 0.2 V µA mA 2 µA ~ +85°C BC1 and BC2=VIH or S1=VIH or S2=VIL Icc 4 Stand by s upply current ( TTL lev el ) 0.4 - BC1 and BC2< = 0.2V, S1< = 0.2V, S2 Vcc-0.2V > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) Units Vcc+0.2V BC1 and BC2=VIH or S1=VIH or S2=VIL or OE=VIH, VI/O=0 ~ Vcc (1) S1 => Vcc - 0.2V, Max 0.4 ±1 ±1 50 10 50 Icc 1 Activ e supply c urrent ( AC,MOS lev el ) Ty p - - 20 - - 0.5 mA * -1.0V in case of AC (Pulse width < = 30ns) Note 2: Typical parameter indicates the value for the center of distribution at 2.85V, and is not 100% tested. CAPACITANCE Symbol CI CO Parameter (Vcc=2.7 ~ 3.0V, unless otherwise noted) Conditions Min Input capacitance V I =GND, VI =25mVrms, f =1MHz Output capacitance V O = GND,VO =25mVrms, f =1MHz MITSUBISHI ELECTRIC Limits Ty p Max 10 10 Units pF 3 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=2.7 ~ 3.0V, unless otherwise noted) 1TTL 2.7~3.0V Input pulse V IH=2.4V, V IL=0.2V Input rise time and f all time 5ns Supply v oltage Ref erence lev el V OH=V OL=1.5V DQ CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t dis (BC1) t dis (BC2) t en(OE) t V(A) 70HI Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address Min 70 Units Max 70 70 70 70 70 35 25 25 25 25 25 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S1) t su(S2) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) Units 70HI Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low Min 70 55 0 60 60 60 60 60 35 0 0 Max 25 25 5 5 MITSUBISHI ELECTRIC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~18 t v (A) t a(A) t a(BC1) or t a(BC2) BC1,BC2 (Note3) t dis (BC1) or t dis (BC1) (Note3) t a(S1) S1 (Note3) t dis (S1) (Note3) t dis (S2) (Note3) t a(S2) S2 (Note3) t a (OE) OE (Note3) t en (OE) W = "H" lev el DQ 1~16 Write cycle ( W control mode ) t dis (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) (Note3) VALID DATA t CW A 0~18 t su (BC1) or t su (BC2) BC1,BC2 (Note3) (Note3) t su (S1) S1 (Note3) (Note3) S2 t su (S2) (Note3) (Note3) OE t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) t CW A 0~18 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1,BC2 S1 (Note3) (Note3) S2 (Note3) W (Note3) (Note5) (Note4) (Note3) (Note3) t su (D) DQ 1~16 t h (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1 control mode) t CW A 0~18 BC1,BC2 (Note3) t su (S1) t su (A) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) t su (D) t h (D) (Note3) DATA IN STABLE DQ 1~16 Write cycle (S2 control mode) t CW A 0~18 BC1,BC2 (Note3) t su (A) t su (S2) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Parameter Test conditions Min V I (S1) V I (S2) Byte control input BC1 & BC2 Chip select input S1 2.7V Vcc(PD) 2.0V Vcc(PD) 2.7V 2.7V Vcc(PD) 2.0V Vcc(PD) 2.7V 2.2 2.2 0.2 - 0.1 0.8 other inputs = 0 ~ Vcc ~ +40°C - 0.2 1.5 ~ +85°C - - 15 (3) BC1 and BC2 => Vcc - 0.2V µA Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested. (2) TIMING REQUIREMENTS t su (PD) t rec (PD) ~ +25°C other inputs = 0 ~ Vcc (2) S2 <= 0.2V, > S1 < = 0.2V, S2= Vcc - 0.2V other inputs = 0 ~ Vcc Symbol V Vcc(PD) (1) S1 => Vcc - 0.2V, (PD) V Vcc(PD) Vcc=2.0V Icc Units V Chip select input S2 Power down supply c urrent Max 2.0 (PD) Power down supply voltage V I (BC) Limits Ty p Limits Parameter Test conditions Min Ty p Max 0 5 Power down set up time Power down recov ery t ime Units ns ms (3) TIMING DIAGRAM BC control mode Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1 BC2 BC1 , BC2 > = Vcc-0.2V S1 control mode note7 : On the S1 mode, the level of S2 must be fixed at S2 > Vcc-0.2V or S2 = Vcc t su (PD) 2.7V 2.7V 0.2V. t rec (PD) 2.2V 2.2V S1 > = Vcc-0.2V S1 S2 control mode Vcc 2.7V S2 2.7V t su (PD) t rec (PD) 0.2V 0.2V S2 0.2V MITSUBISHI ELECTRIC 8 MITSUBISHI LSIs 2000.11.22 Ver. 1.0 M5M5V416CWG -70HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Revision History Ver. 0.0 / September.08.2000 Initial (-70HI) MITSUBISHI ELECTRIC Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI ELECTRIC