RJK0353DSP Silicon N Channel Power MOS FET Power Switching REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Features • • • • Capable of 4.5 V gate drive Low drive current High density mounting Low on-resistance RDS(on) = 4.5 mΩ typ. (at VGS = 10 V) • Pb-free Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8<FP-8DAV>) 8 5 6 7 8 D D D D 5 76 12 1, 2, 3 Source 4 Gate 5, 6, 7, 8 Drain 4 G 34 S S S 1 2 3 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Symbol Ratings Unit VDSS VGSS ID 30 ±20 18 V V A 144 18 A A Note1 ID(pulse) IDR Avalanche current Avalanche energy IAP Note 2 EAR Note 2 16 25.6 A mJ Channel dissipation Channel to ambient thermal impedance Pch Note3 θch-a Note3 2.0 62.5 W °C/W Tch Tstg 150 –55 to +150 °C °C Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tch = 25°C, Rg ≥ 50 Ω 3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 1 of 6 RJK0353DSP Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Gate Resistance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Body–drain diode reverse recovery time Symbol V(BR)DSS IGSS IDSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss Rg Qg Qgs Qgd td(on) tr td(off) tf VDF trr Notes: 4. Pulse test REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 2 of 6 Min 30 — — 1.2 — — — — — — — — — — — — — Typ — — — — 4.5 5.9 41 2180 420 135 2.0 15 5.4 3.0 8.5 4.0 46.4 Max — ± 0.1 1 2.5 5.9 8.3 — — — — — — — — — — — Unit V µA µA V mΩ mΩ S pF pF pF Ω nC nC nC ns ns ns — — — 6.0 0.8 20 — 1.04 — ns V ns Test Conditions ID = 10 mA, VGS = 0 VGS = ±20 V, VDS = 0 VDS = 30 V, VGS = 0 VDS = 10 V, I D = 1 mA ID = 9 A, VGS = 10 V Note4 ID = 9 A, VGS = 4.5 V Note4 ID = 9 A, VDS = 10 V Note4 VDS = 10 V VGS = 0 f = 1 MHz VDD = 10 V VGS = 4.5 V ID = 9 A VGS = 10 V, ID = 9 A VDD ≅ 10 V RL = 1.11 Ω Rg = 4.7 Ω IF = 18 A, VGS = 0 Note4 IF = 18 A, VGS = 0 diF/ dt = 100 A/ µs RJK0353DSP Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating 3.0 500 Test Condition : When using the glass epoxy board (FR4 40x40x1.6 mm), PW ≤ 10 s 10 µs 100 Drain Current ID (A) Channel Dissipation Pch (W) 4.0 2.0 1.0 PW DC 10 = 1m Op 10 era 10 0µ s s ms tio 1 n( Operation in this area is limited by RDS(on) PW ≤ 1 Note 0s 5 ) 0.1 Ta = 25 °C 1 shot Pulse 0 50 100 0.01 0.1 200 150 0.3 1 3 10 30 100 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) Note 5 : When using the glass epoxy board (FR4 40x40x1.6 mm) Typical Output Characteristics Typical Transfer Characteristics 50 50 Pulse Test 3.2 V ID (A) 40 3.0 V 30 40 VDS = 10 V Pulse Test 30 Drain Current Drain Current ID (A) 4.5 V 10 V 2.8 V 20 VGS = 2.6 V 10 20 10 25°C Tc = 75°C –25°C 0 2 4 6 Drain to Source Voltage 8 0 10 120 80 ID = 10 A 40 5A 2A 0 4 8 12 Gate to Source Voltage 16 20 VGS (V) REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 3 of 6 3 4 5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (mΩ) Drain to Source Saturation Voltage VDS (on) (mV) Pulse Test 2 Gate to Source Voltage VDS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage 160 1 100 Pulse Test 30 10 VGS = 4.5 V 10 V 3 1 1 3 10 30 Drain Current 100 ID 300 1000 (A) Static Drain to Source on State Resistance vs. Temperature Typical Capacitance vs. Drain to Source Voltage 20 10000 Pulse Test 3000 16 Capacitance C (pF) Static Drain to Source on State Resistance RDS (on) (mΩ) RJK0353DSP 12 ID = 2 A, 5 A, 10 A 8 VGS = 4.5 V 4 0 –25 0 25 50 75 Tc (°C) 12 VDS 8 20 10 4 VDD = 25 V 10 V 0 0 20 40 Gate Charge 60 80 0 100 Qg (nc) Repetitive Avalanche Energy EAR (mJ) 50 IAP = 16 A VDD = 15 V duty < 0.1 % Rg ≥ 50 Ω 30 20 10 0 25 50 75 100 125 150 Channel Temperature Tch (°C) REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 4 of 6 30 20 Pulse Test 10 V 40 5V 30 20 VGS = 0, –5 V 10 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage VSD (V) Maximum Avalanche Energy vs. Channel Temperature Derating 40 10 50 Reverse Drain Current IDR (A) 16 VDD = 25 V 10 V VGS (V) 20 VGS 40 30 VGS = 0 f = 1 MHz Reverse Drain Current vs. Source to Drain Voltage Gate to Source Voltage VDS (V) Drain to Source Voltage ID = 18 A Crss Drain to Source Voltage VDS (V) Dynamic Input Characteristics 50 Coss 100 10 0 100 125 150 Case Temperature 300 30 2 A, 5 A, 10 A 10 V Ciss 1000 RJK0353DSP Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γs (t) 10 D=1 1 0.5 0.2 0.1 0.1 0.05 0.01 θch - f(t) = γs (t) x θch - f θch - f = 83.3°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.02 0.01 1s 0.001 h p ot uls e PDM D= PW T PW T 0.0001 10 µ 100 µ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (s) Avalanche Test Circuit Avalanche Waveform EAR = L VDS Monitor 1 L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor V(BR)DSS IAP Rg VDS VDD D. U. T ID Vin 15 V 50 Ω 0 VDD Switching Time Test Circuit Switching Time Waveform Vout Monitor Vin Monitor 90% D.U.T. Rg RL Vin Vout Vin 10 V 10% 10% 10% VDS = 10 V 90% td(on) REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 5 of 6 tr 90% td(off) tf RJK0353DSP Package Dimensions JEITA Package Code P-SOP8-3.95 × 4.9-1.27 RENESAS Code PRSP0008DD-D Previous Code FP-8DAV MASS[Typ.] 0.085g F Package Name SOP-8 *1 D bp 1 c *2 E Index mark HE 5 8 4 Z Terminal cross section (Ni/Pd/Au plating) * 3 bp x M e NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Dimension in Millimeters Symbol Min D E A2 A1 A bp b1 c c1 A1 A L1 L y HE e x y Z L L1 Detail F Ordering Information Part No. RJK0353DSP-00-J0 Quantity 2500 pcs REJ03G1648-0401 Rev.4.01 Apr 24, 2008 Page 6 of 6 Shipping Container Taping Nom Max 4.90 5.3 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.1 0.75 0.40 0.60 1.27 1.08 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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