RENESAS M30800SAFP

M32C/80 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0038-0110
Rev.1.10
Nov. 01, 2005
1. Overview
The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic
molded LQFP/QFP package.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
The M32C/80 Group is ROMless device.
Use the M32C/80 Group in microprocessor mode after reset.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.10 Nov. 01, 2005 page 1
REJ03B0038-0110
of 56
1. Overview
M32C/80 Group
1.2 Performance Overview
Table 1.1 lists performance overview of the M32C/80 Group.
Table 1.1 M32C/80 Group Performance
CPU
Item
Basic Instructions
Minimum Instruction Execution Time
Operating Mode
Memory Space
Memory Capacity
Peripheral I/O Port
function Multifunction Timer
Intelligent I/O Communication Function
Serial I/O
A/D Converter
D/A Converter
DMAC
DMAC II
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Characteristics Power Consumption
Operating AmbientTemperature
Package
NOTES:
Performance
108 instructions
31.3 ns ( f(BCLK)=32 MHz, VCC1=4.2 to 5.5 V )
41.7 ns ( f(BCLK)=24 MHz, VCC1=3.0 to 5.5 V )
Single-chip mode, Memory expansion mode, Microprocessor mode
16 Mbytes
See Table 1.2
47 I/O pins (when using 16-bit bus) and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
2 channels
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus(1), I2C Bus(2)
10-bit A/D converter: 1 circuit, 10 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, operation and chain transfer function
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
34 internal sources and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main Clock oscillation circuit (*), Sub clock oscillation circuit (*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor
Main clock oscillation stop detect circuit
VCC1=4.2 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=32 MHz)
VCC1=3.0 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=24 MHz)
22 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz)
17 mA (VCC1=VCC2=3.3 V, f(BCLK)=24 MHz)
10 µA (VCC1=VCC2=3.3 V, f(BCLK)=32 kHz, in wait mode)
–20 to 85oC, –40 to 85oC(optional)
100-pin plastic molded LQFP/QFP
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 2
of 56
1. Overview
M32C/80 Group
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
8
8
(1)
Port P0
8
(2)
Port P1
8
(1)
8
(1)
Port P2
Port P3
8
(1)
Port P4
(1)
Port P5
<VCC2>
8
7
DMAC
8
UART/
Clock Synchronous Serial I/O
5 channels
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Port P8
Clock Generating Circuit
XIN - XOUT
XCIN - XCOUT
On-chip Oscillator
PLL Frequency Synthesizer
Port P7
A/D Converter
1 circuit
Standard: 8 inputs
Maximum: 10 inputs
Port P6
Peripheral Functions
DMACII
Three-phase Motor Control Circuit
X/Y converter
16 bits X 16 bits
R0H
R0L
R1H
R1L
A1
ISP
R3
USP
RAM
PC
SVF
SVP
SB
VCT
Multiplier
Rev. 1.10 Nov. 01, 2005 page 3
REJ03B0038-0110
of 56
8
Port P10
FB
NOTES:
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode
and all external data buses are selected as 8-bit buses.
Figure 1.1 M32C/80 Group Block Diagram
8
A0
Intelligent I/O
Communication Function
2 channels
INTB
R2
Port P9
D/A Converter
8 bits X 2 channels
Memory
FLG
P85
M32C/80 series CPU core
<VCC1>
Watchdog Timer (15 bits)
CRC Calcilation Circuit (CCITT)
X16+X12+X5+1
1. Overview
M32C/80 Group
1.4 Product Information
Table 1.2 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.2 M32C/80 Group
As of November, 2005
Type Number
Package Type
M30800SAGP
PLQP0100KB-A (100P6Q-A)
M30800SAFP
PRQP0100JB-A (100P6S-A)
M30800SAGP-BL
PLQP0100KB-A (100P6Q-A)
M30800SAFP-BL
PRQP0100JB-A (100P6S-A)
ROM
Capacity
RAM
Capacity
Remarks
ROMless
−
8K
ROMless with
on-chip boot loader
M30800 S A GP -BL
On-chip boot loader
Package type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Memory type:
S = ROMless version
RAM capacity, pin count, etc
M32C/80 Group
M16C Family
Figure 1.2 Product Numbering System
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 4
of 56
1. P70 and P71 are ports for the N-channel open drain output.
Figure 1.3 Pin Assignment
Rev. 1.10 Nov. 01, 2005 page 5
REJ03B0038-0110
of 56
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SRxD3 / SDA3 / TxD3 / TB2IN / P92
STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc1
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
ISRxD0 / U / TA4OUT / P80
25
26
27
28
29
30
ISRxD1 / W / TA2IN / P75
ISCLK1 / W / TA2OUT / P74
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
SRxD2 / SDA2 / TxD2 / TA0OUT / P70
24
4
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
23
3
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
ISCLK0 / TA3IN / P77
2
ISTxD0 / TA3OUT / P76
1
CLK4 / ANEX0 / P95
STxD4 / SCL4 /
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
P14 / D12
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 )
P21 / A1 ( / D1 )
P22 / A2 ( / D2 )
P23 / A3 ( / D3 )
P24 / A4 ( / D4 )
P25 / A5 ( / D5 )
P26 / A6 ( / D6 )
P27 / A7 ( / D7 )
Vss
P30 / A8 ( / D8 )
Vcc2
P31 / A9 ( / D9 )
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P34 / A12 ( / D12 )
P35 / A13 ( / D13 )
P36 / A14 ( / D14 )
P37 / A15 ( / D15 )
P40 / A16
P41 / A17
P42 / A18
P43 / A19
58
57
56
55
54
53
52
51
P32 / A10 ( / D10 )
P13 / D11
77
P33 / A11 ( / D11 )
P12 / D10
78
59
P11 / D9
79
60
P10 / D8
80
M32C/80 Group
1. Overview
1.5 Pin Assignment
Figures 1.3 and 1.4 show pin assignments (top view).
D7 / P07
81
D6 / P06
82
D5 / P05
83
D4 / P04
84
D3 / P03
85
46
P50 / WRL / WR
D2 / P02
86
45
P51 / WRH / BHE
D1 / P01
87
44
P52 / RD
D0 / P00
88
43
P53 / CLKOUT / BCLK / ALE
KI3 / AN7 / P107
89
42
P54 / HLDA / ALE
KI2 / AN6 / P106
90
41
P55 / HOLD
KI1 / AN5 / P105
91
40
P56 / ALE
KI0 / AN4 / P104
92
39
P57 / RDY
AN3 / P103
93
38
P60 / CTS0 / RTS0 / SS0
AN2 / P102
94
37
P61 / CLK0
AN1 / P101
95
36
P62 / RxD0 / SCL0 / STxD0
AVss
96
35
P63 / TxD0 / SDA0 / SRxD0
AN0 / P100
97
34
P64 / CTS1 / RTS1 / SS1
VREF
98
33
P65 / CLK1
AVcc
99
32
P66 / RxD1 / SCL1 / STxD1
RxD4 / ADTRG / P97
100
31
P67 / TxD1 / SDA1 / SRxD1
<VCC2>
M32C/80 GROUP
<VCC1>
50
P44 / CS3 / A20
49
P45 / CS2 / A21
48
P46 / CS1 / A22
47
P47 / CS0 / A23
NOTE:
PRQP0100JB-A
(100P6S-A)
1. Overview
P36 / A14 ( / D14 )
P37 / A15 ( / D15 )
P40 / A16
P41 / A17
52
51
Vcc2
60
53
P30 / A8 ( / D8 )
61
54
Vss
62
P34 / A12 ( / D12 )
P27 / A7 ( / D7 )
63
P35 / A13 ( / D13 )
P26 / A6 ( / D6 )
64
55
P25 / A5 ( / D5 )
65
P33 / A11 ( / D11 )
P24 / A4 ( / D4 )
66
56
P23 / A3 ( / D3 )
67
57
P22 / A2 ( / D2 )
68
P31 / A9 ( / D9 )
P21 / A1 ( / D1 )
69
P32 / A10 ( / D10 )
P20 / A0 ( / D0 )
70
58
P17 / D15 / INT5
71
59
P15 / D13 / INT3
P16 / D14 / INT4
72
P14 / D12
74
73
P13 / D11
75
M32C/80 Group
D10 / P12
76
50
P42 / A18
D9 / P11
77
49
P43 / A19
D8 / P10
78
D7 / P07
<VCC2>
48
P44 / CS3 / A20
79
47
P45 / CS2 / A21
D6 / P06
80
46
P46 / CS1 / A22
D5 / P05
81
45
P47 / CS0 / A23
D4 / P04
82
44
P50 / WRL / WR
D3 / P03
83
43
P51 / WRH / BHE
D2 / P02
84
42
P52 / RD
D1 / P01
85
41
P53 / CLKOUT / BCLK / ALE
D0 / P00
86
40
P54 / HLDA / ALE
KI3 / AN7 / P107
87
39
P55 / HOLD
KI2 / AN6 / P106
88
38
P56 / ALE
KI1 / AN5 / P105
89
37
P57 / RDY
KI0 / AN4 / P104
90
36
P60 / CTS0 / RTS0 / SS0
AN3 / P103
91
35
P61 / CLK0
AN2 / P102
92
34
P62 / RxD0 / SCL0 / STxD0
AN1 / P101
93
33
P63 / TxD0 / SDA0 / SRxD0
AVss
94
32
P64 / CTS1 / RTS1 / SS1
AN0 / P100
95
31
P65 / CLK1
VREF
96
30
P66 / RxD1 / SCL1 / STxD1
AVcc
97
29
P67 / TxD1 / SDA1 / SRxD1
STxD4 / SCL4 / RxD4 / ADTRG / P97
98
28
P70 / TA0OUT / TxD2 / SDA2 / SRxD2
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
99
27
P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2
CLK4 / ANEX0 / P95
100
26
P72 / TA1OUT / V / CLK2
M32C/80 GROUP
15
16
17
18
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
25
14
Vcc1
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
13
XIN
24
12
Vss
ISCLK1 / W / TA2OUT / P74
11
XOUT
23
10
RESET
22
9
XCOUT / P86
ISTxD0 / TA3OUT / P76
8
XCIN / P87
ISRxD1 / W / TA2IN / P75
7
CNVss
21
6
BYTE
ISCLK0 / TA3IN / P77
5
CLK3 / TB0IN / P90
20
4
STxD3 / SCL3 / RxD3 / TB1IN / P91
19
3
SRxD3 / SDA3 / TxD3 / TB2IN / P92
U / TA4IN / P81
2
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
ISRxD0 / U / TA4OUT / P80
1
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
<VCC1>
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
Figure 1.4 Pin Assignment
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 6
of 56
PLQP0100KB-A
(100P6Q-A)
1. Overview
M32C/80 Group
Table 1.3 Pin Characteristics
Package
Pin No
FP GP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Control
pins
Port
Interrupt
pins
P96
P95
P94
P93
P92
P91
P90
BYTE
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
Timer
pins
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
UART
pins
Analog
pins
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
ANEX1
ANEX0
DA1
DA0
Bus control
pins
Intelligent I/O
pins
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
NMI
INT2
INT1
INT0
Rev. 1.10 Nov. 01, 2005 page 7
REJ03B0038-0110
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TB5IN/TA0IN
TA0OUT
ISRxD0
ISCLK0
ISTxD0
ISRxD1
ISCLK1
ISTxD1
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
RDY
ALE
HOLD
HLDA/ALE
CLKOUT/BCLK/ALE
RD
WRH/BHE
WRL/WR
CS0/A23
CS1/A22
CS2/A21
CS3/A20
of 56
1. Overview
M32C/80 Group
Table 1.3 Pin Characteristics (Continued)
Package
pin No
FP GP
Control
pins
Port
Interrupt
pins
Timer
pins
UART
pins
Analog
pins
Bus control
pins
49
50
P43
A19
P42
A18
51
52
P41
A17
P40
A16
55
56
57
53
54
55
P37
P36
A15(/D15)
A14(/D14)
A13(/D13)
58
59
56
57
P34
P33
58
59
P32
A11(/D11)
A10(/D10)
P31
A9(/D9)
P30
A8(/D8)
P27
P26
A7(/D7)
51
52
53
54
60
61
62
63
64
65
66
P35
60
61
VCC2
62
63
64
VSS
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
83
84
85
81
82
83
86
87
84
85
A12(/D12)
A6(/D6)
A5(/D5)
P25
A4(/D4)
P24
P23
A3(/D3)
A2(/D2)
P22
P21
P20
P17
P16
P15
A1(/D1)
A0(/D0)
D15
INT5
INT4
INT3
D14
D13
P14
P13
D12
D11
P12
D10
P11
D9
P10
P07
D8
D7
P06
P05
D6
D5
P04
D4
P03
P02
D3
D2
P01
D1
D0
88
89
90
86
87
88
P00
91
89
92
93
94
90
91
92
P105
P104
95
96
97
93
94
95
98
99
96
97
100
98
P107
KI3
AN7
P106
KI2
KI1
AN6
AN5
KI0
P103
AN4
AN3
P102
AN2
P101
AN1
P100
AN0
VREF
AVSS
AVCC
P97
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 8
RxD4/SCL4/STxD4
of 56
ADTRG
Intelligent I/O
pins
1. Overview
M32C/80 Group
1.6 Pin Description
Table 1.4 Pin Description
Signal name
Power supply
Analog power
supply input
Reset input
Pin name I/O type
VCC1, VCC2
VSS
AVCC
AVSS
____________
RESET
I
Supply
voltage
Description
-
Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the
I
VCC1
VSS pin. VCC1 ≥ VCC2(1)
Supplies power for the A/D converter. Connect the AVCC pin to
I
VCC1
VCC1 and the AVSS pin to VSS
The microcomputer is in a reset state when "L" is applied to the
RESET pin
Connect this pin to VCC1
____________
CNVSS
External data
CNVSS
I
VCC1
BYTE
I
VCC1
D0 to D7
I/O
VCC2
when the this pin is held "H". Set it to either one.
Inputs and outputs data (D0 to D7) while accessing an external
D8 to D15
I/O
VCC2
memory space with separate bus
Inputs and outputs data (D8 to D15) while accessing an external
O
VCC2
memory space with 16-bit separate bus
Outputs address bits (A0 to A22)
O
I/O
VCC2
VCC2
Outputs inversed address bit A23
Inputs and outputs data (D0 to D7) and outputs 8 low-order
bus width
select input
Bus control
pins
A0 to A22
Switches the data bus in external memory space 3. The data
bus is 16 bits long when the this pin is held "L" and 8 bits long
______
A23
A0/D0 to
A7/D7
address bits (A0 to A7) by time-sharing while accessing an
external memory space with multiplexed bus
A8/D8 to
A15/D15
______
I/O
VCC2
______
CS0 to CS3
O
VCC2
O
VCC2
Inputs and outputs data (D8 to D15) and outputs 8 middle-order
address bits (A8 to A15) by time-sharing while accessing an
external memory space with multiplexed bus
______
______
Output CS0 to CS3 that are chip-select signals specifying an external space
________ ______
WRL/WR
_________ ________
WRH/BHE
_______
_____
________
RD
________
______
________
_____
_______
________
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH
______
_______
can be switched with WR and BHE by program
_________
_____
WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is writtenn to an even
_______
address when WRL is held "L".
________
Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L".
______ ________
_____
WR, BHE and RD are selected
______
Data is written to external memory space when WR is held "L".
_____
Data is read when RD is held "L".
________
An odd address is accessed when BHE is held "L".
______ ________
_____
Select WR, BHE and RD for an external 8-bit data bus
ALE
__________
HOLD
O
I
VCC2
VCC2
ALE is a signal latching address
__________
The microcomputer is placed in a hold state while the HOLD pin
O
VCC2
is held "L"
Outputs an "L" siganl while the microcomputer is placed in a hold state
I
VCC2
Bus is placed in a wait state while the RDY pin is held "L"
__________
HLDA
________
RDY
I: Input
O: Output
I/O: Input and output
NOTE:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
Rev. 1.10 Nov. 01, 2005 page 9
REJ03B0038-0110
of 56
1. Overview
M32C/80 Group
Table 1.4 Pin Description (Continued)
Signal name
Main clock input XIN
XOUT
Main clock
output
I
Supply
voltage
VCC1
O
VCC1
Pin name I/O type
Description
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. To apply
external clock, input the clock from XIN and leave XOUT open
I/O pins for a sub clock oscillation circuit. Connect a crystal
Sub clock input XCIN
Sub clock
XCOUT
I
O
VCC1
VCC1
output
BCLK output
BCLK
O
VCC2
Clock output
______
INT interrupt
CLKOUT
_______
_______
INT0 to INT2
O
I
VCC2
VCC1
I
VCC2
VCC1
I
I/O
VCC1
VCC1
TA4OUT
TA0IN to
I
VCC1
Input pins for the timer A0 to A4
TA4IN
TB0IN to
I
VCC1
Input pins for the timer B0 to B5
O
VCC1
output pins for the three-phase motor control timer
I
VCC1
Input pins for data transmission control
_______
Outputs BCLK signal
Outputs clock having thesame frequency as fC, f8, or f32
______
Input pins for the INT interrupt
_______
input
INT3 to INT5
_______
NMI interrupt input NMI
_______
_____
_____
Key input interrupt KI0 to KI3
Timer A
TA0OUT to
Timer B
oscillator between XCIN and XCOUT. To apply external clock,
input the clock from XCIN and leave XCOUT open
TB5IN
__
__
Three-phase motor U, U, V, V,
_______
Input pin for the NMI interrupt
Input pins for the key input interrupt
I/O pins for the timer A0 to A4
(TA0OUT is a pin for the N-channel open drain output.)
__
control output
Serial I/O
W, W
_________
CTS0 to
_________
CTS4
_________
RTS0 to
O
VCC1
Output pins for data reception control
RTS4
CLK0 to
I/O
VCC1
Inputs and outputs the transfer clock
CLK4
RxD0 to
I
VCC1
Inputs serial data
RxD4
TxD0 to
O
VCC1
Outputs serial data (TxD2 is a pin for the N-channel open drain
VCC1
output.)
Inputs and outputs serial data (SDA2 is a pin for for the N-
_________
I 2C
mode
TxD4
SDA0 to
I/O
SDA4
SCL0 to
I/O
VCC1
channel open drain output.)
Inputs and outputs the transfer clock (SCL2 is a pin for the N-
SCL4
STxD0 to
I
VCC1
channel open drain output.)
Outputs serial data when slave mode is selected (SDA2 is a pin
special function STxD4
SRxD0 to
I
VCC1
for the N-channel open drain output.)
Inputs serial data when slave mode is selected
I
VCC1
Input pins to control serial I/O special function
Serial I/O
SRxD4
______
_______
SS0 to SS4
I: Input
O: Output
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
I/O: Input and output
page 10
of 56
1. Overview
M32C/80 Group
Table 1.5 Pin Description (Continued)
Signal name
Pin name I/O type
Supply
voltage
Reference
voltage input
VREF
I
-
A/D converter
AN0 to AN7
___________
ADTRG
I
I
VCC1
VCC1
I/O
VCC1
ANEX0
D/A converter
ANEX1
DA0, DA1
Intelligent I/O
ISCLK0
communication ISCLK1
function
ISTxD0
Description
Applies reference voltage for the A/D converter and D/A converter
Analog input pins for the A/D converter
Input pin for an external A/D trigger
Extended analog input pin for the A/D converter and output pin in
external op-amp connection mode
Extended analog input pin for the A/D converter
I
O
VCC1
VCC1
I/O
VCC1
Output pin for the D/A converter
Inputs and outputs clock for the intelligent I/O communication
O
VCC1
fucntion
Outputs data for the intelligent I/O communication fucntion
I
VCC1
Inputs data for the intelligent I/O communication fucntion
I/O
VCC2
I/O ports fro CMOS. Each port can be programmed for nput or
ISTxD1
ISRxD0
ISRxD1
I/O port
P00 to P07(1)
P10 to P17(2)
output under the control of the direction register. An input port
can be set, by program, for a pull-up resistor available or for no
P20 to P27(1)
P30 to P37(1)
pull-up resistor available in 4-bit units
P40 to P47(1)
P50 to P57(1)
P60 to P67
P70 to P77
P90 to P97
P100 to P107
P80 to P84,
I/O
VCC1
I/O ports having equivalent functions to P0
(P70 and P71 are ports for the N-channel open drain output.)
I/O
VCC1
I/O ports having equivalent functions to P0
I
VCC1
Shares a pin with NMI. NMI input state can be got by reading P8 5
P86, P87
_______
I: Input
NOTES:
P85
O: Output
_______
I/O: Input and output
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. They
cannot be used as I/O ports.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor
mode and all external data buses are selected as 8-bit buses.
Rev. 1.10 Nov. 01, 2005 page 11
REJ03B0038-0110
of 56
2. Central Processing Unit (CPU)
M32C/80 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers.
Two sets of register banks are provided.
b31
b15
General Registers
b0
R2
R0H
R3
R1H
R0L
R1L
Data Register(1)
R2
R3
b23
A0
Address Register(1)
A1
SB
Static Base Register(1)
FB
Frame Base Register(1)
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
INTB
Interrupt Table Register
Program Counter
PC
FLG
b15
Flag Register
b8 b7
IPL
b0
U I O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved Space
b15
High-speed Interrupt Registers
b0
SVF
b23
Flag Save Register
SVP
PC Save Register
VCT
Vector Register
b7
DMAC-associated Registers
b0
DMD0
DMD1
b15
DCT0
DCT1
DMA Mode Register
DMA Transfer Count Register
DRC0
DRC1
b23
DMA Transfer Count Reload Register
DMA0
DMA1
DMA Memory Address Register
DRA0
DRA1
DMA Memory Address Reload Register
DSA0
DSA1
DMA SFR Address Register
NOTE:
1. The register bank is comprised of these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
Page 12 of 56
2. Central Processing Unit (CPU)
M32C/80 Group
2.1 General Registers
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC, 24 bits wide, indicates the address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow has occurred after executing an instruction.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
Page 13 of 56
2. Central Processing Unit (CPU)
M32C/80 Group
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows:
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
2.3 DMAC-Associated Registers
Registers associated with DMAC are as follows:
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
Page 14 of 56
3. Memory
M32C/80 Group
3. Memory
Figure 3.1 shows a memory map of the M32C/80 Group.
The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16.
The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine.
The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is
allocated from address 00040016 to 0023FF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged.
SFRs, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers, is allocated from address 00000016 to 0003FF16. All blank spaces within SFRs are reserved and
cannot be accessed by users.
The special page vector table is addressed from FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
In microprocessor mode, some spaces are reserved and cannot be accessed by users.
00000016
SFRs
00040016
0023FF16
Internal RAM
Reserved Space
FFFE00 16
01000016
Special Page
Vector Table
FFFFDC 16
Undefined Instruction
Overflow
BRK Instruction
Address Match
External Space
Watchdog Timer(1)
FFFFFF16
FFFFFF 16
NMI
Reset
NOTE:
1. Watchdog timer interrupt and oscillation stop detection interrupt share vectors.
Figure 3.1 Memory Map
Rev. 1.10 Nov. 01, 2005 Page 15
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
4. Special Function Registers (SFRs)
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
Register
Symbol
Value after RESET
Processor Mode Register(1)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
0000 00112(CNVss pin ="H")
0016
0000 10002
0010 00002
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
0016
XXXX 00002
XXXX 10002(BYTE pin ="L")
000B16
External Data Bus Width Control Register
DS
000C16
000D16
000E16
000F16
001016
001116
Main Clock Division Register
Oscillation Stop Detection Register
Watchdog Timer Start Register
Watchdog Timer Control Register
MCD
CM2
WDTS
WDC
XXXX 00002(BYTE pin ="H")
XXX0 10002
0016
XX16
000X XXXX2
Address Match Interrupt Register 0
RMAD0
00000016
Processor Mode Register 2
PM2
0016
001216
001316
001416
001516
Address Match Interrupt Register 1
RMAD1
00000016
001616
001716
001816
001916
Address Match Interrupt Register 2
RMAD2
00000016
001A16
001B16
001C16
001D16
Address Match Interrupt Register 3
RMAD3
00000016
PLL Control Register 0
PLL Control Register 1
PLC0
PLC1
0001 X0102
000X 00002
Address Match Interrupt Register 4
RMAD4
00000016
Address Match Interrupt Register 5
RMAD5
00000016
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed.
Rev. 1.10 Nov. 01, 2005 Page 16
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
Value after RESET
Address Match Interrupt Register 6
RMAD6
00000016
Address Match Interrupt Register 7
RMAD7
00000016
External Space Wait Control Register 0
External Space Wait Control Register 1
External Space Wait Control Register 2
External Space Wait Control Register 3
EWCR0
EWCR1
EWCR2
EWCR3
X0X0 00112
X0X0 00112
X0X0 00112
X0X0 00112
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 17
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
Register
Symbol
Value after RESET
DMA0 Interrupt Control Register
Timer B5 Interrupt Control Register
DMA2 Interrupt Control Register
UART2 Receive /ACK Interrupt Control Register
Timer A0 Interrupt Control Register
UART3 Receive /ACK Interrupt Control Register
Timer A2 Interrupt Control Register
UART4 Receive /ACK Interrupt Control Register
Timer A4 Interrupt Control Register
UART0/UART3 Bus Conflict Detect Interrupt Control Register
DM0IC
TB5IC
DM2IC
S2RIC
TA0IC
S3RIC
TA2IC
S4RIC
TA4IC
BCN0IC/BCN3IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
UART0 Receive/ACK Interrupt Control Register
A/D0 Conversion Interrupt Control Register
UART1 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 0
Timer B1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 2
Timer B3 Interrupt Control Register
Intelligent I/O Interrupt Control Register 4
INT5 Interrupt Control Register
S0RIC
AD0IC
S1RIC
IIO0IC
TB1IC
IIO2IC
TB3IC
IIO4IC
INT5IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
INT3 Interrupt Control Register
INT3IC
XX00 X0002
INT1 Interrupt Control Register
INT1IC
XX00 X0002
DMA1 Interrupt Control Register
UART2 Transmit /NACK Interrupt Control Register
DMA3 Interrupt Control Register
UART3 Transmit /NACK Interrupt Control Register
Timer A1 Interrupt Control Register
UART4 Transmit /NACK Interrupt Control Register
Timer A3 Interrupt Control Register
UART2 Bus Conflict Detect Interrupt Control Register
DM1IC
S2TIC
DM3IC
S3TIC
TA1IC
S4TIC
TA3IC
BCN2IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 18
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
Register
UART0 Transmit /NACK Interrupt Control Register
UART1/UART4 Bus Conflict Detect Interrupt Control Register
UART1 Transmit/NACK Interrupt Control Register
Key Input Interrupt Control Register
Timer B0 Interrupt Control Register
Intelligent I/O Interrupt Control Register 1
Timer B2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 3
Timer B4 Interrupt Control Register
Symbol
S0TIC
BCN1IC/BCN4IC
S1TIC
KUPIC
TB0IC
IIO1IC
TB2IC
IIO3IC
TB4IC
Value after RESET
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
INT4 Interrupt Control Register
INT4IC
XX00 X0002
INT2 Interrupt Control Register
INT2IC
XX00 X0002
INT0 Interrupt Control Register
Exit Priority Control Register
Interrupt Request Register 0
Interrupt Request Register 1
Interrupt Request Register 2
Interrupt Request Register 3
Interrupt Request Register 4
INT0IC
RLVL
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
XX00 X0002
XXXX 00002
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Enable Register 4
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
0016
0016
0016
0016
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 19
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Register
Symbol
Value after RESET
SI/O Receive Buffer Register 0
G0RB
Transmit Buffer/Receive Data Register 0
G0TB/G0DR
XXXX XXXX2
XXX0 XXXX2
XX16
Receive Input Register 0
SI/O Communication Mode Register 0
Transmit Output Register 0
SI/O Communication Control Register 0
G0RI
G0MR
G0TO
G0CR
XX16
0016
XX16
0000 X0112
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 20
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
Register
Data Compare Register 00
Data Compare Register 01
Data Compare Register 02
Data Compare Register 03
Data Mask Register 00
Data Mask Register 01
Communication Clock Select Register
Symbol
G0CMP0
G0CMP1
G0CMP2
G0CMP3
G0MSK0
G0MSK1
CCS
Receive CRC Code Register 0
G0RCRC
Transmit CRC Code Register 0
G0TCRC
SI/O Expansion Mode Register 0
SI/O Expansion Receive Control Register 0
SI/O Special Communication Interrupt Detect Register 0
SI/O Expansion Transmit Control Register 0
G0EMR
G0ERC
G0IRF
G0ETC
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XXXX 00002
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 21
REJ03B0038-0110
of 56
XX16
0016
0016
0016
0016
0016
0000 0XXX2
4. Special Function Registers (SFRs)
M32C/80 Group
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
to
02AF16
Register
Symbol
Value after RESET
XXXX XXXX2
SI/O Receive Buffer Register 1
G1RB
Transmit Buffer/Receive Data Register 1
G1TB/G1DR
XXX0 XXXX2
XX16
Receive Input Register 1
SI/O Communication Mode Register 1
Transmit Output Register 1
SI/O Communication Control Register 1
Data Compare Register 10
Data Compare Register 11
Data Compare Register 12
Data Compare Register 13
Data Mask Register 10
Data Mask Register 11
G1RI
G1MR
G1TO
G1CR
G1CMP0
G1CMP1
G1CMP2
G1CMP3
G1MSK0
G1MSK1
XX16
0016
XX16
0000 X0112
XX16
XX16
XX16
XX16
XX16
XX16
Receive CRC Code Register 1
G1RCRC
Transmit CRC Code Register 1
G1TCRC
SI/O Expansion Mode Register 1
SI/O Expansion Receive Control Register 1
SI/O Special Communication Interrupt Detection Register 1
SI/O Expansion Transmit Control Register 1
G1EMR
G1ERC
G1IRF
G1ETC
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 22
REJ03B0038-0110
of 56
XX16
0016
0016
0016
0016
0016
0000 0XXX2
4. Special Function Registers (SFRs)
M32C/80 Group
Address
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
Register
Symbol
Value after RESET
XX16
X0 Register Y0 Register
X0R,Y0R
X1 Register Y1 Register
X1R,Y1R
X2 Register Y2 Register
X2R,Y2R
X3 Register Y3 Register
X3R,Y3R
X4 Register Y4 Register
X4R,Y4R
X5 Register Y5 Register
X5R,Y5R
X6 Register Y6 Register
X6R,Y6R
X7 Register Y7 Register
X7R,Y7R
X8 Register Y8 Register
X8R,Y8R
X9 Register Y9 Register
X9R,Y9R
X10 Register Y10 Register
X10R,Y10R
X11 Register Y11 Register
X11R,Y11R
X12 Register Y12 Register
X12R,Y12R
X13 Register Y13 Register
X13R,Y13R
X14 Register Y14 Register
X14R,Y14R
X15 Register Y15 Register
X15R,Y15R
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 23
REJ03B0038-0110
of 56
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
X/Y Control Register
Register
Symbol
XYC
Value after RESET
XXXX XX002
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
0016
0016
0016
0016
0016
XX16
XX16
UART1 Transmit Buffer Register
02EB16
02EC16 UART1 Transmit/Receive Control Register 0
02ED16 UART1 Transmit/Receive Control Register 1
02EE16
UART1 Receive Buffer Register
02EF16
02F016
02F116
02F216
02F316
02F416 UART4 Special Mode Register 4
02F516 UART4 Special Mode Register 3
02F616 UART4 Special Mode Register 2
02F716 UART4 Special Mode Register
02F816 UART4 Transmit/Receive Mode Register
02F916 UART4 Bit Rate Register
02FA16
UART4 Transmit Buffer Register
02FB16
02FC16 UART4 Transmit/Receive Control Register 0
02FD16 UART4 Transmit/Receive Control Register 1
02FE16
UART4 Receive Buffer Register
02FF16
030016 Timer B3, B4, B5 Count Start Flag
030116
030216
Timer A1-1 Register
030316
030416
Timer A2-1 Register
030516
030616
Timer A4-1 Register
030716
030816 Three-Phase PWM Control Register 0
030916 Three-Phase PWM Control Register 1
030A16 Three-Phase Output Buffer Register 0
030B16 Three-Phase Output Buffer Register 1
030C16 Dead Time Timer
030D16 Timer B2 Interrupt Generation Frequency Set Counter
030E16
030F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 24
REJ03B0038-0110
of 56
U1TB
U1C0
U1C1
U1RB
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
U4C0
U4C1
U4RB
TBSR
XX16
0000 10002
0000 00102
XX16
XX16
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
000X XXXX2
XX16
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
XX16
XX16
XX16
XX16
XX16
0016
0016
XX11 11112
XX11 11112
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Register
Symbol
Value after RESET
XX16
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 00002
00XX 00002
00XX 00002
External Interrupt Request Source Select Register
IFSR
0016
UART3 Special Mode Register 4
UART3 Special Mode Register 3
UART3 Special Mode Register 2
UART3 Special Mode Register
UART3 Transmit/Receive Mode Register
UART3 Bit Rate Register
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
UART3 Transmit Buffer Register
U3TB
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
U3C0
U3C1
UART3 Receive Buffer Register
U3RB
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
UART2 Receive Buffer Register
U2RB
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 25
REJ03B0038-0110
of 56
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
Register
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
Count Source Prescaler Register(1)
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
UART0 Transmit Buffer Register
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
UART0 Receive Buffer Register
U0RB
Value after RESET
0016
0XXX XXXX2
0016
0016
0016
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
00XX 00002
00XX 00002
00XX 00002
XXXX XXX02
0XXX 00002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has
been performed.
Rev. 1.10 Nov. 01, 2005 Page 26
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
Symbol
Value after RESET
DMA0 Request Source Select Register
DMA1 Request Source Select Register
DMA2 Request Source Select Register
DMA3 Request Source Select Register
DM0SL
DM1SL
DM2SL
DM3SL
CRC Data Register
CRCD
CRC Input Register
CRCIN
A/D0 Register 0
AD00
A/D0 Register 1
AD01
A/D0 Register 2
AD02
A/D0 Register 3
AD03
A/D0 Register 4
AD04
A/D0 Register 5
AD05
A/D0 Register 6
AD06
A/D0 Register 7
AD07
A/D0 Control Register 2
A/D0 Control Register 3
A/D0 Control Register 0
A/D0 Control Register 1
D/A Register 0
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
XX0X XXX02
XXXX X0002
0016
0016
XX16
D/A Register 1
DA1
XX16
D/A Control Register
DACON
XXXX XX002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 27
REJ03B0038-0110
of 56
0X00 00002
0X00 00002
0X00 00002
0X00 00002
XX16
XX16
XX16
XXXX XXXX2
0000 00002
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFRs)
M32C/80 Group
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Register
Symbol
Value after RESET
Function Select Register D1
PSD1
X0XX XX002
Function Select Register C3
PSC3
X0XX XXXX2
Function Select Register C
Function Select Register A0
Function Select Register A1
Function Select Register B0
Function Select Register B1
Function Select Register A2
Function Select Register A3
Function Select Register B2
Function Select Register B3
PSC
PS0
PS1
PSL0
PSL1
PS2
PS3
PSL2
PSL3
00X0 00002
0016
0016
0016
0016
00X0 00002
0016
00X0 00002
0016
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XX16
XX16
0016
0016
XX16
XX16
00X0 00002
0016
XX16
Port P10 Direction Register
PD10
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.10 Nov. 01, 2005 Page 28
REJ03B0038-0110
of 56
4. Special Function Registers (SFRs)
M32C/80 Group
Address
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Register
Symbol
Value after RESET
Pull-Up Control Register 2
Pull-Up Control Register 3
PUR2
PUR3
0016
0016
Port P0 Register(1)
Port P1 Register(1)
P0
P1
XX16
XX16
Port P0 Direction Register(1)
Port P1 Direction Register(1)
Port P2 Register(1)
Port P3 Register(1)
Port P2 Direction Register(1)
Port P3 Direction Register(1)
Port P4 Register(1)
Port P5 Register(1)
Port P4 Direction Register(1)
Port P5 Direction Register(1)
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Pull-up Control Register 0
Pull-up Control Register 1
PUR0
PUR1
0016
XXXX 00002
Port Control Register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. Pins, functioning as bus control pins, cannot be selected as I/O ports.
Rev. 1.10 Nov. 01, 2005 Page 29
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Condition
Value
Unit
VCC1, VCC2
Symbol
Supply Voltage
Parameter
VCC1=AVCC
-0.3 to 6.0
V
VCC2
Supply Voltage
-
-0.3 to VCC1
V
AVCC
Analog Supply Voltage
VI
Input Voltage
VCC1=AVCC
RESET, CNVSS, BYTE, P60-P67, P72-P77,
P80-P87, P90-P97, P100-P107, VREF, XIN
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57
Output Voltage
V
V
-0.3 to VCC2+0.3
P70, P71
VO
-0.3 to 6.0
-0.3 to VCC1+0.3
-0.3 to 6.0
P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, XOUT
-0.3 to VCC1+0.3
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57
-0.3 to VCC2+0.3
P70, P71
V
-0.3 to 6.0
Pd
Power Dissipation
500
mW
Topr
Operating Ambient Temperature
Topr=25° C
-20 to 85/
-40 to 85(1)
°C
Tstg
Storage Temperature
-65 to 150
°C
NOTE:
1. Contact our sales office if temperature range of -40 to 85° C is required.
Rev. 1.10 Nov. 01, 2005 Page 30
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
Table 5.2 Recommended Operating Conditions
(VCC1= VCC2=3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified)
Symbol
Parameter
VCC1, VCC2
AVCC
Supply Voltage (VCC1≥ VCC2)
Analog Supply Voltage
VSS
Supply Voltage
AVSS
Analog Supply Voltage
Input High ("H")
Voltage
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
Input Low ("L")
Voltage
Typ.
5.0
VCC1
Max.
5.5
0
VCC2
P60-P67, P72-P77, P80-P87(3), P90-P97, P100-P107, XIN,
RESET, CNVSS, BYTE
P70, P71
0.8VCC1
VCC1
0.8VCC1
6.0
P00-P07, P10-P17 (in single-chip mode)
0.8VCC2
VCC2
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
P20-P27, P30-P37, P40-P47, P50-P57
0.5VCC2
VCC2
0
0.2VCC2
0
0.2VCC1
0
0.2VCC2
0
0.16VCC2
P90-P97, P100-P107, XIN,
RESET, CNVSS, BYTE
P00-P07, P10-P17 (in single-chip mode)
NOTES:
1. Typical values when average output current is 100 ms.
2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, and P10 must be 80 mA or less.
Total IOL(peak) for P3, P4, P5, P6, P7, and P80 to P84 must be 80 mA or less.
Total IOH(peak) for P0, P1, and P2 must be -40 mA or less.
Total IOH(peak) for P86, P87, P9, and P10 must be -40 mA or less.
Total IOH(peak) for P3, P4, and P5 must be -40 mA or less.
Total IOH(peak) for P6, P7, and P80 to P84 must be -40 mA or less.
3. VIH and VIL reference for P87 applies when P87 is used as a programmable input port.
It does not apply when P87 is used as XCIN.
of 56
V
V
V
0.8VCC2
P60-P67, P70-P77, P80-P87(3),
Unit
V
P20-P27, P30-P37, P40-P47, P50-P57
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
Peak Output High
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("H") Current(2)
P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Average Output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
High ("H") Current(1) P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Peak Output Low
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("L") Current(2)
P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Average Output Low P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57,
("L") Current(1)
P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107
Rev. 1.10 Nov. 01, 2005 Page 31
REJ03B0038-0110
Min.
3.0
0
VIH
VIL
Standard
V
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
5. Electrical Characteristics
M32C/80 Group
Table 5.2 Recommended Operating Conditions (Continued)
(VCC1=VCC2=3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified)
Symbol
f(BCLK)
f(XIN)
f(XCIN)
CPU Operation Frequency
Main Clock Input Frequency
Min.
On-chip Oscillator Frequency (Topr=25° C)
f(PLL)
PLL Clock Frequency
Wait Time to Stabilize PLL Frequency Synthesizer
Rev. 1.10 Nov. 01, 2005 Page 32
REJ03B0038-0110
of 56
Typ.
Max.
Unit
VCC1=4.2 to 5.5 V
0
32
MHz
VCC1=3.0 to 5.5 V
0
24
MHz
VCC1=4.2 to 5.5 V
0
32
MHz
VCC1=3.0 to 5.5 V
0
24
MHz
Sub Clock Frequency
f(Ring)
tSU(PLL)
Standard
Parameter
0.5
32.768
50
kHz
1
2
MHz
VCC1=4.2 to 5.5 V
10
32
MHz
VCC1=3.0 to 5.5 V
10
24
MHz
VCC1=5.0 V
5
ms
VCC1=3.3 V
10
ms
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Table 5.3 Electrical Characteristics
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified)
Symbol
VOH
Parameter
Output High ("H")
Voltage
P00-P07, P10-P17,
P50-P57
P60-P67, P72-P77,
P97, P100-P107
P00-P07, P10-P17,
P50-P57
P60-P67, P72-P77,
P97, P100-P107
XOUT
Condition
P20-P27, P30-P37, P40-P47, IOH=-5mA
VCC2-2.0
Max.
VCC2
P80-P84, P86, P87, P90-
VCC1-2.0
VCC1
P20-P27, P30-P37, P40-P47, IOH=-200µA
VCC2-0.3
VCC2
IOH=-200µA
VCC1-0.3
VCC1
3.0
VCC1
P80-P84, P86, P87, P90-
XCOUT
VOL
Output Low ("L")
Voltage
VT+-VT- Hysteresis
Standard
IOH=-5mA
IOH=-1mA
Min.
Typ.
High Power
No load applied
2.5
Low Power
No load applied
1.6
P00-P07, P10-P17, P20-P27,
P50-P57, P60-P67, P70-P77,
P87, P90-P97, P100-P107
P00-P07, P10-P17, P20-P27,
P50-P57, P60-P67, P70-P77,
P30-P37, P40-P47, IOL=5mA
Unit
V
V
V
V
2.0
V
0.45
V
2.0
V
P80-P84, P86,
P30-P37, P40-P47, IOL=200µA
P80-P84, P86,
P87, P90-P97, P100-P107
XOUT
IOL=1mA
XCOUT
High Power
No load applied
0
Low Power
No load applied
0
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN,
V
0.2
1.0
V
0.2
1.8
5.0
V
µA
-5.0
µA
167
kΩ
60
MΩ
MΩ
V
mA
INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4,
TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
RESET
IIH
Input High ("H")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=5V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, XIN, RESET, CNVSS, BYTE
IIL
Input Low ("L")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, XIN, RESET, CNVSS, BYTE
RPULLUP Pull-up Resistance
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
P50-P57, P60-P67, P72-P77, P80-P84, P86,
20
40
P87, P90-P97, P100-P107
RfXIN
RfXCIN
VRAM
I CC
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
Power Supply Current
XIN
XCIN
In stop mode
In single-chip mode,
output pins are left
open and other pins
are connected to VSS.
Rev. 1.10 Nov. 01, 2005 Page 33
REJ03B0038-0110
of 56
1.5
15
2.0
f(BCLK)=32 MHz, Square wave,
No division
f(BCLK)=32 kHz, In wait mode,
Topr=25° C
While clock stops, Topr=25° C
While clock stops, Topr=85° C
22
µA
10
0.8
5
20
µA
µA
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Table 5.4 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF=4.2 to 5.5V, Vss= AVSS = 0V at
Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min.
-
INL
Resolution
VREF=VCC1
Integral Nonlinearity Error
DNL
Unit
Typ. Max.
10
AN0 to AN7, ANEX0,
ANEX1
±3
External op-amp
connection mode
±7
Bits
LSB
LSB
VREF=VCC1=VCC2=5V
LSB
LSB
Differential Nonlinearity Error
±1
-
Offset Error
±3
LSB
-
Gain Error
±3
LSB
40
kΩ
RLADDER
Resistor Ladder
tCONV
10-bit Conversion Time(1, 2)
VREF=VCC1
8
Time(1, 2)
LSB
2.06
µs
1.75
µs
0.188
µs
tCONV
8-bit Conversion
tSAMP
Sampling Time(1)
VREF
Reference Voltage
2
VCC1
V
VIA
Analog Input Voltage
0
VREF
V
NOTES:
1. Divide f(XIN), if exceeding 16 MHz, to keep φAD frequency at 16 MHz or less.
2. With using the sample and hold function.
Table 5.5 D/A Conversion Characteristics (VCC1=VCC2=VREF=4.2 to 5.5V, VSS=AVSS=0V
at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min.
tSU
Typ.
Unit
Max.
Resolution
8
Absolute Accuracy
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
4
10
(Note 1)
NOTE:
1. Measurement when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being
used, is set to "0016". The resistor ladder in the A/D converter is excluded.
IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
Rev. 1.10 Nov. 01, 2005 Page 34
REJ03B0038-0110
of 56
Bits
1.0
%
3
µs
20
kΩ
1.5
mA
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 5.6 External Clock Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
31.25
ns
tw(H)
External Clock Input High ("H") Width
13.75
ns
13.75
tw(L)
External Clock Input Low ("L") Width
tr
External Clock Rise Time
5
ns
ns
tf
External Clock Fall Time
5
ns
Table 5.7 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (RD standard)
(Note 1)
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard)
(Note 1)
ns
tac2(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexrd bus)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
26
ns
tsu(RDY-BCLK)
RDY Input Setup Time
26
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
30
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
td(BCLK-HLDA)
HLDA Output Delay Time
ns
25
NOTE:
1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a
wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
9
10 X m
tac1(RD – DB) = f(BCLK) X 2
tac1(AD – DB) =
109 X n
f(BCLK)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
– 35
[ns] (if external bus cycle is aφ + bφ, n=a+b)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
9
tac2(RD – DB) =
10 X m
f(BCLK) X 2
tac2(AD – DB) =
109 X p
– 35
f(BCLK) X 2
Rev. 1.10 Nov. 01, 2005 Page 35
REJ03B0038-0110
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
of 56
ns
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 5.8 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Width
40
ns
Table 5.9 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
tw(TAH)
TAiIN Input High ("H") Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Width
200
ns
400
ns
Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 5.12 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(UP)
TAiOUT Input Cycle Time
tw(UPH)
TAiOUT Input High ("H") Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.10 Nov. 01, 2005 Page 36
REJ03B0038-0110
of 56
2000
ns
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.13 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on both edges)
80
ns
Table 5.14 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
400
Unit
tc(TB)
TBiIN Input Cycle Time
ns
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
Table 5.15 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TB)
TBiIN Input Cycle Time
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
400
ns
Table 5.16 A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max
Unit
tc(AD)
ADTRG Input Cycle Time (required for trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Width
125
ns
Table 5.17 Serial I/O
Symbol
tc(CK)
Parameter
CLKi Input Cycle Time
Standard
Min.
Max.
200
Unit
ns
tw(CKH)
CLKi Input High ("H") Width
100
ns
tw(CKL)
CLKi Input Low ("L") Width
100
ns
td(C-Q)
TxDi Output Delay Time
80
ns
th(C-Q)
TxDi Hold Time
0
ns
tsu(D-C)
RxDi Input Setup Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
_______
Table 5.18 External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi Input High ("H") Width
250
ns
tw(INL)
INTi Input Low ("L") Width
250
ns
Rev. 1.10 Nov. 01, 2005 Page 37
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.19 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Measurement
Condition
Standard
Min.
Unit
Max.
18
-3
ns
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
-3
ns
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
0
ns
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
18
See Figure 5.1
(Note 1)
ns
ns
18
ns
18
ns
-5
ns
-5
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
10 9
th(WR – DB) =
– 10 [ns]
f(BCLK) X 2
9
10
th(WR – AD) =
– 10 [ns]
f(BCLK) X 2
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
9
tw(WR) =
10 X n
f(BCLK) X 2
– 15
[ns]
(if external bus cycle is aφ + bφ, n=(bx2)-1)
– 20
[ns]
(if external bus cycle is aφ + bφ, m= b)
9
td(DB – WR) =
10 X m
f(BCLK)
Rev. 1.10 Nov. 01, 2005 Page 38
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.20 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
Measurement
Condition
Standard
Min.
Unit
Max.
18
ns
-3
ns
Address Output Hold Time (RD standard)
(Note 1)
ns
Address Output Hold Time (WR standard)
(Note 1)
ns
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
18
ns
-3
ns
(Note 1)
ns
(Note 1)
See Figure 5.1
ns
18
ns
18
ns
-5
ns
th(BCLK-WR)
WR Signal Output Hold Time
-5
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
18
-5
ns
ns
td(AD-ALE)
ALE Signal Output Delay Time (address standard)
(Note 3)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 4)
ns
tdz(RD-AD)
Address Output Float Start Time
8
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, m= (bx2)-1)
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
td(AD – ALE) =
10 X n
f(BCLK) X 2
– 20
[ns] (if external bus cycle is aφ + bφ, n= a)
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
9
th(ALE – AD) =
10 X n
f(BCLK) X 2
Rev. 1.10 Nov. 01, 2005 Page 39
REJ03B0038-0110
– 10
of 56
[ns] (if external bus cycle is aφ + bφ, n= a)
ns
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=5V
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.1 P0 to P10 Measurement Circuit
Rev. 1.10 Nov. 01, 2005 Page 40
REJ03B0038-0110
of 56
30pF
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[ Read Timing ] (1φ +1φ Bus Cycle)
BCLK
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
-3ns.min
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
-3ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-5ns.min
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
26ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b)
[ Write timing ] (1φ +1φ Bus Cycle)
BCLK
th(BCLK-CS)
td(BCLK-CS)
18ns.max
-3ns.min
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
th(BCLK-AD)
18ns.max
-3ns.min
ADi
BHE
td(BCLK-WR)
WR,WRL,
WRH
18ns.max
tw(WR)(3)
th(WR-AD)(3)
th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTE:
3. Varies with operation frequency:
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ+bφ, m=b)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is aφ+bφ , n=(bx2)-1)
Figure 5.2 VCC1=VCC2=5V Timing Diagram (1)
Rev. 1.10 Nov. 01, 2005 Page 41
REJ03B0038-0110
of 56
Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
9
tcyc=
10
f(BCLK)
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
[ Read Timing ] (2φ +2φ Bus Cycle)
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
-5ns.min
18ns.max
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
-3ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
th(ALE-AD)
ADi
/DBi
Address
(1)
tsu(DB-BCLK) 26ns.min
Data input
tdz(RD-AD)
Address
8ns.max
td(BCLK-AD)
ADi
BHE
th(RD-DB)
tac2(RD-DB)(1)
18ns.max
(1)
td(BCLK-RD)
tac2(AD-DB)
th(BCLK-RD)
18ns.max
th(BCLK-AD)
-3ns.min
0ns.min
th(RD-AD)
(1)
-5ns.min
RD
NOTE:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
[ Write Timing ] (2φ +2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-5ns.min
ALE
tcyc
td(BCLK-CS)
th(BCLK-CS)
(2)
th(WR-CS)
-3ns.min
18ns.max
CSi
td(AD-ALE)
(2)
ADi
/DBi
(2)
th(ALE-AD)
Address
Address
Data output
td(DB-WR)
td(BCLK-AD)
(2)
(2)
th(WR-DB)
18ns.max
ADi
BHE
-3ns.min
td(BCLK-WR)
th(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTE:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
Figure 5.3 VCC1=VCC2=5V Timing Diagram (2)
Rev. 1.10 Nov. 01, 2005 Page 42
REJ03B0038-0110
th(BCLK-AD)
of 56
th(WR-AD) (2)
-5ns.min
Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
9
tcyc= 10
f(BCLK)
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
tc(TA)
tw(TAH)
TAiIN Input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT Input
tw(UPL)
TAiOUT Input
(Counter increment/
decrement input)
In event counter mode
TAiIN Input
th(TIN–UP)
tsu(UP–TIN)
(When counting on the falling edge)
TAiIN Input
(When counting on the rising edge)
tc(TB)
tw(TBH)
TBiIN Input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG Input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi Input
tw(INH)
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
Figure 5.4 VCC1=VCC2=5V Timing Diagram (3)
Rev. 1.10 Nov. 01, 2005 Page 43
REJ03B0038-0110
of 56
2 CPU clock cycles +
300ns or more
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
th(BCLK–RDY)
tsu(RDY–BCLK)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD Input
HLDA Output
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
td(BCLK–HLDA)
Hi–Z
Measurement Conditions
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 5.5 VCC1=VCC2=5V Timing Diagram (4)
Rev. 1.10 Nov. 01, 2005 Page 44
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Table 5.21 Electrical Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS=0V at Topr = –20 to 85oC,
f(BCLK)=24MHZ unless otherwise specified)
Symbol
VOH
Parameter
Output High ("H")
Voltage
Condition
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-1mA
Max.
VCC2
P50-P57
P60-P67, P72-P77, P80-P84, P86, P87, P90-
VCC1-0.6
VCC1
V
2.7
VCC1
V
XCOUT
IOH=-0.1mA
High Power
Low Power
Output Low ("L")
Voltage
VT+-VT- Hysteresis
Unit
Min.
Typ.
VCC2-0.6
P97, P100-P107
XOUT
VOL
Standard
No load applied
2.5
No load applied
1.6
V
V
V
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P84,
P86, P87, P90-P97, P100-P107
XOUT
IOL=1mA
0.5
V
IOL=0.1mA
0.5
V
XCOUT
High Power
No load applied
0
V
Low Power
No load applied
0
V
0.2
1.0
V
0.2
1.8
V
VI=3V
4.0
µA
VI=0V
-4.0
µA
500
kΩ
35
MΩ
MΩ
V
mA
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN,
INT0-INT5, ADTRG, CTS0-CTS4, CLK0CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0RxD4, SCL0-SCL4, SDA0-SDA4
RESET
IIH
Input High ("H")
Current
IIL
Input Low ("L")
Current
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87,
P90-P97, P100-P107, XIN, RESET, CNVSS,
BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87,
P90-P97, P100-P107, XIN, RESET, CNVSS,
BYTE
RPULLUP Pull-up Resistance
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
40
70
P50-P57, P60-P67, P72-P77, P80-P84, P86,
P87, P90-P97, P100-P107
RfXIN
RfXCIN
VRAM
ICC
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
Power Supply
Current
XIN
XCIN
in stop mode
Measurement condition:
In single-chip mode,
output pins are left open
and other pins are
connected to VSS.
3.0
30.0
2.0
f(BCLK)=24 MHz, Square wave,
No division
f(BCLK)=32 kHz, In wait mode,
Topr=25° C
17
While clock stops, Topr=25° C
0.8
While clock stops, Topr=85° C
Rev. 1.10 Nov. 01, 2005 Page 45
REJ03B0038-0110
of 56
µA
10
5
µA
50
µA
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Table 5.22 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF= 3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Unit
Min. Typ. Max.
-
Resolution
INL
DNL
Integral Nonlinearity Error
No S&H (8-bit)
VREF=VCC1
10
Bits
VCC1=VCC2=VREF=3.3V
±2
LSB
Differential Nonlinearity Error
No S&H (8-bit)
±1
LSB
-
Offset Error
No S&H (8-bit)
±2
LSB
-
Gain Error
No S&H (8-bit)
±2
LSB
40
kΩ
RLADDER
Resistor Ladder
VREF=VCC1
Time(1, 2)
tCONV
8-bit Conversion
VREF
Reference Voltage
VIA
Analog Input Voltage
8.0
µs
6.1
3.3
VCC1
V
0
VREF
V
S&H: Sample and Hold
NOTES:
1. Divide f(XIN), if exceeding 10 MHz, to keep φAD frequency at 10 MHz or less.
2. S&H not available.
Table 5.23 D/A Conversion Characteristics (VCC1=VCC2=VREF=3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min. Typ.
tSU
-
Resolution
-
Absolute Accuracy
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
4
(Note 1)
10
Unit
Max.
8
Bits
1.0
%
3
µs
20
kΩ
1.0
mA
NOTE:
1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being
used, is set to "0016". The resistor ladder in the A/D converter is excluded.
IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
Rev. 1.10 Nov. 01, 2005 Page 46
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.24 External Clock Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
41
ns
tw(H)
External Clock Input High ("H") Width
18
ns
18
tw(L)
External Clock Input Low ("L") Width
tr
External Clock Rise Time
5
ns
tf
External Clock Fall Time
5
ns
ns
Table 5.25 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data Input Access Time (RD standard)
(Note 1)
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard)
(Note 1)
ns
tac2(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
30
tsu(RDY-BCLK)
RDY Input Setup Time
ns
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
60
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
td(BCLK-HLDA)
HLDA Output Delay Time
25
ns
NOTE:
1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a
wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
9
10 X m
tac1(RD – DB) = f(BCLK) X 2
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
– 35
[ns] (if external bus cycle is aφ + bφ, n=a+b)
– 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
9
tac1(AD – DB) =
10 X n
f(BCLK)
9
tac2(RD – DB) =
10 X m
f(BCLK) X 2
tac2(AD – DB) =
109 X p
– 35
f(BCLK) X 2
Rev. 1.10 Nov. 01, 2005 Page 47
REJ03B0038-0110
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS= 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.26 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Width
40
ns
Table 5.27 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Width
200
ns
Table 5.28 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 5.29 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tw(TAH)
TAiIN Input High ("H") Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Width
100
ns
Table 5.30 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input High ("H") Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.10 Nov. 01, 2005 Page 48
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.31 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Width (counted on both edges)
80
ns
Table 5.32 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Wdth
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
Table 5.33 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Width
200
ns
Table 5.34 A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG Input Cycle Time (required for trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Width
125
ns
Table 5.35 Serial I/O
Symbol
tc(CK)
Parameter
CLKi Input Cycle Time
Standard
Min.
Max.
200
Unit
ns
tw(CKH)
CLKi Input High ("H") Width
100
ns
tw(CKL)
CLKi Input Low ("L") Width
100
ns
td(C-Q)
TxDi Output Delay Time
th(C-Q)
TxDi Hold Time
0
ns
tsu(D-C)
RxDi Input Setup Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
80
ns
_______
Table 5.36 External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi Input High ("H") Width
250
ns
tw(INL)
INTi Input Low ("L") Width
250
ns
Rev. 1.10 Nov. 01, 2005 Page 49
REJ03B0038-0110
of 56
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Switching Characteristics
(VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.37 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
18
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
18
0
See Figure 5.1
td(BCLK-WR)
WR Signal Output Delay Time
WR Signal Output Hold Time
ns
ns
0
ns
(Note 1)
ns
18
-3
th(BCLK-WR)
ns
ns
ns
18
ns
0
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(WR – DB) =
10 9
f(BCLK) X 2
– 20
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
9
tw(WR) =
10 x n
f(BCLK) X 2
– 15
[ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1)
– 20
[ns]
9
td(DB – WR) =
10 x m
f(BCLK)
Rev. 1.10 Nov. 01, 2005 Page 50
REJ03B0038-0110
of 56
(if external bus cycle is aφ + bφ, m=b)
5. Electrical Characteristics
M32C/80 Group
VCC1=VCC2=3.3V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.38 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
ns
th(RD-AD)
Address Output Hold Time (RD standard)
(Note 1)
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-Select Signal Output Delay Time
th(BCLK-CS)
Chip-Select Signal Output Hold Time (BCLK standard)
18
18
0
ns
ns
ns
th(RD-CS)
Chip-Select Signal Output Hold Time (RD standard)
(Note 1)
ns
th(WR-CS)
Chip-Select Signal Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
See Figure 5.1
18
-3
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
ns
ns
18
ns
0
ns
td(DB-WR)
Data Output delay Time (WR standard)
(Note 2)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
18
ns
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
-2
ns
td(AD-ALE)
ALE Signal Output Delay Time (address standard)
(Note 3)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 4)
tdz(RD-AD)
Address Output Float Start Time
ns
8
NOTES:
1. Values can be obtained by the following equations, according to BLCK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
–10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 20
[ns]
2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (if external bus cycle is aφ + bφ, m=(b+2)-1)
3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
td(AD – ALE) =
10 x n
f(BCLK) X 2
– 20
[ns] (if external bus cycle is aφ + bφ, n=a)
4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
9
th(ALE – AD) =
10 x n
f(BCLK) X 2
Rev. 1.10 Nov. 01, 2005 Page 51
REJ03B0038-0110
– 10
of 56
[ns] (if external bus cycle is aφ + bφ, n=a)
ns
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[Read Timing] (1φ + 1φ Bus Cycles)
BCLK
td(BCLK-CS)
th(BCLK-CS)
0ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
ADi
BHE
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-3ns.min
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
30ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b)
[Write Timing] (1φ + 1φ Bus Cycles)
BCLK
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(3)
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max
ADi
BHE
0ns.min
th(WR-AD)(3)
td(BCLK-WR) tw(WR)(3)
18ns.max
WR,WRL,
WRH
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTE:
3. Varies with operation frequency.
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ + bφ, m=b)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
Measurement Conditions
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
tcyc=
(if external bus cycle is aφ + bφ, n=(bx2)-1)
Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1)
Rev. 1.10 Nov. 01, 2005 Page 52
REJ03B0038-0110
of 56
10
9
f(BCLK)
M32C/80 Group
5. Electrical Characteristics
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
[ Read Timing ] (2φ +2φ Bus Cycles)
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
18ns.max
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
0ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
th(ALE-AD)
ADi
/DBi
(1)
Address
tsu(DB-BCLK) 30ns.min
Data input
tdz(RD-AD)
Address
8ns.max
td(BCLK-AD)
ADi
BHE
th(RD-DB)
tac2(RD-DB)(1)
18ns.max
(1)
td(BCLK-RD)
tac2(AD-DB)
th(BCLK-RD)
18ns.max
th(BCLK-AD)
0ns.min
0ns.min
th(RD-AD)
(1)
-3ns.min
RD
NOTE:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
[ Write Timing ] (2φ +2φ Bus Cycles)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
tcyc
td(BCLK-CS)
th(BCLK-CS)
(2)
th(WR-CS)
0ns.min
18ns.max
CSi
td(AD-ALE)
ADi
/DBi
(2)
(2)
th(ALE-AD)
Address
Address
Data output
td(DB-WR)
td(BCLK-AD)
(2)
(2)
th(WR-DB)
18ns.max
ADi
BHE
0ns.min
td(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTE:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2)
Rev. 1.10 Nov. 01, 2005 Page 53
REJ03B0038-0110
th(BCLK-AD)
of 56
th(BCLK-WR)
th(WR-AD) (2)
0ns.min
Measurement Conditions:
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
9
tcyc= 10
f(BCLK)
5. Electrical Characteristics
M32C/80 Group
Vcc1=Vcc2=3.3V
tc(TA)
tw(TAH)
TAiIN Input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT Input
tw(UPL)
TAiOUT Input
(Counter increment/
decrement input)
In event counter mode
TAiIN Input
th(TIN–UP)
tsu(UP–TIN)
(When counting on falling edge)
TAiIN Input
(When counting on rising edge)
tc(TB)
tw(TBH)
TBiIN Input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG Input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi Input
tw(INH)
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
Figure 5.8 VCC1=VCC2=3.3V Timing Diagram (3)
Rev. 1.10 Nov. 01, 2005 Page 54
REJ03B0038-0110
of 56
2 CPU clock cycles +
300ns or more
M32C/80 Group
5. Electrical Characteristics
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Measurement Conditions:
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=2.4V, VIL=0.6V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.9 VCC1=VCC2=3.3V Timing Diagram (4)
Rev. 1.10 Nov. 01, 2005 Page 55
REJ03B0038-0110
of 56
th(BCLK–RDY)
Package Dimensions
M32C/80 Group
Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
*3
e
bp
A1
c
A
A2
F
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
MASS[Typ.]
1.6g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
Rev. 1.10 Nov. 01, 2005 Page 56
REJ03B0038-0110
bp
Detail F
of 56
D
E
A2
HD
HE
A
A1
bp
c
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.5 0.65 0.8
0.10
0.575
0.825
0.4 0.6 0.8
M32C/80 Group Datasheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
0.10
Sep., 02
–
New Document
0.11
Sep., 02
3
Table 1.1.1 “CAN” deleted
0.12
Nov., 02
3
Table 1.1.1
“4.2 to 5.5V” --> “3.0 to 5.5V”
"3.0 to 3.6V (f(XIN)=20MHz without software wait)" deleted
"26mA (f(XIN)=20MHz without software wait,Vcc=3.3V)" deleted
0.30
Aug., 02
–
1. Overview
1.2 Performance Outline
1.3 Block Diagram
1.5 Pin Assignments
Table 1.3 Pin Characteristics for 100-Pin Package
1.6 Pin Description
2. Central Processing Unit (CPU)
3. Memory
4. Special Function Registers (SFR)
0.40
1.00
Jun., 04
Nov., 04
changed
changed
added
changed
changed
added
added
added
added
All pages Words standardized: On-chip oscillator, A/D converter and D/A converter
Overview
2, 3
• Table 1.1 and 1.2 M32C/80 Group Performance
"When using 16-bit bus" added to I/O ports
"Option" deleted from Serial I/O, I2C bus, and IEBus
"Voltage Detection Circuit" added
Value added to "Power Consumption"
"Flash Memory" added
4
• 1.3 Block Diagram Description deleted
5
• Figure 1.2 ROM/RAM Capacity deleted
• Table 1.3 M32C/85 Group Note1 deleted
11
• Table 1.5 Pin Description Note 1 added to I/O ports
Memory
23
• Chapter Description modified
• Figure 3.1 Memory Map modified
SFR
16• "X: Nothing is assigned" modified to "X: Indeterminate"
• "?: Indeterminate” modified to "X: Indeterminate"
• "Users cannot use any symbols with *" deleted
• Register names, symbols, value after RESET of addresses 001716, 001B16,
001F16, 002B16, 002F16, 004C16, and 004D16 deleted
• Value after RESET in the PM0 register revised
16
• Note 3 deleted
29
• Note 1 added to addresses 03E016 to 03EB16
A-1
M32C/80 Group Datasheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.10
Nov., 05
30All pages
1
2
3
9
Electrical Characteristics
• This capter added
Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A
Overview
• Note that the M32C/80 Group is ROMless device added
• Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed
to "Intelligent I/O Communication Function"; item "Flash Memory" deleted
• Figure 1.1 M32C/80 Group Block Diagram Notes 1 and 2 added
• Table 1.4 Pin Description Supply voltage for analog power supply input modi______
15
16
17
19
20
21
26
27, 28
28
3032
33
34
35
41
42
46
47
52
fied "-" to "VCC1"; description for CNVSS changed; supply voltage for INT interrupt input modified; note for I/O ports added
Memory
• Figure 3.1 Memory Map Disgram changed; note added
Special Function Registers (SFRs)
• Note 2 deleted
• Values after RESET in the RMAD6 and RMAD7 registers modified
• Value after RESET in the RLVL register modified
• Value after RESET in the G0RB register modified
• Values after RESET in the G0EMR, G0ERC, and G0IRF registers modified
• Value after RESET in the TCSPR register modified; note 1 added
• Register names, symbols, and value after RESET of addresses 039216 and
03AC16 deleted
• Value after RESET in the PSC register modified
Electrical Characteristics
• Ports P11 to P15 deleted
• Table 5.2 Recpmmended Operating Conditions f(BCLK) standard added
• Table 5.3 Electrical Characteristics Max. standard for ICC modified
• Table 5.4 A/D Conversion Characteristics AN00 to AN07 deleted from "INL" row
• Table 5.7 Memory Expansion Mode and Microprocessor Mode Expressions
on note 1 corrected
• Figure 5.2 VCC1=VCC2=5V Timing Diagram (1) Expression for tcyc added; note 3
corrected
• Figure 5.3 VCC1=VCC2=5V Timing Diagram (2) Expression for tcyc added; notes
1 and 2 corrected
• Table 5.22 A/D Conversion Characteristics Min. standard for VREF modified
• Table 5.25 Memory Expansion Mode and Microprocessor Mode Expressions on note 1 corrected
• Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1) Expression for tcyc added; note
3 corrected
A-2
M32C/80 Group Datasheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
53
• Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2) Expression for tcyc added;
notes 1 and 2 corrected
A-3
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
Renesas Technology Malaysia Sdn. Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0