M16C/63 Group RENESAS MCU 1. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Overview 1.1 Features The M16C/63 Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. This MCU consumes low power, and supports operating modes that allow additional power control. The MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including the multifunction timer and serial interface, the number of system components has been reduced. 1.1.1 Applications This MCU can be used in audio components, cameras, televisions, household appliances, office equipment, communication devices, mobile devices, industrial equipment, and other applications. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 1 of 113 M16C/63 Group 1.2 1. Overview Specifications The M16C/63 Group includes 100-pin and 80-pin packages. Table 1.1 to Table 1.4 list specifications. Table 1.1 Specifications for the 100-Pin Package (1/2) Item Function Description CPU Central processing unit M16C/60 Series core (multiplier: 16-bit × 16-bit 32-bit, multiply and accumulate instruction: 16-bit × 16-bit + 32-bit 32-bit) • Number of basic instructions: 91 • Minimum instruction execution time: 50.0 ns (f(BCLK) = 20 MHz, VCC1 = VCC2 = 2.7 to 5.5 V) 200.0 ns (f(BCLK) = 5 MHz, VCC1 = VCC2 = 1.8 to 5.5 V) • Operating modes: Single-chip, memory expansion, and microprocessor Memory ROM, RAM, data flash See Table 1.5 “Product List”. Voltage Detection Voltage detector • Power-on reset • 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) • 4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed on-chip oscillator (40 MHz ±10%) • Oscillation stop detection: Main clock oscillation stop/reoscillation Clock Clock generator detection function • Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16 Sub clock frequency divider circuit: Divide ratio selectable from 1 and 2 • Power saving features: Wait mode, stop mode • Real-time clock • Address space: 1 MB • External bus interface: 0 to 8 waits inserted, 4 chip select outputs, External Bus Bus memory expansion Expansion I/O Ports Programmable I/O ports Interrupts Watchdog Timer DMA DMAC memory area expansion function (expandable to 4 MB), 3 V and 5 V interfaces • Bus format: Separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20) • CMOS I/O ports: 85 (selectable pull-up resistors) • N-channel open drain ports: 3 • Interrupt vectors: 70 • External interrupt inputs: 17 (NMI, INT × 8, key input × 8) • Interrupt priority levels: 7 15-bit timer × 1 (with prescaler) Automatic reset start function selectable • 4 channels, cycle steal mode • Trigger sources: 43 • Transfer modes: 2 (single transfer, repeat transfer) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 2 of 113 M16C/63 Group 1. Overview Table 1.2 Specifications for the 100-Pin Package (2/2) Item Timers Function Description Timer A 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter two-phase pulse signal processing (two-phase encoder input) × 3 Programmable output mode × 3 Timer B 16-bit timer × 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Three-phase motor control timer functions Real-time clock PWM function • Three-phase inverter control (timer A1, timer A2, timer A4, timer B2) • On-chip dead time timer • Count: second, minute, hour, day of the week, month, year • Periodic interrupt: 0.25 s, 0.5 s • Automatic correction function 8 bits × 2 • 2 circuits • 4 wave pattern matchings (differentiate wave pattern for headers, data Remote control signal receiver 0, data 1, and special data) • 6-byte receive buffer (1 circuit only) • Operating frequency of 32 kHz Serial Interface UART0 to UART2, UART5 to UART7 Clock synchronous/asynchronous × 6 channels I2C-bus, IEBus (1), special mode 2 SIM (UART2) SI/O3, SI/O4 Clock synchronization only × 2 channels Multi-master I2C-bus Interface 1 channel CEC Functions (3) CEC transmit/receive, arbitration lost detection, ACK automatic output, operation frequency of 32 kHz A/D Converter 10-bit resolution × 26 channels, including sample and hold function Conversion time: 2.15 µs D/A Converter 8-bit resolution × 2 circuits CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant Flash Memory • Erase/write power supply voltage: 2.7 to 5.5 V • Erase/write cycles: 1,000 times (program ROM 1, program ROM 2), 10,000 times (data flash) • Program security: ROM code protect, ID code check Debug Functions On-chip debug, on-board flash rewrite, address match interrupt × 4 Operation Frequency/Supply Voltage 5 MHz/VCC1 = 1.8 to 5.5 V, VCC2 = 1.8 V to VCC1 20 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1 Current Consumption Described in 5. “Electrical Characteristics” Operating Temperature -20°C to 85°C, -40°C to 85°C (2) Package 100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A) 100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A) 100-pin LGA: PTLG0100KA-A (Previous package code: 100F0M) Notes: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. See Table 1.5 “Product List” for the operating temperature. 3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 3 of 113 M16C/63 Group Table 1.3 1. Overview Specifications for the 80-Pin Package (1/2) Item Function Description CPU Central processing unit M16C/60 Series core (multiplier: 16-bit × 16-bit 32-bit, multiply and accumulate instruction: 16-bit × 16-bit + 32-bit 32-bit) • Number of basic instructions: 91 • Minimum instruction execution time: 50.0 ns (f(BCLK) = 20 MHz, VCC1 = 2.7 to 5.5 V) 200.0 ns (f(BCLK) = 5 MHz, VCC1 = 1.8 to 5.5 V) • Operating mode: Single-chip Memory ROM, RAM, data flash See Table 1.5 “Product List”. Voltage Detection Voltage detector • Power-on reset • 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) • 4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed on-chip oscillator (40 MHz ±10%) • Oscillation stop detection: Main clock oscillation stop/reoscillation Clock Clock generator detection function • Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16 Sub clock frequency divider circuit: Divide ratio selectable from 1 and 2 • Power saving features: Wait mode, stop mode • Real-time clock External Bus Bus memory expansion Expansion I/O Ports Programmable I/O ports Interrupts Watchdog Timer DMA DMAC None • CMOS I/O ports: 68 (selectable pull-up resistors) • N-channel open drain ports: 3 • Interrupt vectors: 70 • External interrupt inputs: 14 (NMI, INT × 5, key input × 8) • Interrupt priority levels: 7 15-bit timer × 1 (with prescaler) Automatic reset start function selectable • 4 channels, cycle steal mode • Trigger sources: 43 • Transfer modes: 2 (single transfer, repeat transfer) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 4 of 113 M16C/63 Group 1. Overview Table 1.4 Specifications for the 80-Pin Package (2/2) Item Function Timer A Timer B Timers 16-bit timer × 5 Timer mode × 5 Event counter mode, one-shot timer mode, pulse width modulation (PWM) mode × 3 Event counter two-phase pulse signal processing (two-phase encoder input) × 2 Programmable output mode × 1 16-bit timer × 6 Timer mode × 6 Event counter mode, pulse period measurement mode, pulse width measurement mode × 5 Three-phase motor control None timer functions Real-time clock PWM function Remote control signal receiver Serial Interface Description • Count: second, minute, hour, day of the week, month, year • Periodic interrupt: 0.25 s, 0.5 s • Automatic correction function 8 bits × 2 • 2 circuits • 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) • 6-byte receive buffer (1 circuit only) • Operating frequency of 32 kHz Clock synchronous/asynchronous × 3 channels I2C-bus, IEBus (1), special mode 2 UART0 to UART2, UART5 Clock asynchronous × 1 channel I2C-bus, IEBus (1), SIM Clock synchronization only × 2 channels SI/O3, SI/O4 (SI/O3 is used for transmission only) Multi-master I2C-bus Interface CEC Functions (3) A/D Converter 1 channel CEC transmit/receive, arbitration lost detection, ACK automatic output, operation frequency of 32 kHz 10-bit resolution × 26 channels, including sample and hold function Conversion time: 2.15 µs D/A Converter 8-bit resolution × 2 circuits CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant Flash Memory • Erase/write power supply voltage: 2.7 to 5.5 V • Erase/write cycles: 1,000 times (program ROM 1, program ROM 2), 10,000 times (data flash) • Program security: ROM code protect, ID code check Debug Functions On-chip debug, on-board flash rewrite, address match interrupt × 4 Operation Frequency/Supply Voltage 5 MHz/VCC1 = 1.8 to 5.5 V 20 MHz/VCC1 = 2.7 to 5.5 V Current Consumption Described in 5. “Electrical Characteristics” Operating Temperature -20°C to 85°C, -40°C to 85°C (2) Package 80-pin LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A) Notes: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. See Table 1.5 “Product List” for the operating temperature. 3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 5 of 113 M16C/63 Group 1.3 1. Overview Product List Table 1.5 lists product information. Figure 1.1 shows the Part No., with Memory Size and Package, and Figure 1.2 and Figure 1.3 shows the Marking Diagram (Top View). Table 1.5 Product List As of September 2009 ROM Capacity Part No. Program ROM 1 Program ROM 2 Data flash RAM Capacity Package Code Remarks R5F363A6NFA PRQP0100JD-B R5F363A6NFB PLQP0100KB-A Operating temperature PTLG0100KA-A -20°C to 85°C PLQP0080KB-A R5F363A6NLG (D) 128 KB R5F363B6NFE 16 KB 4 KB × 2 blocks 12 KB R5F363A6DFA R5F363B6DFE PRQP0100JD-B Operating PLQP0100KB-A temperature PLQP0080KB-A -40°C to 85°C R5F363AENFA PRQP0100JD-B R5F363AENFB PLQP0100KB-A Operating temperature PTLG0100KA-A -20°C to 85°C PLQP0080KB-A R5F363A6DFB R5F363AENLG (D) R5F363BENFE 256 KB 16 KB 4 KB × 2 blocks 20 KB R5F363AEDFA PRQP0100JD-B Operating PLQP0100KB-A temperature PLQP0080KB-A -40°C to 85°C R5F363AEDFB R5F363BEDFE R5F363AKNFA R5F363AKNFB R5F363AKNLG (D) 384 KB 16 KB R5F363AKDFA 4 KB × 2 blocks 31 KB PRQP0100JD-B Operating temperature PLQP0100KB-A -40°C to 85°C R5F363AKDFB R5F363AMNFA R5F363AMNFB R5F363AMNLG (D) 512 KB 16 KB R5F363AMDFA R5F363AMDFB (D): Under development (P): Planning Note: Previous package codes are is as follows: PRQP0100JD-B: 100P6F-A PLQP0100KB-A: 100P6Q-A PTLG0100KA-A: 100F0M PLQP0080KB-A: 80P6Q-A REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 6 of 113 4 KB × 2 blocks PRQP0100JD-B Operating PLQP0100KB-A temperature PTLG0100KA-A -20°C to 85°C 31 KB PRQP0100JD-B Operating PLQP0100KB-A temperature PTLG0100KA-A -20°C to 85°C PRQP0100JD-B Operating temperature PLQP0100KB-A -40°C to 85°C M16C/63 Group 1. Overview Part No. R 5 F 3 63 A 6 D FA Package type FA: Package PRQP0100JD-B (100P6F-A) FB: Package PLQP0100KB-A (100P6Q-A) FE: Package PLQP0080KB-A (80P6Q-A) LG: Package PTLG0100KA-A (100F0M) Property code N: Operating temperature: -20°C to 85°C D: Operating temperature: -40°C to 85°C Memory capacity Program ROM 1/RAM 6: 128 KB/12 KB E: 256 KB/20 KB K: 384 KB/31 KB M: 512 KB/31 KB Number of pins A: 100 pins B: 80 pins M16C/63 Group 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part No., with Memory Size and Package PRQP0100JD-B (100P6F-A), PLQP0100KB-A (100P6Q-A), PLQP0080KB-A (80P6Q-A) M1 6 C R 5 F 3 6 3 A6 DF A XXXXXXX Type No. (See Figure 1.1 “Part No., with Memory Size and Package”) Running No. 0 to 9, A to Z (except for I, O, Q) Week code (from 01 to 54) Last one digit of year Figure 1.2 Marking Diagram (Top View) (1/2) PTLG0100KA-A (100F0M) R5F363A6 NLG XXXXXXX JAPAN Type No. (See Figure 1.1 “Part No., with Memory Size and Package”) Running No. 0 to 9, A to Z (except for I, O, Q) Country of production Week code (from 01 to 54) Last one digit of year Figure 1.3 Marking Diagram (Top View) (2/2) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 7 of 113 M16C/63 Group 1.4 1. Overview Block Diagram Figure 1.4 and Figure 1.5 show block diagrams. 8 Port P0 8 Port P1 8 8 Port P2 8 Port P3 8 Port P4 Port P5 VCC2 ports Internal peripheral functions Timer (16-bit) Outputs (timer A): 5 Inputs (timer B): 6 UART or clock synchronous serial I/O (6 channels) System clock generator XIN-XOUT XCIN-XCOUT On-chip oscillator (125 kHz) High-speed on-chip oscillator Clock synchronous serial I/O (8-bit x 2 channels) Three-phase motor control circuit DMAC (4 channels) Multi-master I2C-bus interface (1 channel) Real-time clock CRC calculator (CRC-CCITT or CRC-16) CEC function PWM function (8-bit x 2) Voltage detector Remote control signal receiver (2 circuits) Power-on reset On-chip debugger Watchdog timer (15-bit) Memory M16C/60 Series CPU core A/D converter (10-bit resolution x 26 channels) R0H R1H SB R0L R1L USP R2 R3 D/A converter (8 bit-resolution x 2 circuits) ISP 8 Port P9 A0 A1 FB Port P8 8 8 PC FLG Port P7 8 Notes: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.4 Block Diagram for the 100-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 8 of 113 RAM (2) INTB VCC1 ports Port P10 ROM (1) Port P6 8 Multiplier M16C/63 Group 1. Overview 8 8 Port P0 8 Port P2 4 Port P3 8 Port P4 Port P5 VCC1 ports Internal peripheral functions System clock generator UART or clock synchronous serial I/O (3 channels) UART (1 channel) Timer (16-bit) Outputs (timer A): 5 Inputs (timer B): 6 XIN-XOUT XCIN-XCOUT On-chip oscillator (125 kHz) High-speed on-chip oscillator Clock synchronous serial I/O (8-bit x 2 channels) DMAC (4 channels) Multi-master I2C-bus interface (1 channel) Real-time clock PWM function (8-bit x 2) CRC calculator (CRC-CCITT or CRC-16) CEC function Voltage detector Remote control signal receiver (2 circuits) Power-on reset Watchdog timer (15-bit) On-chip debugger M16C/60 Series CPU core A/D converter (10-bit resolution x 26 channels) R0H R1H SB R0L R1L ISP 8 Port P9 A0 A1 FB PC FLG Port P8 7 8 Port P7 4 Notes: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.5 RAM (2) INTB VCC1 ports Port P10 ROM (1) USP R2 R3 D/A converter (8-bit resolution x 2 circuits) Memory Block Diagram for the 80-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 9 of 113 Port P6 8 Multiplier M16C/63 Group 1.5 1. Overview Pin Assignments Figure 1.6 to Figure 1.9 show pin assignments. Table 1.6 to Table 1.9 list pin names. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_0/CTS6/RTS6/D8 P1_1/CLK6/D9 P1_2/RXD6/SCL6/D10 P1_3/TXD6/SDA6/D11 P1_4/D12 P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15 P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_0/A8 [A8/D7] VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 (See Note 3) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC2 ports M16C/63 Group PRQP0100JD-B (100P6F-A) (top view) VCC1 ports 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P4_4/CTS7/RTS7/CS0 P4_5/CLK7/CS1 P4_6/PWM0/RXD7/SCL7/CS2 P4_7/PWM1/TXD7/SDA7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/TRHO/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN/PWM1 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_1/TB1IN/PMC1/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI/SD/CEC (1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U/CTS5/RTS5 P8_0/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/SDAMM/TA0OUT (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3/KI7 P10_2/AN2/KI6 P10_1/AN1/KI5 AVSS P10_0/AN0/KI4 VREF AVCC P9_7/ADTRG/SIN4 Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals. Figure 1.6 Pin Assignment for the 100-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 10 of 113 M16C/63 Group 1. Overview 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_3/TXD6/SDA6/D11 P1_4/D12 P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15 P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_0/A8 [A8/D7] VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 (See Note 3) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC2 ports M16C/63 Group PLQP0100KB-A (100P6Q-A) (top view) VCC1 ports 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P4_2/A18 P4_3/A19 P4_4/CTS7/RTS7/CS0 P4_5/CLK7/CS1 P4_6/PWM0/RXD7/SCL7/CS2 P4_7/PWM1/TXD7/SDA7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/TRHO/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/SDAMM/TA0OUT (1) P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V RESET XOUT VSS XIN VCC1 P8_5/NMI/SD/CEC (1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U/CTS5/RTS5 P8_0/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P9_4/DA1/TB4IN/PWM1 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_1/TB1IN/PMC1/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P1_2/RXD6/SCL6/D10 P1_1/CLK6/D9 P1_0/CTS6/RTS6/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3/KI7 P10_2/AN2/KI6 P10_1/AN1/KI5 AVSS P10_0/AN0/KI4 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals. Figure 1.7 Pin Assignment for the 100-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 11 of 113 M16C/63 Group 1. Overview M16C/63 Group PTLG0100KA-A (100F0M) (top view) VCC1 ports VCC2 ports 10 9 8 7 6 5 4 3 2 1 K P4_2 P4_3 P5_0 P5_1 P5_4 P6_0 P6_3 P6_6 P7_1 (1) P7_2 K J P4_1 P4_0 P4_6 P5_2 P5_5 P6_1 P6_4 P7_0 (1) P7_3 P7_4 J H P3_6 P3_7 P4_5 P5_3 P5_6 P6_2 P6_7 P7_5 P7_7 P8_0 H G P3_2 P3_3 P4_4 P4_7 P5_7 P6_5 P7_6 P8_3 P8_5 (1) P8_2 G F P3_0 VCC2 P3_1 P3_4 P3_5 P8_4 P8_1 VSS XIN VCC1 F E P2_6 P2_7 VSS P2_5 P1_6 P0_0 P9_3 P8_6 RESET XOUT E D P2_2 P2_1 P2_3 P2_4 P0_5 P10_7 P10_0 P9_1 CNVSS P8_7 D C P2_0 P1_7 P1_1 P1_0 P0_1 P10_3 AVSS P9_7 P9_0 BYTE C B P1_4 P1_5 P0_6 P0_4 P0_2 P10_5 P10_2 AVCC P9_6 P9_2 B A P1_3 P1_2 P0_7 P0_3 P10_6 P10_4 P10_1 VREF P9_5 P9_4 A 10 9 8 7 6 5 4 3 2 1 VCC2 ports VCC1 ports Notes: 1. N-channel open drain output. 2. Check the position of Pin A1 by referring to appendix 1, Package Dimensions. Figure 1.8 Pin Assignment for the 100-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 12 of 113 (Note 2) M16C/63 Group Table 1.6 1. Overview Pin Names for the 100-Pin Package (1/2) Pin No. I/O Pin for Peripheral Function Control Pin Port FA FB LG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B2 A2 A1 E4 B1 D3 C2 C1 D2 D1 E3 E2 E1 F3 F2 F1 G2 F5 G3 G1 F4 H1 H2 G4 H3 J1 J2 K1 K2 J3 H4 K3 G5 34 32 J4 P6_4 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 K4 H5 J5 K5 G6 H6 J6 K6 H7 J7 K7 K8 G7 J8 H8 G8 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 Interrupt P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 Serial interface SOUT4 CLK4 TB4IN/PWM1 TB3IN/PWM0 TB2IN/PMC0 TB1IN/PMC1 TB0IN A/D converter, D/A converter Bus Control Pin ANEX1 ANEX0 DA1 DA0 SOUT3 SIN3 CLK3 P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 CLKOUT Timer NMI INT2 INT1 INT0 REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 13 of 113 SD ZP CEC TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS5/RTS5 RXD5/SCL5 CLK5 TXD5/SDA5 TRHO PWM1 PWM0 CTS2/RTS2 CLK2 RXD2/SCL2/SCLMM TXD2/SDA2/SDAMM TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/ CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 TXD7/SDA7 RXD7/SCL7 CLK7 CTS7/RTS7 RDY ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 M16C/63 Group Table 1.7 1. Overview Pin Names for the 100-Pin Package (2/2) Pin No. I/O Pin for Peripheral Function FA FB LG 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 K9 K10 J10 J9 H9 H10 F6 F7 G9 G10 F8 F9 F10 E8 E9 E10 E7 D7 D8 D10 D9 C10 C9 E6 B9 B10 A10 A9 C8 C7 A8 B8 D6 B7 A7 B6 C6 E5 D5 A6 B5 A5 C5 B4 A4 C4 D4 A3 B3 C3 Control Pin Port Interrupt Timer Serial interface A/D converter, D/A converter Bus Control Pin P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 P3_0 A8, [A8/D7] VCC2 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 INT7 INT6 INT5 INT4 INT3 IDU IDW IDV TXD6/SDA6 RXD6/SCL6 CLK6 CTS6/RTS6 KI3 KI2 KI1 KI0 KI7 KI6 KI5 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 KI4 AN0 AVSS P10_0 VREF AVCC P9_7 REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 14 of 113 SIN4 ADTRG A7, [A7/D7], [A7/D6] A6, [A6/D6], [A6/D5] A5, [A5/D5], [A5/D4] A4, [A4/D4], [A4/D3] A3, [A3/D3], [A3/D2] A2, [A2/D2], [A2/D1] A1, [A1/D1], [A1/D0] A0, [A0/D0], A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P0_7/AN0_7 P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_3/AN2_3 P2_4/INT6/AN2_4 P2_5/INT7/AN2_5 P2_6/AN2_6 P2_7/AN2_7 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 P4_2 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M16C/63 Group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P9_5/ANEX0/CLK4 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_0/TB0IN/CLK3 CNVSS(BYTE) P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI/CEC (1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/CTS5/RTS5 P8_0/TA4OUT/RXD5/SCL5 P7_7/TA3IN/CLK5 PLQP0080KB-A (80P6Q-A) (top view) P9_4/DA1/TB4IN/PWM1 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3/KI7 P10_2/AN2/KI6 P10_1/AN1/KI5 AVSS P10_0/AN0/KI4 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 59 1. Overview 60 M16C/63 Group 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P4_3 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/TRHO/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT/SDAMM (1) P7_1/RXD2/SCL2/TA0IN/TB5IN/SCLMM (1) P7_6/TA3OUT/TXD5/SDA5 Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. Figure 1.9 Pin Assignment for the 80-Pin Package REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 15 of 113 M16C/63 Group Table 1.8 1. Overview Pin Names for the 80-Pin Package (1/2) I/O Pin for Peripheral Function Pin No. Control Pin Port Interrupt Timer Serial interface 1 P9_5 2 P9_4 TB4IN/PWM1 3 P9_3 TB3IN/PWM0 4 P9_2 TB2IN/PMC0 SOUT3 5 P9_0 TB0IN CLK3 6 CNVSS 7 XCIN P8_7 8 XCOUT P8_6 9 10 RESET XOUT 11 VSS 12 XIN 13 VCC1 CLK4 DA1 DA0 14 P8_5 NMI 15 P8_4 INT2 16 P8_3 INT1 17 P8_2 INT0 18 P8_1 TA4IN 19 P8_0 TA4OUT CTS5/RTS5 RXD5/SCL5 20 P7_7 TA3IN CLK5 21 P7_6 TA3OUT TXD5/SDA5 22 P7_1 TA0IN/TB5IN RXD2/SCL2/SCLMM TA0OUT TXD2/SDA2/SDAMM CEC ZP 23 P7_0 24 P6_7 TXD1/SDA1 25 P6_6 RXD1/SCL1 26 P6_5 CLK1 27 P6_4 28 P6_3 CTS1/RTS1/CTS0/ CLKS1 TXD0/SDA0 29 P6_2 RXD0/SCL0 30 P6_1 CLK0 31 32 P6_0 CLKOUT P5_7 33 P5_6 34 P5_5 35 P5_4 36 P5_3 37 P5_2 38 P5_1 39 P5_0 40 P4_3 REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 16 of 113 TRHO A/D converter, D/A converter ANEX0 CTS0/RTS0 M16C/63 Group Table 1.9 1. Overview Pin Names for the 80-Pin Package (2/2) I/O Pin for Peripheral Function Pin No. Control Pin Port Interrupt Timer Serial interface A/D converter, D/A converter 41 P4_2 42 P4_1 43 P4_0 44 P3_7 45 P3_6 46 P3_5 47 P3_4 48 P3_3 49 P3_2 50 P3_1 51 P3_0 52 P2_7 AN2_7 53 P2_6 AN2_6 54 P2_5 INT7 AN2_5 55 P2_4 INT6 AN2_4 56 P2_3 AN2_3 57 P2_2 AN2_2 58 P2_1 AN2_1 59 P2_0 AN2_0 60 P0_7 AN0_7 61 P0_6 AN0_6 62 P0_5 AN0_5 63 P0_4 AN0_4 64 P0_3 AN0_3 65 P0_2 AN0_2 66 P0_1 AN0_1 67 P0_0 68 P10_7 KI3 AN7 69 P10_6 KI2 AN6 70 P10_5 KI1 AN5 71 P10_4 KI0 AN4 72 P10_3 KI7 AN3 73 P10_2 KI6 AN2 P10_1 KI5 AN1 P10_0 KI4 AN0 74 75 AN0_0 AVSS 76 77 VREF 78 AVCC 79 P9_7 SIN4 80 P9_6 SOUT4 REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 17 of 113 ADTRG ANEX1 M16C/63 Group 1.6 1. Overview Pin Functions Table 1.10 Pin Functions for the 100-Pin Package (1/3) Signal Name Pin Name I/O Power Supply Description Power supply input VCC1, VCC2, VSS I - Apply 1.8 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2) and 0 V to the VSS pin. Analog power supply input AVCC, AVSS I VCC1 This is the power supply for the A/D and D/A converters. Connect the AVCC pin to VCC1, and connect the AVSS pin to VSS. RESET I VCC1 Driving this pin low resets the MCU. VCC1 Input pin to switch processor modes. After a reset, to start operating in single-chip mode, connect the CNVSS pin to VSS via a resistor. To start operating in microprocessor mode, connect the pin to VCC1. Reset input CNVSS External data bus width select input CNVSS I BYTE I VCC1 Input pin to select the data bus of the external area. The data bus is 16 bits when it is low, and 8 bits when it is high. This pin must be fixed either high or low. Connect the BYTE pin to VSS in single-chip mode. D0 to D7 I/O VCC2 Inputs or outputs data (D0 to D7) while accessing an external area with a separate bus. D8 to D15 I/O VCC2 Inputs or outputs data (D8 to D15) while accessing an external area with a 16-bit separate bus. A0 to A19 O VCC2 Outputs address bits A0 to A19. A0/D0 to A7/D7 I/O VCC2 Inputs or outputs data (D0 to D7) and outputs address bits (A0 to A7) by timesharing, while accessing an external area with an 8-bit multiplexed bus. A1/D0 to A8/D7 I/O VCC2 Inputs or outputs data (D0 to D7) and outputs address bits (A1 to A8) by timesharing, while accessing an external area with a 16-bit multiplexed bus. CS0 to CS3 O VCC2 Outputs chip-select signals CS0 to CS3 to specify an external area. WRL/WR WRH/BHE RD O VCC2 Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and WRH can be switched with BHE and WR. • WRL, WRH, and RD selected If the external data bus is 16 bits, data is written to an even address in an external area when WRL is driven low. Data is written to an odd address when WRH is driven low. Data is read when RD is driven low. • WR, BHE, and RD selected Data is written to an external area when WR is driven low. Data in an external area is read when RD is driven low. An odd address is accessed when BHE is driven low. Select WR, BHE, and RD when using an 8-bit external data bus. ALE O VCC2 Outputs ALE signal to latch address. HOLD I VCC2 The MCU is placed in a hold state while the HOLD pin is driven low. HLDA O VCC2 In a hold state, HLDA outputs a low-level signal. RDY I VCC2 The MCU bus is placed in a wait state while the RDY pin is driven low. Bus control pins Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration allows VCC2 to interface at a different voltage than VCC1. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 18 of 113 M16C/63 Group Table 1.11 1. Overview Pin Functions for the 100-Pin Package (2/3) Signal Name Main clock input Pin Name I/O Power Supply Description I/O for the main clock oscillator. Connect a ceramic resonator or crystal between pins XIN and XOUT. (1) Input an external clock to XIN pin and leave XOUT pin open. XIN I VCC1 Main clock output XOUT O VCC1 Sub clock input XCIN I VCC1 XCOUT O VCC1 I/O for a sub clock oscillator. Connect a crystal between XCIN pin and XCOUT pin. (1) Input an external clock to XCIN pin and leave XCOUT pin open. BCLK output BCLK O VCC2 Outputs the BCLK signal. Clock output CLKOUT O VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32. INT0 to INT2 I VCC1 INT3 to INT7 I VCC2 NMI interrupt input NMI I VCC1 Input for the NMI interrupt. Key input interrupt input KI0 to KI7 I VCC1 Input for the key input interrupt. TA0OUT to TA4OUT I/O VCC1 I/O for timers A0 to A4 (TA0OUT is N-channel open drain output). TA0IN to TA4IN I VCC1 Input for timers A0 to A4. ZP I VCC1 Input for Z-phase. TB0IN to TB5IN I VCC1 Input for timers B0 to B5. U, U, V, V, W, W O VCC1 Output for the three-phase motor control timer. SD I VCC1 Forced cutoff input. IDU, IDV, IDW I VCC2 Input for the position data. TRHO O VCC1 Output for the real-time clock. PWM output PWM0, PWM1 O Remote control signal receiver input PMC0, PMC1 I VCC1 CTS0 to CTS2, CTS5 I VCC1 CTS6, CTS7 I VCC2 RTS0 to RTS2, RTS5 O VCC1 RTS6, RTS7 O VCC2 CLK0 to CLK2, CLK5 I/O VCC1 CLK6, CLK7 I/O VCC2 RXD0 to RXD2, RXD5 I VCC1 RXD6, RXD7 I VCC2 TXD0 to TXD2, TXD5 O VCC1 TXD6, TXD7 O VCC2 CLKS1 O VCC1 Sub clock output INT interrupt input Timer A Timer B Three-phase motor control timer Real-time clock output Serial interface UART0 to UART2, UART5 to UART7 Input for the INT interrupt. VCC1, VCC2 PWM output. Input for the remote control signal receiver. Input pins to control data transmission. Output pins to control data reception. Transmit/receive clock I/O. Serial data input. Serial data output. (2) Output for the transmit/receive clock multiple-pin output function. Notes: 1. Contact the oscillator manufacturer regarding the oscillation characteristics. 2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi, SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins (i = 0, 1, 5 to 7). REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 19 of 113 M16C/63 Group Table 1.12 Signal Name UART0 to UART2, UART5 to UART7 I2C mode Serial interface SI/O3, SI/O4 1. Overview Pin Functions for the 100-Pin Package (3/3) Pin Name I/O Power Supply SDA0 to SDA2, SDA5 I/O VCC1 SDA6, SDA7 I/O VCC2 SCL0 to SCL2, SCL5 I/O VCC1 SCL6, SCL7 I/O VCC2 CLK3, CLK4 I/O VCC1 Description Serial data I/O for I2C mode. Transmit/receive clock I/O for I2C mode. Transmit/receive clock I/O. SIN3, SIN4 I VCC1 Serial data input. SOUT3, SOUT4 O VCC1 Serial data output. SDAMM I/O VCC1 Serial data I/O (N-channel open drain output). SCLMM I/O VCC1 Transmit/receive clock I/O (N-channel open drain output). CEC I/O CEC I/O VCC1 CEC I/O (N-channel open drain output). Reference voltage input VREF I VCC1 Reference voltage input for the A/D and D/A converters. AN0 to AN7 I VCC1 AN0_0 to AN0_7 AN2_0 to AN2_7 I VCC2 ADTRG I VCC1 External A/D trigger input. ANEX0, ANEX1 I VCC1 Extended analog input for the A/D converter. DA0, DA1 O VCC1 Output for the D/A converter. VCC2 8-bit CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. A pull-up resistor may be enabled or disabled for input ports in 4-bit units. VCC1 8-bit I/O ports having equivalent functions to P0. However, P7_0, P7_1, and P8_5 are N-channel open drain output ports. No pull-up resistor is provided. P8_5 is an input port for verifying the NMI pin level and shares a pin with NMI. Multi-master I2C-bus interface A/D converter D/A converter I/O ports P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 I/O I/O REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 20 of 113 Analog input for the A/D converter. M16C/63 Group Table 1.13 1. Overview Pin Functions for the 80-Pin Package (1/2) Signal Name Pin Name I/O Power Supply Power supply input VCC1, VSS I - Apply 1.8 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. Analog power supply input AVCC, AVSS I VCC1 This is the power supply for the A/D and D/A converters. Connect the AVCC pin to VCC1, and connect the AVSS pin to VSS. Reset input RESET I VCC1 Driving this pin low resets the MCU. CNVSS CNVSS I VCC1 Input pin to switch processor modes. After a reset, to start operating in single-chip mode, connect the CNVSS pin to VSS via a resistor. XIN I VCC1 Main clock output XOUT O VCC1 Sub clock input XCIN I VCC1 Sub clock output XCOUT O VCC1 I/O pins for a sub clock oscillator. Connect a crystal between XCIN pin and XCOUT pin. (1) Input an external clock to XCIN pin and leave XCOUT pin open. Clock output CLKOUT O VCC1 Outputs a clock with the same frequency as fC, f1, f8, or f32. INT0 to INT2 I VCC1 INT6, INT7 I VCC1 Input for the INT interrupt. NMI interrupt input NMI I VCC1 Input for the NMI interrupt. Key input interrupt input KI0 to KI7 I VCC1 Input for the key input interrupt. TA0OUT, TA3OUT, TA4OUT I/O VCC1 I/O for timers A0, A3, and A4 (TA0OUT is N-channel open drain output). TA0IN, TA3IN, TA4IN I VCC1 Input for timers A0, A3, and A4. ZP I VCC1 Input for Z-phase. TB0IN, TB2IN to TB5IN I VCC1 Input for timers B0, and B2 to B5. Real-time clock output TRHO O VCC1 Output for the real-time clock. PWM output PWM0, PWM1 O VCC1 PWM output. Remote control signal receiver input PMC0 I VCC1 Input for the remote control signal receiver. Main clock input INT interrupt input Timer A Timer B Description I/O pins for the main clock oscillator. Connect a ceramic resonator or crystal between pins XIN and XOUT. (1) Input an external clock to XIN pin and leave XOUT pin open. Note: 1. Contact the oscillator manufacturer regarding oscillation characteristics. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 21 of 113 M16C/63 Group Table 1.14 1. Overview Pin Functions for the 80-Pin Package (2/2) Signal Name Serial interface UART0 to UART2, UART5 UART0 to UART2, UART5 I2C mode Serial interface SI/O3, SI/O4 Pin Name I/O Power Supply CTS0, CTS1, CTS5 I VCC1 Input pins to control data transmission RTS0, RTS1, RTS5 O VCC1 Output pins to control data reception CLK0, CLK1, CLK5 I/O VCC1 Transmit/receive clock I/O. RXD0 to RXD2, RXD5 I VCC1 Serial data input. TXD0 to TXD2, TXD5 O VCC1 Serial data output. (1) CLKS1 O VCC1 Output for the transmit/receive clock multiple-pin output function. SDA0 to SDA2, SDA5 I/O VCC1 Serial data I/O for I2C mode. SCL0 to SCL2, SCL5 I/O VCC1 Transmit/receive clock I/O for I2C mode. CLK3, CLK4 I/O VCC1 Transmit/receive clock I/O. SIN4 I VCC1 Serial data input. SOUT3, SOUT4 O VCC1 Serial data output. Description SDAMM I/O VCC1 Serial data I/O (N-channel open drain output). SCLMM I/O VCC1 Transmit/receive clock I/O (N-channel open drain output). CEC I/O CEC I/O VCC1 CEC I/O (N-channel open drain output). Reference voltage input VREF I VCC1 Reference voltage input for the A/D and D/A converters. AN0 to AN7 I VCC1 AN0_0 to AN0_7 AN2_0 to AN2_7 I VCC1 Multi-master I2C-bus interface A/D converter D/A converter I/O ports Analog input for the A/D converter. ADTRG I VCC1 Input for an external A/D trigger. ANEX0, ANEX1 I VCC1 Extended analog input for the A/D converter. DA0, DA1 O VCC1 Output for the D/A converter. P0_0 to P0_7 P2_0 to P2_7 P3_0 to P3_7 P5_0 to P5_7 P6_0 to P6_7 P8_0 to P8_7 P10_0 to P10_7 I/O VCC1 8-bit CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. A pull-up resistor may be enabled or disabled for input ports in 4-bit units. P8_5 is an N-channel open drain output port. No pull-up resistor is provided. P8_5 is an input port for verifying the NMI pin level and shares a pin with NMI. P4_0 to P4_3 P7_0, P7_1 P7_6, P7_7 P9_0, P9_2 to P9_7 I/O VCC1 I/O ports having equivalent functions to P0. However, P7_0 and P7_1 are N-channel open drain output ports. No pull-up resistor is provided. Note: 1. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5), SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 22 of 113 M16C/63 Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a register bank, and there are two register banks. b31 b15 b8 b7 b0 R2 R0H (high-order bits of R0) R0L (low-order bits of R0) R3 R1H (high-order bits of R1) R1L (low-order bits of R1) Data registers (1) R2 R3 A0 Address registers (1) A1 FB b19 Frame base registers (1) b15 b0 INTBH INTBL Interrupt table register INTBH is the 4 high-order bits of the INTB register and INTBL is the 16 low-order bits. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL Flag register b7 U b0 I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: 1. These registers compose a register bank. There are two register banks. Figure 2.1 2.1 CPU Registers Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data registers. R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers R2R0 and R3R1, respectively. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 23 of 113 M16C/63 Group 2.2 2. Central Processing Unit (CPU) Address Registers (A0 and A1) A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register that is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.5 Program Counter (PC) The PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register used for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register that indicates the CPU state. 2.8.1 Carry Flag (C Flag) The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z Flag) The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0. 2.8.4 Sign Flag (S Flag) The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O Flag) The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0. 2.8.7 Interrupt Enable Flag (I Flag) The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0 when an interrupt request is accepted. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 24 of 113 M16C/63 Group 2.8.8 2. Central Processing Unit (CPU) Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software interrupt number 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7. If a requested interrupt has higher priority than IPL, the interrupt request is enabled. 2.8.10 Reserved Areas Only set these bits to 0. The read value is undefined. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 25 of 113 M16C/63 Group 3. 3.1 3. Address Space Address Space Address Space The M16C/63 Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to 4 MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external areas from bank 0 to bank 7. Figure 3.1 shows the Address Space. Areas that can be accessed vary depending on processor mode and the status of each control bit. Memory expansion mode 00000h SFR 00400h Internal RAM Internal RAM is allocated from address 00400h higher. Reserved area 04000h 0D000h 0D800h 1 MB address space External area SFR External area 0E000h Internal ROM (data flash) 10000h Internal ROM (program ROM 2) 14000h 27000h In 4-MB mode When data flash is enabled Bank 7 When program ROM 2 is enabled Bank 6 Bank 5 External area Bank 4 Bank 3 Bank 2 Reserved area 28000h Bank 1 40000h External area Bank 0 BFFFFh D0000h 512 KB × 8 Reserved area Internal ROM (program ROM 1) Program ROM 1 is allocated from address FFFFFh lower. FFFFFh Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: - The PM13 bit in the PM1 register is 0 (addresses 04000h to 0CFFFh and 80000h to CFFFFh are used as external areas) Figure 3.1 Address Space REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 26 of 113 M16C/63 Group 3.2 3. Address Space Memory Map Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved. Do not access these areas. Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from 00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when subroutines are called or when an interrupt request is accepted. The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1, and program ROM 2. The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but can also store programs. Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh and lower, with the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh. The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details. The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh. The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table for interrupts. Figure 3.2 shows the Memory Map. 00000h Internal RAM 00400h SFR Internal RAM XXXXXh Size Address XXXXXh 12 KB 033FFh 20 KB 053FFh 0D000h 31 KB 07FFFh 0D800h Reserved area 0E000h 10000h 14000h 27000h SFR External area Internal ROM (data flash) Internal ROM (program ROM 2) 13000h 13FF0h 13FFFh On-chip debugger monitor area User boot code area External area Reserved area 28000h Relocatable vector table External area Program ROM 1 Size Address YYYYYh 128 KB E0000h 256 KB C0000h 384 KB A0000h 512 KB 80000h 256 bytes beginning with the start address set in the INTB register 80000h Reserved area Special page vector table FFFD8h YYYYYh Reserved area Internal ROM (program ROM 1) FFFFFh FFE00h FFFDCh Fixed vector table Address for ID code stored FFFFFh OFS1 address Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: - Memory expansion mode - The PM10 bit in the PM1 register is 1 (addresses 0E000h to 0FFFFh are used as data flash) - The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled) - The PM13 bit in the PM1 register is 1 (all areas in internal RAM, and the program ROM 1 area from 80000h are usable) Figure 3.2 Memory Map REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 27 of 113 M16C/63 Group 3.3 3. Address Space Accessible Area in Each Mode Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure 3.3 shows the Accessible Area in Each Mode. In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed. In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed. Address space is expandable to 4 MB with the memory area expansion function. In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is expandable to 4 MB with the memory area expansion function. Allocate ROM to the fixed vector table from FFFDCh to FFFFFh. Single-Chip Mode 00000h SFR 00400h Memory Expansion Mode 00000h SFR 00000h 00400h 00400h Internal RAM 0D800h 0E000h 10000h SFR Reserved area Internal ROM (data flash) Internal ROM (program ROM 2) 14000h Reserved area 0D000h 0D800h 0E000h 10000h 14000h SFR External area SFR Internal RAM Internal RAM Reserved area 0D000h Microprocessor Mode Reserved area 0D000h SFR 0D800h Internal ROM (data flash) Internal ROM (program ROM 2) External area External area 27000h 27000h Reserved area Reserved area 28000h 28000h External area Reserved area 80000h Reserved area Internal ROM (program ROM 1) FFFFFh External area Internal ROM (program ROM 1) FFFFFh FFFFFh Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: Single-chip mode and memory expansion mode - The PM10 bit in the PM1 register is 1 (addresses 0E000h to 0FFFFh are used as data flash) - The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled) - The PM13 bit in the PM1 register is 1 (all areas in internal RAM, and the program ROM 1 area from 80000h are usable) Microprocessor mode - The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area) - The PRG2C0 bit is 1 (program ROM 2 disabled) Figure 3.3 Accessible Area in Each Mode REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 28 of 113 M16C/63 Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) 4.1 SFRs An SFR is a control register for a peripheral function. Table 4.1 to Table 4.15 list SFR information. Table 4.1 SFR Information (1/16) (1) Address Register Symbol Reset Value 0000h 0001h 0002h 0003h PM1 CM0 CM1 CSR EWR PRCR DBR 0000 0000b (CNVSS pin is low) 0000 0011b (CNVSS pin is high) (2) 0000 1000b 0100 1000b 0010 0000b 01h XXXX XX00b 00h 00h CM2 0X00 0010b (3) PRG2C EWC PCLKR SCM0 XXXX XX00b 00h 0000 0011b XXXX X000b CPSRF PCLKSTP1 0XXX XXXXb X000 0000b Reset Source Determine Register RSTFR XX00 001Xb (hardware reset) (4) Voltage Detector 2 Flag Register VCR1 0004h Processor Mode Register 0 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register External Area Recovery Cycle Control Register Protect Register Data Bank Register 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h Oscillation Stop Detection Register 0019h Program 2 Area Control Register External Area Wait Control Expansion Register Peripheral Clock Select Register Sub Clock Division Control Register Clock Prescaler Reset Flag Peripheral Clock Stop Register PM0 0000 1000b (2) 001Ah Voltage Detector Operation Enable Register 001Bh 001Ch 001Dh 001Eh 001Fh Chip Select Expansion Control Register CSE 000X 0000b (2, 5) 001X 0000b (2, 6) 00h Processor Mode Register 2 PM2 XX00 0X01b Notes: 1. 2. 3. 4. 5. 6. VCR2 X: Undefined The blank areas are reserved. No access is allowed. Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following bits and registers: the VCR1 register, the VCR2 register, and bits PM01 and PM00 in the PM0 register. Oscillator stop detect reset does not affect bits CM20, CM21, and CM27. The state of bits in the RSTFR register depends on the reset type. This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset. This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 29 of 113 M16C/63 Group Table 4.2 4. Special Function Registers (SFRs) SFR Information (2/16) (1) Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h Register Symbol Reset Value 40 MHz On-Chip Oscillator Control Register 0 FRA0 XXXX XX00b Voltage Monitor Function Select Register VWCE 00h 0027h 0028h 0029h Voltage Detector 1 Level Select Register VD1LS 0000 1010b (5) 002Ah Voltage Monitor 0 Control Register VW0C 1100 XX10b (2, 3) 1100 XX11b (2, 4) 002Bh Voltage Monitor 1 Control Register VW1C 1000 1X10b (6) 1000 XX10b (2, 7) 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Voltage Monitor 2 Control Register VW2C 1000 0X10b (2) 0042h INT7 Interrupt Control Register INT7IC XX00 X000b 0043h INT6 Interrupt Control Register INT6IC XX00 X000b 0044h INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register INT3IC XX00 X000b TB5IC TB4IC U1BCNIC TB3IC U0BCNIC XXXX X000b 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh Notes: 1. 2. 3. 4. 5. 6. 7. XXXX X000b XXXX X000b SI/O4 Interrupt Control Register INT5 Interrupt Control Register S4IC INT5IC XX00 X000b SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register S3IC INT4IC XX00 X000b BCNIC DM0IC DM1IC KUPIC ADIC S2TIC XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XXXX X000b X: Undefined The blank areas are reserved. No access is allowed. Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following registers or bit: the VW0C register, the VW1C2 bit in the VW1C register, and bits VW2C2 and VW2C3 in the VW2C register. This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0 during hardware reset. This is the reset value after hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, or voltage monitor 2 reset (The value does not change after oscillator detect reset, watchdog timer reset, or software reset.) This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset This is the reset value after voltage monitor 1 reset, voltage monitor 2 reset, oscillator stop detect reset, watchdog timer reset, or software reset REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 30 of 113 M16C/63 Group Table 4.3 4. Special Function Registers (SFRs) SFR Information (3/16) (1) Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register Reset Value S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 005Dh INT0 Interrupt Control Register INT0IC XX00 X000b 005Eh INT1 Interrupt Control Register INT1IC XX00 X000b 005Fh INT2 Interrupt Control Register INT2IC XX00 X000b DM2IC DM3IC U5BCNIC CEC1IC S5TIC CEC2IC S5RIC U6BCNIC RTCTIC S6TIC RTCCIC S6RIC U7BCNIC PMC0IC S7TIC PMC1IC S7RIC XXXX X000b XXXX X000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h DMA2 Interrupt Control Register DMA3 Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register CEC1 Interrupt Control Register UART5 Transmit Interrupt Control Register CEC2 Interrupt Control Register UART5 Receive Interrupt Control Register UART6 Bus Collision Detection Interrupt Control Register Real-Time Clock Periodic Interrupt Control Register UART6 Transmit Interrupt Control Register Real-Time Clock Alarm Interrupt Control Register UART6 Receive Interrupt Control Register UART7 Bus Collision Detection Interrupt Control Register Remote Control Signal Receiver 0 Interrupt Control Register UART7 Transmit Interrupt Control Register Remote Control Signal Receiver 1 Interrupt Control Register UART7 Receive Interrupt Control Register 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh I2C-bus Interface Interrupt Control Register 007Ch SCL/SDA Interrupt Control Register 007Dh 007Eh 007Fh 0080h to 017Fh Note: 1. Symbol IICIC SCLDAIC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 31 of 113 M16C/63 Group Table 4.4 4. Special Function Registers (SFRs) SFR Information (4/16) (1) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh Note: 1. Symbol Reset Value DMA0 Source Pointer Register SAR0 XXh XXh 0Xh DMA0 Destination Pointer DAR0 XXh XXh 0Xh DMA0 Transfer Counter TCR0 XXh XXh DMA0 Control Register DM0CON 0000 0X00b DMA1 Source Pointer SAR1 XXh XXh 0Xh DMA1 Destination Pointer DAR1 XXh XXh 0Xh DMA1 Transfer Counter TCR1 XXh XXh DMA1 Control Register DM1CON 0000 0X00b DMA2 Source Pointer SAR2 XXh XXh 0Xh DMA2 Destination Pointer DAR2 XXh XXh 0Xh DMA2 Transfer Counter TCR2 XXh XXh DMA2 Control Register DM2CON 0000 0X00b X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 32 of 113 M16C/63 Group Table 4.5 4. Special Function Registers (SFRs) SFR Information (5/16) (1) Address 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh Note: 1. Symbol Reset Value DMA3 Source Pointer Register SAR3 XXh XXh 0Xh DMA3 Destination Pointer DAR3 XXh XXh 0Xh DMA3 Transfer Counter TCR3 XXh XXh DMA3 Control Register DM3CON 0000 0X00b Timer B0-1 Register TB01 Timer B1-1 Register TB11 Timer B2-1 Register TB21 PPWFS1 XXh XXh XXh XXh XXh XXh XXXX X000b TBCS0 TBCS1 00h X0h TCKDIVC0 0000 X000b TACS0 TACS1 TACS2 00h 00h X0h PWMFS TAPOFS 0XX0 X00Xb XXX0 0000b Timer A Output Waveform Change Enable Register TAOW XXX0 X00Xb Three-Phase Protect Control Register TPRC 00h Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer AB Division Control Register 0 Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 16-Bit Pulse Width Modulation Mode Function Select Register Timer A Waveform Output Function Select Register X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 33 of 113 M16C/63 Group Table 4.6 4. Special Function Registers (SFRs) SFR Information (6/16) (1) Address 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh Note: 1. Symbol Reset Value Timer B3-1 Register Register TB31 Timer B4-1 Register TB41 Timer B5-1 Register TB51 PPWFS2 XXh XXh XXh XXh XXh XXh XXXX X000b Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 TBCS2 TBCS3 00h X0h PMC0 Function Select Register 0 PMC0 Function Select Register 1 PMC0 Function Select Register 2 PMC0 Function Select Register 3 PMC0 Status Register PMC0 Interrupt Source Select Register PMC0 Compare Control Register PMC0 Compare Data Register PMC1 Function Select Register 0 PMC1 Function Select Register 1 PMC1 Function Select Register 2 PMC1 Function Select Register 3 PMC1 Status Register PMC1 Interrupt Source Select Register PMC0CON0 PMC0CON1 PMC0CON2 PMC0CON3 PMC0STS PMC0INT PMC0CPC PMC0CPD PMC1CON0 PMC1CON1 PMC1CON2 PMC1CON3 PMC1STS PMC1INT 00h 00XX 0000b 0000 00X0b 00h 00h 00h XXX0 X000b 00h XXX0 X000b XXXX 0X00b 0000 00X0b 00h X000 X00Xb X000 X00Xb IFSR3A IFSR2A IFSR 00h 00h 00h AIER AIER2 XXXX XX00b XXXX XX00b Pulse Period/Pulse Width Measurement Mode Function Select Register 2 Interrupt Source Select Register 3 Interrupt Source Select Register 2 Interrupt Source Select Register Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 34 of 113 M16C/63 Group Table 4.7 4. Special Function Registers (SFRs) SFR Information (7/16) (1) Address 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh Symbol Reset Value Address Match Interrupt Register 0 Register RMAD0 00h 00h X0h Address Match Interrupt Register 1 RMAD1 00h 00h X0h Address Match Interrupt Register 2 RMAD2 00h 00h X0h Address Match Interrupt Register 3 RMAD3 00h 00h X0h 0220h Flash Memory Control Register 0 FMR0 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Flash Memory Control Register 1 Flash Memory Control Register 2 Flash Memory Control Register 3 FMR1 FMR2 FMR3 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) 00X0 XX0Xb XXXX 0000b XXXX 0000b Flash Memory Control Register 6 FMR6 XX0X XX00b Note: 1. X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 35 of 113 M16C/63 Group Table 4.8 4. Special Function Registers (SFRs) SFR Information (8/16) (1) Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh Note: 1. Register UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register Symbol Reset Value U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0C0 U0C1 U0RB UART Transmit/Receive Control Register 2 UCON 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh X000 0000b UCLKSEL0 X0h U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh UART Clock Select Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U1C0 U1C1 U1RB U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 36 of 113 M16C/63 Group Table 4.9 4. Special Function Registers (SFRs) SFR Information (9/16) (1) Address 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh Note: 1. Symbol Reset Value SI/O3 Transmit/Receive Register Register S3TRR XXh SI/O3 Control Register SI/O3 Bit Rate Register SI/O4 Transmit/Receive Register S3C S3BRG S4TRR 0100 0000b XXh XXh SI/O4 Control Register SI/O4 Bit Rate Register SI/O3, 4 Control Register 2 S4C S4BRG S34C2 0100 0000b XXh 00XX X0X0b U5SMR4 U5SMR3 U5SMR2 U5SMR U5MR U5BRG U5TB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh UART5 Special Mode Register 4 UART5 Special Mode Register 3 UART5 Special Mode Register 2 UART5 Special Mode Register UART5 Transmit/Receive Mode Register UART5 Bit Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART6 Special Mode Register 4 UART6 Special Mode Register 3 UART6 Special Mode Register 2 UART6 Special Mode Register UART6 Transmit/Receive Mode Register UART6 Bit Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register U5C0 U5C1 U5RB U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 37 of 113 M16C/63 Group Table 4.10 4. Special Function Registers (SFRs) SFR Information (10/16) (1) Address 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h to 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh Note: 1. Register Symbol Reset Value U7SMR4 U7SMR3 U7SMR2 U7SMR U7MR U7BRG U7TB S00 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh XXh I2C0 Address Register 0 I2C0 Control Register 0 I2C0 Clock Control Register I2C0 Start/Stop Condition Control Register I2C0 Control Register 1 I2C0 Control Register 2 I2C0 Status Register 0 I2C0 Status Register 1 I2C0 Address Register 1 I2C0 Address Register 2 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2 0000 000Xb 00h 00h 0001 1010b 0011 0000b 00h 0001 000Xb XXXX X000b 0000 000Xb 0000 000Xb Timer B3/B4/B5 Count Start Flag TBSR 000X XXXXb Timer A1-1 Register TA11 Timer A2-1 Register TA21 Timer A4-1 Register TA41 XXh XXh XXh XXh XXh XXh 00h 00h XX11 1111b XX11 1111b XXh XXh XXXX 0000b UART7 Special Mode Register 4 UART7 Special Mode Register 3 UART7 Special Mode Register 2 UART7 Special Mode Register UART7 Transmit/Receive Mode Register UART7 Bit Rate Register UART7 Transmit Buffer Register UART7 Transmit/Receive Control Register 0 UART7 Transmit/Receive Control Register 1 UART7 Receive Buffer Register I2C0 Data Shift Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Position-Data-Retain Function Control Register U7C0 U7C1 U7RB INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 38 of 113 M16C/63 Group Table 4.11 4. Special Function Registers (SFRs) SFR Information (11/16) (1) Address 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Note: 1. Symbol Reset Value Timer B3 Register Register TB3 Timer B4 Register TB4 Timer B5 Register TB5 XXh XXh XXh XXh XXh XXh Port Function Control Register PFCR 0011 1111b Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register TB3MR TB4MR TB5MR 00XX 0000b 00XX 0000b 00XX 0000b Count Start Flag TABSR 00h One-Shot Start Flag Trigger Select Register Up/Down Flag ONSF TRGSR UDF 00h 00h 00h Timer A0 Register TA0 Timer A1 Register TA1 Timer A2 Register TA2 Timer A3 Register TA3 Timer A4 Register TA4 Timer B0 Register TB0 Timer B1 Register TB1 Timer B2 Register TB2 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b X000 0000b Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 39 of 113 M16C/63 Group Table 4.12 4. Special Function Registers (SFRs) SFR Information (12/16) (1) Address Register Symbol Reset Value TRHSEC TRHMIN TRHHR TRHWK TRHDY TRHMON TRHYR TRHCR TRHCSR TRHADJ TRHIFR TRHIER TRHAMN TRHAHR TRHAWK TRHPRC CECC1 CECC2 CECC3 CECC4 CECFLG CISEL CCTB1 CCTB2 CCRB1 CCRB2 CRADRI1 CRADRI2 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0001b 0000 0001b 0000 0000b 0000 0100b 0000 1000b 0000 0000b XXX0 0000b 0000 0000b 0000 0000b 0000 0000b 0XXX X000b 00XX XXXXb XXXX X000b 00h XXXX 0000b 00h 00h 00h 00h XXXX XX00b 00h XXXX X000b 00h 00h 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h Second Data Register Minute Data Register Hour Data Register Day-of-the-Week Data Register Date Data Register Month Data Register Year Data Register Timer RH Control Register Timer RH Count Source Select Register Clock Error Correction Register Timer RH Interrupt Flag Register Timer RH Interrupt Enable Register Alarm Minute Register Alarm Hour Register Alarm Day-of-the-Week Register Timer RH Protect Register CEC Function Control Register 1 CEC Function Control Register 2 CEC Function Control Register 3 CEC Function Control Register 4 CEC Flag Register CEC Interrupt Source Select Register CEC Transmit Buffer Register 1 CEC Transmit Buffer Register 2 CEC Receive Buffer Register 1 CEC Receive Buffer Register 2 CEC Receive Follower Address Set Register 1 CEC Receive Follower Address Set Register 2 Pull-Up Control Register 0 PUR0 0361h Pull-Up Control Register 1 PUR1 0362h 0363h 0364h 0365h 0366h 0367h 0368h Pull-Up Control Register 2 PUR2 0000 0000b (2) 0000 0010b 00h Port Control Register PCR 0000 0XX0b 0369h NMI/SD Digital Filter Register NMIDF XXXX X000b 00h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh Notes: 1. 2. X: Undefined The blank areas are reserved. No access is allowed. Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows: - 00000000b when a low-level signal is input to the CNVSS pin - 00000010b when a high-level signal is input to the CNVSS pin Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detect reset are as follows: - 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode). - 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode). REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 40 of 113 M16C/63 Group Table 4.13 4. Special Function Registers (SFRs) SFR Information (13/16) (1) Address 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh Notes: 1. 2. Symbol Reset Value PWM Control Register 0 Register PWMCON0 00h PWM0 Prescaler PWM0 Register PWM1 Prescaler PWM1 Register PWM Control Register 1 PWMPRE0 PWMREG0 PWMPRE1 PWMREG1 PWMCON1 00h 00h 00h 00h 00h Count Source Protection Mode Register Watchdog Timer Refresh Register Watchdog Timer Start Register Watchdog Timer Control Register CSPR WDTR WDTS WDC 00h (2) XXh XXh 00XX XXXXb DMA2 Source Select Register DM2SL 00h DMA3 Source Select Register DM3SL 00h DMA0 Source Select Register DM0SL 00h DMA1 Source Select Register DM1SL 00h X: Undefined The blank areas are reserved. No access is allowed. When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 41 of 113 M16C/63 Group Table 4.14 4. Special Function Registers (SFRs) SFR Information (14/16) (1) Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Note: 1. Register Symbol Reset Value Open-Circuit Detection Assist Function Register AINRST XX00 XXXXb SFR Snoop Address Register CRCSAR CRC Mode Register CRCMR XXXX XXXXb 00XX XXXXb 0XXX XXX0b CRC Data Register CRCD CRC Input Register CRCIN A/D Register 0 AD0 A/D Register 1 AD1 A/D Register 2 AD2 A/D Register 3 AD3 A/D Register 4 AD4 A/D Register 5 AD5 A/D Register 6 AD6 A/D Register 7 AD7 XXh XXh XXh XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 42 of 113 M16C/63 Group Table 4.15 4. Special Function Registers (SFRs) SFR Information (15/16) (1) Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 0400h to D07Fh Note: 1. Register Symbol Reset Value A/D Control Register 2 ADCON2 0000 X00Xb A/D Control Register 0 A/D Control Register 1 D/A0 Register ADCON0 ADCON1 DA0 0000 0XXXb 0000 0000b 00h DA1 00h DACON XXXX XX00b Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh Port P10 Direction Register PD10 00h D/A1 Register D/A Control Register X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 43 of 113 M16C/63 Group Table 4.16 4. Special Function Registers (SFRs) SFR Information (16/16) (1) Address D080h D081h D082h D083h D084h D085h D086h D087h D088h D089h D08Ah D08Bh D08Ch D08Dh D08Eh D08Fh D090h D091h D092h D093h D094h D095h D096h D097h D098h D099h D09Ah D09Bh D09Ch D09Dh D09Eh D09Fh Note: 1. Symbol Reset Value PMC0 Header Pattern Set Register (Min) Register PMC0HDPMIN PMC0 Header Pattern Set Register (Max) PMC0HDPMAX PMC0 Data 0 Pattern Set Register (Min) PMC0 Data 0 Pattern Set Register (Max) PMC0 Data 1 Pattern Set Register (Min) PMC0 Data 1 Pattern Set Register (Max) PMC0 Measurements Register PMC0D0PMIN PMC0D0PMAX PMC0D1PMIN PMC0D1PMAX PMC0TIM 0000 0000b XXXX X000b 0000 0000b XXXX X000b 0000 0000b 00h 0000 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h XX00 0000b PMC0 Counter Value Register PMC0 Receive Data Store Register 0 PMC0 Receive Data Store Register 1 PMC0 Receive Data Store Register 2 PMC0 Receive Data Store Register 3 PMC0 Receive Data Store Register 4 PMC0 Receive Data Store Register 5 PMC0 Receive Bit Count Register PMC0BC PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 PMC0RBIT PMC1 Header Pattern Set Register (Min) PMC1HDPMIN PMC1 Header Pattern Set Register (Max) PMC1HDPMAX PMC1 Data 0 Pattern Set Register (Min) PMC1 Data 0 Pattern Set Register (Max) PMC1 Data 1 Pattern Set Register (Min) PMC1 Data 1 Pattern Set Register (Max) PMC1 Measurements Register PMC1D0PMIN PMC1D0PMAX PMC1D1PMIN PMC1D1PMAX PMC1TIM PMC1 Counter Value Register PMC1BC 0000 0000b XXXX X000b 0000 0000b XXXX X000b 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined The blank areas are reserved. No access is allowed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 44 of 113 M16C/63 Group 4.2 4. Special Function Registers (SFRs) Notes on SFRs 4.2.1 Register Settings Table 4.17 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 4.17 Registers with Write-Only Bits Register Symbol Address Watchdog Timer Refresh Register WDTR 037Dh Watchdog Timer Start Register WDTS 037Eh Timer A0 Register TA0 0327h to 0326h Timer A1 Register TA1 0329h to 0328h Timer A2 Register TA2 032Bh to 032Ah Timer A3 Register TA3 032Dh to 032Ch Timer A4 Register TA4 032Fh to 032Eh Timer A1-1 Register TA11 0303h to 0302h Timer A2-1 Register TA21 0305h to 0304h Timer A4-1 Register TA41 0307h to 0306h Three-Phase Output Buffer Register 0 IDB0 030Ah Three-Phase Output Buffer Register 1 IDB1 030Bh Dead Time Timer DTT 030Ch ICTB2 030Dh UART0 Bit Rate Register U0BRG 0249h UART1 Bit Rate Register U1BRG 0259h UART2 Bit Rate Register U2BRG 0269h UART5 Bit Rate Register U5BRG 0289h Timer B2 Interrupt Generation Frequency Set Counter UART6 Bit Rate Register U6BRG 0299h UART7 Bit Rate Register U7BRG 02A9h UART0 Transmit Buffer Register U0TB 024Bh to 024Ah UART1 Transmit Buffer Register U1TB 025Bh to 025Ah UART2 Transmit Buffer Register U2TB 026Bh to 026Ah UART5 Transmit Buffer Register U5TB 028Bh to 028Ah UART6 Transmit Buffer Register U6TB 029Bh to 029Ah UART7 Transmit Buffer Register U7TB 02ABh to 02AAh SI/O3 Bit Rate Register S3BRG 0273h SI/O4 Bit Rate Register S4BRG 0277h I2C0 Control Register 1 S3D0 02B6h I2C0 Status Register 0 S10 02B8h REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 45 of 113 M16C/63 Group 5. 5. Electrical Characteristics Electrical Characteristics 5.1 Electrical Characteristics (Common to 1.8 V, 3 V, and 5 V) 5.1.1 Table 5.1 Absolute Maximum Rating Absolute Maximum Ratings Rated Value Unit VCC1 Symbol Supply voltage Parameter VCC1 = AVCC Condition −0.3 to 6.5 V VCC2 Supply voltage VCC1 = AVCC −0.3 to VCC1 + 0.1 (1) V AVCC Analog supply voltage VCC1 = AVCC −0.3 to 6.5 V VREF Analog reference voltage VCC1 = AVCC −0.3 to VCC1 + 0.1 (1) V VI Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN −0.3 to VCC1 + 0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 −0.3 to VCC2 + 0.3 (1) V −0.3 to 6.5 V P7_0, P7_1, P8_5 VO −0.3 to VCC1 + 0.3 Output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 V −0.3 to VCC2 + 0.3 (1) V −0.3 to 6.5 V 300 mW When the MCU is operating −20 to 85/−40 to 85 °C Flash program erase −20 to 85/−40 to 85 P7_0, P7_1, P8_5 Pd Power consumption Topr Operating temperature Tstg (1) Storage temperature Note: 1. Maximum value is 6.5 V. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 46 of 113 −40°C < Topr ≤ 85°C −65 to 150 °C M16C/63 Group 5.1.2 5. Electrical Characteristics Recommended Operating Conditions Table 5.2 Recommended Operating Conditions (1/4) VCC1 = VCC2 = 1.8 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol VCC1 VCC2 Standard Parameter Supply voltage Supply voltage Min. Typ. Max. Unit VCC1 ≥ VCC2 2.7 5.5 V VCC1 = VCC2 1.8 5.5 V VCC1 ≥ 2.7 2.7 VCC1 V VCC1 < 2.7 VCC1 V AVCC Analog supply voltage VCC1 V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH High input voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (in single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input in memory expansion and microprocessor modes) VIL Low input voltage 2.7 V ≤ VCC1 ≤ 5.5 V 0.8VCC2 VCC2 V 1.8 V ≤ VCC1 < 2.7 V 0.85VCC2 VCC2 V 2.7 V ≤ VCC1 ≤ 5.5 V 0.8VCC2 VCC2 V 1.8 V ≤ VCC1 < 2.7 V 0.85VCC2 VCC2 V 2.7 V ≤ VCC1 ≤ 5.5 V 0.5VCC2 VCC2 V 1.8 V ≤ VCC1 < 2.7 V 0.55VCC2 VCC2 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE 2.7 V ≤ VCC1 ≤ 5.5 V 0.8VCC1 VCC1 V 1.8 V ≤ VCC1 < 2.7 V 0.85VCC1 VCC1 V P7_0, P7_1, P8_5 2.7 V ≤ VCC1 ≤ 5.5 V 0.8VCC1 6.5 V 1.8 V ≤ VCC1 < 2.7 V 0.85VCC1 6.5 V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 0 0.2VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (in single-chip mode) 0 0.2VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input in memory expansion and microprocessor mode) 0 0.16VCC2 V P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE 0 0.2VCC1 V REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 47 of 113 M16C/63 Group Table 5.3 5. Electrical Characteristics Recommended Operating Conditions (2/4) VCC1 = VCC2 = 1.8 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol Parameter IOH(sum) High peak output current (100-pin package) IOH(peak) High peak output current IOH(avg) High average output current (1) Typ. Max. Unit VCC1, VCC2 Sum of IOH(peak) at P0_0 to P0_7, P1_0 to ≥ 2.7 V P1_7, P2_0 to P2_7 Sum of IOH(peak) at P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 -40.0 mA -40.0 mA Sum of IOH(peak) at P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4 -40.0 mA Sum of IOH(peak) at P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 -40.0 mA VCC1, VCC2 Sum of IOH(peak) at P0_0 to P0_7, P1_0 to -5.0 mA P1_7, P2_0 to P2_7 Sum of IOH(peak) at P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 -5.0 mA Sum of IOH(peak) at P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4 -5.0 mA Sum of IOH(peak) at P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 -5.0 mA VCC1, VCC2 Sum of all ports ≥ 2.7 V -80.0 mA VCC1, VCC2 Sum of all ports < 2.7 V -10.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, ≥ 2.7 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 −10.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, < 2.7 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 −1.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, ≥ 2.7 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 −5.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, < 2.7 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 −0.5 mA < 2.7 V High peak output current (80-pin package) Standard Min. Note: 1. The average output current is the mean value within 100 ms. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 48 of 113 M16C/63 Group Table 5.4 5. Electrical Characteristics Recommended Operating Conditions (3/4) VCC1 = VCC2 = 1.8 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol IOL(sum) Standard Parameter Low peak VCC1, VCC2 output ≥ 2.7 V current (100-pin package) Min. Typ. Max. Unit Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 80.0 mA Sum of IOL(peak) at P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_5 80.0 mA VCC1, VCC2 Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, < 2.7 V P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 10.0 mA Sum of IOL(peak) at P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_5 10.0 mA VCC1, VCC2 Sum of all ports ≥ 2.7 V 80.0 mA VCC1, VCC2 Sum of all ports < 2.7 V 10.0 mA IOL(peak) Low peak VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, output P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, ≥ 2.7 current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 10.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, < 2.7 V P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 1.0 mA P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 5.0 mA VCC1, VCC2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, < 2.7 V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 0.5 mA Low peak output current (80-pin package) IOL(avg) f(XIN) VCC1, VCC2 Low average ≥ 2.7 V output current (1) Main clock input oscillation frequency 2.7 V ≤ VCC1 ≤ 5.5 V 1 20 MHz 1.8 V ≤ VCC1 < 2.7 V 1 10 MHz f(XCIN) Sub clock oscillation frequency f(BCLK) CPU operation clock 32.768 2.7 V ≤ VCC1 ≤ 5.5 V 20 1.8 V ≤ VCC1 < 2.7 V Notes: 1. The average output current is the mean value within 100 ms. 2. Calculated by the following equation according to VCC1: 16.67 × V See Figure 5.1 “Relation between f(BCLK) and VCC1” REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 49 of 113 kHz MHz (Note 2) MHz CC1 – 25 [MHz] M16C/63 Group 5. Electrical Characteristics f (BCLK) [MHz] 20 5 1.8 2.7 Vcc1 [V] Figure 5.1 Relation between f(BCLK) and VCC1 REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 50 of 113 5.5 M16C/63 Group Table 5.5 5. Electrical Characteristics Recommended Operating Conditions (4/4)(1) VCC1 = 1.8 to 5.5 V, VSS = 0 V, and Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. The ripple voltage must not excess Vr(VCC1) and/or dVr(VCC1)/dt. Symbol Vr(VCC1) Standard Parameter Allowable ripple voltage dVr(VCC1)/dt Ripple voltage falling gradient Min. Typ. Max. VCC1 = 5.0 V 0.5 Vp-p VCC1 = 3.0 V 0.3 Vp-p VCC1 = 2.0 V 0.2 Vp-p VCC1 = 5.0 V 0.3 V/ms VCC1 = 3.0 V 0.3 V/ms VCC1 = 2.0 V 0.3 V/ms Note: 1. The device is operationally guaranteed under these operating conditions. VCC1 Figure 5.2 Ripple Waveform REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 51 of 113 Unit V r(VCC1) M16C/63 Group 5.1.3 5. Electrical Characteristics A/D Conversion Characteristics Table 5.6 A/D Conversion Characteristics (1/2) (1) AVCC = VCC1 = VCC2 = VREF = 1.8 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol Parameter Measuring Condition - Resolution AVCC = VCC1 = VCC2 = VREF INL Integral non-linearity error 10bit VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 5.0 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 3.3 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 3.0 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, 2.2 V (3) AN0_0 to AN0_7 input, AN2_0 to AN2_7 input (Note 2) - Absolute accuracy 10bit Min. Standard Typ. Max. 10 Unit Bits ±3 LSB ±3 LSB ±3 LSB ±6 LSB VCC1 = AN0 to AN7 input, 1.8 V (3) AN0_0 to AN0_7 input, AN2_0 to AN2_7 input (Note 2) ±6 LSB VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 5.0 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 3.3 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, AN0_0 to AN0_7 input, 3.0 V AN2_0 to AN2_7 input, ANEX0, ANEX1 input (Note 2) VCC1 = AN0 to AN7 input, 2.2 V (3) AN0_0 to AN0_7 input, AN2_0 to AN2_7 input (Note 2) ±3 LSB ±3 LSB ±3 LSB ±6 LSB VCC1 = AN0 to AN7 input, 1.8 V (3) AN0_0 to AN0_7 input, AN2_0 to AN2_7 input (Note 2) ±6 LSB Notes: 1. Use when AVCC = VCC1. 2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and connect them to VSS. See Figure 5.3 “A/D Accuracy Measure Circuit”. 3. PUMPON bit in the ADCON1 register is 1 (Voltage multiplier ON) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 52 of 113 M16C/63 Group 5. Electrical Characteristics AN Analog input AN: One of the analog input pin P0 to P10: I/O pins other than AN P0 to P10 Figure 5.3 A/D Accuracy Measure Circuit Table 5.7 A/D Conversion Characteristics (2/2) (1) AVCC = VCC1 = VCC2 = VREF = 1.8 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol φAD Parameter A/D operating clock frequency Measuring Condition Standard Min. Typ. Max. Unit 4.0 V ≤ VREF ≤ AVCC ≤ 5.5 V 2 20 MHz 3.2 V ≤ VREF ≤ AVCC ≤ 5.5 V 2 16 MHz 3.0 V ≤ VREF ≤ AVCC ≤ 5.5 V 2 10 MHz 1.8 V ≤ VREF ≤ AVCC ≤ 5.5 V 2 5 MHz - Tolerance level impedance DNL Differential non-linearity error (4) ±1 LSB - Offset error (4) ±3 LSB - Gain error (4) ±3 LSB tCONV 10-bit conversion time VCC1 = 5 V, φAD = 20 MHz tSAMP Sampling time VREF Reference voltage VIA Notes: 1. 2. 3. 4. Analog input voltage (2), (3) 3 kΩ 2.15 μs 0.75 μs 1.8 AVCC V 0 VREF V Use when AVCC = VCC1 = VCC2. Do not use A/D converter when VCC1 > VCC2. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and connect them to VSS. See Figure 5.3 “A/D Accuracy Measure Circuit”. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 53 of 113 M16C/63 Group 5.1.4 5. Electrical Characteristics D/A Conversion Characteristics Table 5.8 D/A Conversion Characteristics VCC1 = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol Parameter - Resolution - Absolute Accuracy tSU Setup Time RO Output Resistance IVREF Reference Power Supply Input Current Measuring Condition Standard Min. 5 See Notes 1 and 2 Typ. 6 Max. Unit 8 Bits 2.5 LSB 3 μs 8.2 kΩ 1.5 mA Notes: 1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h. 2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)). REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 54 of 113 M16C/63 Group 5.1.5 5. Electrical Characteristics Flash Memory Electrical Characteristics Table 5.9 CPU Clock When Operating Flash Memory (f(BCLK)) VCC1 = 1.8 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C unless otherwise specified. Symbol Parameter - CPU rewrite mode f(SLOW_R) Slow read mode Conditions Standard Min. Typ. Max. 10 (1) 5 - Low current consumption read mode - Data flash read fC(32.768) 3.0 V < VCC1 ≤ 5.5 V 35 20 (2) Unit MHz MHz kHz MHz Notes: 1. Set the PM17 bit in the PM1 register to 1 (one wait). 2. When the frequency is 1.8 ≤ VCC1 ≤ 3.0 V, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in the PM1 register to 1 (one wait) Table 5.10 Flash Memory (Program ROM 1, 2) Electrical Characteristics VCC1 = 2.7 to 5.5 V at Topr = 0 to 60°C (option: -40°C to 85°C), unless otherwise specified. Symbol - Parameter Conditions Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C VCC1 = 3.3 V, Topr = 25°C Two words program time Standard Min. Typ. Max. Unit times 1,000 (2) 150 4000 μs - Lock bit program time VCC1 = 3.3 V, Topr = 25°C 70 3000 μs - Block erase time VCC1 = 3.3 V, Topr = 25°C 0.2 3.0 s td(SR-SUS) Time delay from suspend request until suspend 5 + CPU clock × 3 cycles ms - Interval from erase start/restart until following suspend request 0 μs - Suspend interval necessary for auto-erasure to complete (7) 20 ms - Time from suspend until erase restart - Program, erase voltage 2.7 5.5 V - Read voltage 2.7 5.5 V 0 60 °C 50 μs 30 + CPU clock × 1 cycle - Program, erase temperature tPS Flash Memory Circuit Stabilization Wait Time - Data hold time (6) Ambient temperature = 55°C 20 μs year Notes: 1. Definition of program and erase cycles: The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 55 of 113 M16C/63 Group 5. Electrical Characteristics Table 5.11 Flash Memory (Data Flash) Electrical Characteristics VCC1 = 2.7 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified. Symbol Parameter Conditions Standard Min. Typ. Max. Unit - Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C - Two words program time VCC1 = 3.3 V, Topr = 25°C 300 4000 μs - Lock bit program time VCC1 = 3.3 V, Topr = 25°C 140 3000 μs - Block erase time VCC1 = 3.3 V, Topr = 25°C 0.2 3.0 s td(SR-SUS) Time delay from suspend request until suspend 5 + CPU clock × 3 cycles ms - Interval from erase start/restart until following suspend request 0 μs - Suspend interval necessary for auto-erasure to complete (7) 20 ms - Time from suspend until erase restart - Program, erase voltage - Read voltage - Program, erase temperature tPS Flash Memory Circuit Stabilization Wait Time - Data hold time (6) Ambient temperature = 55 °C 10,000 (2) times 30 + CPU clock × 1 cycle μs 2.7 5.5 V 2.7 5.5 V −20/−40 85 °C 50 μs 20 year Notes: 1. Definition of program and erase cycles The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 10,000), each block can be erased n times. For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 56 of 113 M16C/63 Group 5.1.6 5. Electrical Characteristics Voltage Detector and Power Supply Circuit Electrical Characteristics Table 5.12 Voltage Detector 0 Electrical Characteristics The measurement condition is VCC1 = 1.8 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified. Symbol Vdet0 Parameter Condition Standard Min. Typ. Max. Unit Voltage detection level Vdet0_0 (1) When VCC1 is falling. 1.80 1.90 2.10 V (1) When VCC1 is falling. 2.70 2.85 3.00 V 200 μs Voltage detection level Vdet0_2 - Voltage detector 0 response time (3) When VCC1 falls from 5 V to (Vdet0_0 - 0.1) V - Voltage detector self power consumption VC25 = 1, VCC1 = 5.0 V td(E-A) Waiting time until voltage detector operation starts (2) μA 1.5 100 μs Notes: 1. Select the voltage detection level with the VDSEL1 bit in the OFS1 address. 2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2 register to 0. 3. Time from when passing the Vdet0 until when a voltage monitor 0 reset is generated. Table 5.13 Voltage Detector 1 Electrical Characteristics The measurement condition is VCC1 = 1.8 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified. Symbol Vdet1 - Parameter Condition Standard Min. Typ. Max. Unit Voltage detection level Vdet1_0 (1) When VCC1 is falling. 1.90 2.20 2.50 V Voltage detection level Vdet1_6 (1) When VCC1 is falling. 2.80 3.10 3.40 V Voltage detection level Vdet1_B (1) When VCC1 is falling. 3.55 3.85 4.15 V Voltage detection level Vdet1_F (1) When VCC1 is falling. 4.15 4.45 4.75 V Hysteresis width at the rising of VCC1 in voltage When selecting Vdet1_0 detector 1 When selecting Vdet1_6 to Vdet1_F - Voltage detector 1 response time (3) When VCC1 falls from 5 V to (Vdet1_0 - 0.1) V - Voltage detector self power consumption VC26 = 1, VCC1 = 5.0 V td(E-A) Waiting time until voltage detector operation starts (2) 0.10 V 0.15 V 200 μs μA 1.7 100 μs Notes: 1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC26 bit in the VCR2 register to 0. 3. Time from when passing the Vdet1 until when a voltage monitor 1 reset is generated. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 57 of 113 M16C/63 Group 5. Electrical Characteristics Table 5.14 Voltage Detector 2 Electrical Characteristics The measurement condition is VCC1 = 1.8 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified. Symbol Parameter Standard Condition Vdet2 Voltage detection level Vdet2_0 - Hysteresis width at the rising of VCC1 in voltage detector 2 - Voltage detector 2 response time (2) When VCC1 falls from 5 V to (Vdet2_0 - 0.1) V - Voltage detector self power consumption VC27 = 1, VCC1 = 5.0 V td(E-A) Waiting time until voltage detector operation starts (1) When VCC1 is falling Min. Typ. Max. 3.70 4.00 4.30 0.15 Unit V V 200 μs μA 1.7 100 μs Notes: 1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2 register to 0. 2. Time from when passing the Vdet2 until when a voltage monitor 2 reset is generated. Table 5.15 Power-On Reset Circuit The measurement condition is VCC1 = 2.0 to 5.5 V, Topr = -20 to 85°C/ -40 to 85°C, unless otherwise specified. Symbol Parameter Vpor1 Voltage at which power-on reset enabled (1) trth External power VCC1 rise gradient Condition Standard Min. Typ. Max. 0.1 2.0 Unit V 50000 mV/ms Note: 1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address to 0. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 58 of 113 M16C/63 Group 5. Electrical Characteristics Vdet0 (1) External Power VCC1 Vdet0 (1) t rth t rth Vpor1 Voltage detection 0 circuit response time tw(por) (2) Internal reset signal 1 1 × 32 fOCO-S × 32 fOCO-S Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 7. “Voltage Detector” for details. 2. When using power-on reset, hold the external power VCC1 at or below Vpor1 during tw(por), and then turn it on. tw(por) is 30 s or more when -20°C ≤ Topr ≤ 85°C, and 3000 s or more when -40°C ≤ Topr < -20°C. Figure 5.4 Power-On Reset Circuit Electrical Characteristics Table 5.16 Power Supply Circuit Timing Characteristics The measurement condition is VCC1 = 1.8 to 5.5 V and Topr = 25°C, unless otherwise specified. Symbol Parameter Condition Standard Min. Typ. Max. Unit td(P-R) Internal power supply stability time when power is on (1) 5 ms td(R-S) STOP release time 150 μs td(W-S) Low power mode wait mode release time 150 μs Note: 1. Waiting time until the internal power supply generator stabilizes when power is on. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 59 of 113 M16C/63 Group 5. Electrical Characteristics Recommended operation voltage td(P-R) Internal power supply stability time when power is on Vcc1 td(P-R) CPU clock td(R-S) STOP release time td(W-S) Low power mode wait mode release time Interrupt for (a) Stop mode release or (b) Wait mode release CPU clock (a) (b) td(E-A) Voltage detector operation start time td(R-S) td(W-S) VC25, VC26, VC27 Voltage detector Stop Operate td(E-A) Figure 5.5 Power Supply Circuit Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 60 of 113 M16C/63 Group 5.1.7 5. Electrical Characteristics Oscillation Circuit Electrical Characteristics Table 5.17 40 MHz On-Chip Oscillator Circuit Electrical Characteristics (1/2) VCC1 = 1.8 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified. Symbol fOCO40M Parameter Condition Standard Unit Min. Typ. Max. 40 MHz on-chip oscillator frequency Average frequency in a 10 ms period 2.7 V ≤ VCC1 < 5.5 V 36 40 44 MHz Average frequency in a 10 ms period 1.8 V ≤ VCC1 < 2.7 V 30 40 50 MHz 2 ms tsu(fOCO40M) Wait time until 40 MHz on-chip oscillator stabilizes Note: 1. This indicates the precision error for the oscillation frequency of the 40 MHz on-chip oscillator. Table 5.18 125 kHz On-Chip Oscillator Circuit Electrical Characteristics VCC1 = 1.8 to 5.5 V, Topr = −20 to 85°C/−40 to 85°C, unless otherwise specified. Symbol Parameter fOCO-S 125 kHz on-chip oscillator frequency tsu(fOCO-S) Wait time until 125 kHz on-chip oscillator stabilizes REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 61 of 113 Condition Standard Unit Min. Typ. Max. Average frequency in a 10 ms period 100 125 150 kHz 20 μs M16C/63 Group 5.2 5. Electrical Characteristics Electrical Characteristics (VCC1 = VCC2 = 5 V) 5.2.1 Electrical Characteristics VCC1 = VCC2 = 5 V Table 5.19 Electrical Characteristics (1) (1) VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol VOH VOH VOH VOL VOL Min. Typ. Max. High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH = −5 mA VCC1 − 2.0 VCC1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOH = −5 mA VCC2 − 2.0 VCC2 High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH = −200 μA VCC1 − 0.3 VCC1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOH = −200 μA VCC2 − 0.3 VCC2 HIGHPOWER IOH = −1 mA VCC1 − 2.0 VCC1 LOWPOWER IOH = −0.5 mA VCC1 − 2.0 VCC1 High output voltage High output voltage VOL Standard Measuring Condition Parameter XOUT XCOUT With no load applied 1.5 IOL = 5 mA 2.0 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOL = 5 mA 2.0 Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, voltage P9_0 to P9_7, P10_0 to P10_7 IOL = 200 μA 0.45 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOL = 200 μA 0.45 HIGHPOWER IOL = 1 mA 2.0 LOWPOWER IOL = 0.5 mA 2.0 Low output voltage XOUT XCOUT With no load applied Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 62 of 113 0 V V V V Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, voltage P9_0 to P9_7, P10_0 to P10_7 Low output voltage Unit V V V V M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V Table 5.20 Electrical Characteristics (2) (1) VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol Parameter Measuring Condition Standard Min. Typ. Max. Unit VT+ - VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to KI7, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD, PMC0, PMC1, SCLMM, SDAMM, CEC 0.5 2.0 V VT+ - VT- Hysteresis RESET 0.5 2.5 V IIH High input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE VI = 5 V 5.0 μA IIL Low input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE VI = 0 V −5.0 μA RPULLUP Pull-up resistance P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 VI = 0 V 170 kΩ RfXIN Feedback resistance XIN RfXCIN Feedback resistance XCIN VRAM RAM retention voltage In stop mode Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 63 of 113 30 1.8 50 0.8 MΩ 8 MΩ V M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V Table 5.21 Electrical Characteristics (3) VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol ICC Parameter Measuring Condition Power supply current High-speed mode f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) In single-chip, mode, 125 kHz on-chip oscillator stop the output pin are CM15 = 1 (drive capacity High) open and other pins A/D converter stop are VSS f(BCLK) =20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) A/D converter operating(2) f(BCLK) = 20 MHz XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) A/D converter stop f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) PCLKSTP1 = FF (peripheral clock stop) f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) PCLKSTP1 = FF (peripheral clock stop) 40 MHz on-chip Main clock stop oscillator mode 40 MHz on-chip oscillator on divide-by-2 (f(BCLK) = 20 MHz) 125 kHz on-chip oscillator stop 125 kHz on-chip Main clock stop oscillator mode 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on, no division FMR22 = 1 (slow read mode) Low-power mode f(BCLK) = 32 kHz FMR22 = FMR23 = 1 (in low current consumption read mode) On flash memory (1) Wait mode f(BCLK) = 32 kHz Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on PM25 = 1 (peripheral function clock fC operating) Topr = 25°C Real-time clock operating f(BCLK) = 32 kHz Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator stop PM25 = 0 (peripheral function clock fC stop) Topr = 25°C Min. Standard Typ. Max. Unit 10.7 mA 11.4 mA 10.1 mA 9.1 mA 8.5 mA 9.0 mA 450.0 μA 80.0 μA 5.6 μA 5.3 μA Stop mode Topr = 25°C 2.4 μA During flash memory program f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC1 = 5.0 V 20.0 mA During flash memory erase f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC1 = 5.0 V 30.0 mA Notes: 1. This indicates the memory in which the program to be executed exists. 2. A/D conversion is executed in repeat mode. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 64 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V 5.2.2 Timing Requirements (Peripheral Functions and Others) (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.2.1 Reset Input (RESET Input) Table 5.22 Reset Input (RESET Input) Symbol Standard Parameter Min. RESET input low pulse width tw(RSTL) Max. Unit μs 10 RESET input t w(RTSL) Figure 5.6 5.2.2.2 Table 5.23 Reset Input (RESET Input) External Clock Input External Clock Input (XIN Input) (1) Symbol Standard Parameter Min. Max. Unit tc External clock input cycle time 50 ns tw(H) External clock input high pulse width 20 ns tw(L) External clock input low pulse width 20 ns tr External clock rise time 9 ns tf External clock fall time 9 ns Note: 1. The condition is VCC1 = VCC2 = 3.0 to 5.0 V. XIN input tr t w(H) tf t w(L) tc Figure 5.7 External Clock Input (XIN Input) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 65 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.2.3 Table 5.24 VCC2 = 5 V Timer A Input Timer A Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 100 ns tw(TAH) TAiIN input high pulse width 40 ns tw(TAL) TAiIN input low pulse width 40 ns Table 5.25 Timer A Input (Gating Input in Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 400 ns tw(TAH) TAiIN input high pulse width 200 ns tw(TAL) TAiIN input low pulse width 200 ns Table 5.26 Timer A Input (External Trigger Input in One-Shot Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 200 ns tw(TAH) TAiIN input high pulse width 100 ns tw(TAL) TAiIN input low pulse width 100 ns Table 5.27 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and Programmable Output Mode) Symbol Standard Parameter Min. Max. Unit tw(TAH) TAiIN input high pulse width 100 ns tw(TAL) TAiIN input low pulse width 100 ns tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL) Figure 5.8 Timer A Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 66 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) Table 5.28 VCC2 = 5 V Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 800 ns tsu(TAIN-TAOUT) TAiOUT input setup time 200 ns tsu(TAOUT-TAIN) TAiIN input setup time 200 ns Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) Figure 5.9 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 67 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.2.4 Table 5.29 VCC2 = 5 V Timer B Input Timer B Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input high pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input low pulse width (counted on one edge) 40 ns tc(TB) TBiIN input cycle time (counted on both edges) 200 ns tw(TBH) TBiIN input high pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input low pulse width (counted on both edges) 80 ns Table 5.30 Timer B Input (Pulse Period Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input high pulse width 200 ns tw(TBL) TBiIN input low pulse width 200 ns Table 5.31 Timer B Input (Pulse Width Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input high pulse width 200 ns tw(TBL) TBiIN input low pulse width 200 ns tc(TB) t w(TBH) TBiIN input t w(TBL) Figure 5.10 Timer B Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 68 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.2.5 Table 5.32 VCC2 = 5 V Serial Interface Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 200 ns tw(CKH) CLKi input high pulse width 100 ns tw(CKL) CLKi input low pulse width 100 td(C-Q) TXDi output delay time th(C-Q) TXDi hold time 0 ns tsu(D-C) RXDi input setup time 70 ns th(C-D) RXDi input hold time 90 ns ns 80 ns tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi Figure 5.11 5.2.2.6 Table 5.33 Serial Interface External Interrupt INTi Input External Interrupt INTi Input Symbol Standard Parameter Min. Max. Unit tw(INH) INTi input high pulse width 250 ns tw(INL) INTi input low pulse width 250 ns t w(INL) INTi input t w(INH) Figure 5.12 External Interrupt INTi Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 69 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.3 VCC2 = 5 V Timing Requirements (Memory Expansion Mode and Microprocessor Mode) Table 5.34 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard Min. Max. Unit tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns tac2(RD-DB) Data input access time (for setting with 1 to 3 waits) (Note 2) ns tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns tac4(RD-DB) Data input access time (for setting with 2φ + 3φ or more) (Note 4) ns tsu(DB-RD) Data input setup time 40 ns tsu(RDY-BCLK) RDY input setup time 30 ns tsu(HOLD-BCLK) HOLD input setup time 40 ns th(RD-DB) Data input hold time 0 ns th(BCLK-RDY) RDY input hold time 0 ns th(BCLK-HOLD) HOLD input hold time 0 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 45 [ ns ] --------------------f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n + 0.5 ) × 10 - – 45 [ ns ] ----------------------------------f ( BCLK ) 3. n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) × 10 - – 45 [ ns ] ----------------------------------f ( BCLK ) 4. n is 2 for 2 waits setting, and 3 for 3 waits setting. Calculated according to the BCLK frequency as follows: 9 n × 10 - – 45 [ ns ] ----------------f ( BCLK ) n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 70 of 113 M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode VCC1 = VCC2 = 5 V (Effective in wait state setting) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to wait state and no wait state settings) BCLK tsu(HOLD-BCLK) th(BCLK-HOLD) HOLD input HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK-HLDA) td(BCLK-HLDA) Hi−Z Note: 1. These pins are high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register, and PM11 bit in PM1 register. Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 1.0 V, VIH = 4.0 V y Output timing voltage: VOL = 2.5 V, VOH = 2.5 V Figure 5.13 Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 71 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V 5.2.4 Switching Characteristics (Memory Expansion Mode and Microprocessor Mode) (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.4.1 Table 5.35 In No Wait State Setting Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting) Symbol Measuring Condition Parameter td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) Standard Min. Max. 25 Unit ns 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time td(BCLK-RD) RD signal output delay time 25 th(BCLK-RD) RD signal output hold time WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) ns ns ns 25 Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) HLDA output delay time 25 0 td(DB-WR) Data output hold time (in relation to WR) ns 0 th(BCLK-DB) th(WR-DB) ns 15 −4 See Figure 5.14 td(BCLK-WR) td(BCLK-HLDA) 0 (3) (3) ns ns ns 40 ns 0 ns (Note 1) ns (Note 2) ns 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 40 [ ns ] --------------------f(BCLK) is 12.5 MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1−VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 72 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Figure 5.14 Ports P0 to P10 Measurement Circuit REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 73 of 113 30 pF M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V Memory Expansion Mode and Microprocessor Mode (in no wait state setting) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns(max.) 0ns(min.) CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns(max.) ADi BHE td(BCLK-ALE) 15ns(max.) 0ns(min.) th(BCLK-ALE) th(RD-AD) -4ns(min.) 0ns(min.) ALE th(BCLK-RD) td(BCLK-RD) 25ns(max.) 0ns(min.) RD tac1(RD-DB) (0.5 × tcyc -45)ns(max.) Hi-Z DBi tsu(DB-RD) th(RD-DB) 40ns(min.) 0ns(min.) Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns(max.) 0ns(min.) CSi tcyc ADi BHE td(BCLK-AD) th(BCLK-AD) 25ns(max.) 0ns(min.) td(BCLK-ALE) 15ns(max.) th(BCLK-ALE) -4ns(min.) th(WR-AD) (0.5 × tcyc -10)ns(min.) td(BCLK-WR) th(BCLK-WR) ALE 25ns(max.) 0ns(min.) WR, WRL, WRH td(BCLK-DB) 40ns(max.) 0ns(min.) Hi-Z DBi td(DB-WR) (0.5 × tcyc -40)ns(min.) tcyc = 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.15 th(BCLK-DB) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 74 of 113 th(WR-DB) (0.5 × tcyc -10)ns(min.) M16C/63 Group 5. Electrical Characteristics VCC1 = Switching Characteristics (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.4.2 Table 5.36 VCC2 = 5 V In 1 to 3 Waits Setting and When Accessing External Area Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When Accessing External Area) Symbol Measuring Condition Parameter Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time 25 25 ns ns -4 th(BCLK-RD) RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) td(DB-WR) 0 See Figure 5.14 RD signal output delay time Data output hold time (in relation to BCLK) ns 15 td(BCLK-RD) th(BCLK-DB) ns ns 25 ns 0 ns 25 ns 0 (3) ns 40 ns 0 ns Data output delay time (in relation to WR) (Note 1) ns th(WR-DB) Data output hold time (in relation to WR)(3) (Note 2) ns td(BCLK-HLDA) HLDA output delay time 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 (----------------------------------n – 0.5 ) × 10 - – 40 [ ns ] f ( BCLK ) 2. n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. When n = 1, f(BCLK) is 12.5 MHz or less. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1 − VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 75 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V Memory Expansion Mode and Microprocessor Mode (in 1 to 3 waits setting and when accessing external area) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns(max.) 0ns(min.) CSi tcyc ADi BHE td(BCLK-AD) th(BCLK-AD) 25ns(max.) 0ns(min.) td(BCLK-ALE) 15ns(max.) th(BCLK-ALE) th(RD-AD) -4ns(min.) 0ns(min.) ALE th(BCLK-RD) td(BCLK-RD) 0ns(min.) 25ns(max.) tac2(RD-DB) {(n+0.5) × t cyc - 45}ns(max.) RD Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns(min.) 40ns(min.) Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns(max.) 0ns(min.) CSi tcyc th(BCLK-AD) td(BCLK-AD) 0ns(min.) 25ns(max.) ADi BHE td(BCLK-ALE) 15ns(max.) th(BCLK-ALE) th(WR-AD) -4ns(min.) (0.5 × tcyc -10)ns(min.) ALE th(BCLK-WR) td(BCLK-WR) 0ns(min.) 25ns(max.) WR, WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns(max.) 0ns(min.) Hi-Z DBi td(DB-WR) {(n-0.5) × t cyc - 40}ns(min.) tcyc = (0.5 × tcyc -10)ns(min.) 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.16 th(WR-DB) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 76 of 113 n: 1 (when 1 wait) 2 (when 2 waits) 3 (when 3 waits) M16C/63 Group 5. Electrical Characteristics VCC1 = Switching Characteristics (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) VCC2 = 5 V 5.2.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus Table 5.37 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus) (5) Symbol Parameter Measuring Condition Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) (Note 1) ns th(WR-AD) Address output hold time (in relation to WR) (Note 1) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) th(RD-CS) th(WR-CS) 25 25 ns ns 0 ns Chip select output hold time (in relation to RD) (Note 1) ns Chip select output hold time (in relation to WR) (Note 1) ns td(BCLK-RD) RD signal output delay time th(BCLK-RD) RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) th(BCLK-DB) Data output hold time (in relation to BCLK) 0 ns td(DB-WR) Data output delay time (in relation to WR) (Note 2) ns th(WR-DB) Data output hold time (in relation to WR) (Note 1) ns 25 ns 25 ns 40 ns 0 See Figure 5.14 ns 0 ns td(BCLK-HLDA) HLDA output delay time td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) td(AD-ALE) ALE signal output delay time (in relation to Address) (Note 3) ns th(AD-ALE) ALE signal output hold time (in relation to Address) (Note 4) ns td(AD-RD) RD signal output delay from the end of address 0 ns td(AD-WR) WR signal output delay from the end of address 0 tdz(RD-AD) Address output floating start time Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) × 10 - – 40 [ ns ] n is 2 for 2-wait setting, 3 for 3-wait setting. ----------------------------------f ( BCLK ) 3. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 25 [ ns ] --------------------f ( BCLK ) 4. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 15 [ ns ] --------------------f ( BCLK ) 5. When using multiplex bus, set f(BCLK) 12.5 MHz or less. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 77 of 113 40 ns 15 ns −4 ns ns 8 ns M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 5 V Memory Expansion Mode and Microprocessor Mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) Read timing BCLK th(BCLK-CS) td(BCLK-CS) th(RD-CS) tcyc 25ns(max.) 0ns(min.) (0.5 × tcyc -10)ns(min.) CSi td(AD-ALE) (0.5 × tcyc -25ns(min.) ADi /DBi th(ALE-AD) (0.5 × tcyc -15ns(min.) Address Address Data input tdz(RD-AD) 8ns(max.) tsu(DB-RD) tac3(RD-DB) {(n-0.5) × tcyc -45}ns(max.) 40ns(min.) th(RD-DB) 0ns(min.) td(AD-RD) td(BCLK-AD) 0ns(min.) 25ns(max.) th(BCLK-AD) 0ns(min.) ADi BHE td(BCLK-ALE) 15ns(max.) th(BCLK-ALE) th(RD-AD) (0.5 × tcyc -10)ns(min.) -4ns(min.) ALE td(BCLK-RD) 25ns(max.) th(BCLK-RD) 0ns(min.) RD Write timing BCLK td(BCLK-CS) tcyc 25ns(max.) th(WR-CS) (0.5 × tcyc -10)ns(min.) th(BCLK-CS) 0ns(min.) CSi td(BCLK-DB) th(BCLK-DB) 40ns(max.) ADi /DBi Address 0ns(min.) Address Data output td(DB-WR) {(n-0.5) × t cyc - 40}ns(min.) td(AD-ALE) (0.5 × tcyc -25ns(min.) th(WR-DB) (0.5 × tcyc -10)ns(min.) td(BCLK-AD) th(BCLK-AD) 25ns(max.) ADi BHE td(BCLK-ALE) 15ns(max.) 0ns(min.) th(BCLK-ALE) td(AD-WR) -4ns(min.) 0ns(min.) th(WR-AD) (0.5 × tcyc -10)ns(min.) ALE th(BCLK-WR) td(BCLK-WR) 25ns(max.) 0ns(min.) WR,WRL, WRH Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.17 Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 78 of 113 n: 2 (when 2 waits) 3 (when 3 waits) M16C/63 Group 5. Electrical Characteristics VCC1 = Switching Characteristics (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) VCC2 = 5 V 5.2.4.4 In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area Table 5.38 Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2 φ + 3 φ, 2 φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area) Symbol Measuring Condition Parameter Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time 25 25 RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) th(BCLK-DB) Data output hold time (in relation to BCLK) (3) td(DB-WR) Data output delay time (in relation to WR) HLDA output delay time ns ns -4 th(BCLK-RD) td(BCLK-HLDA) 0 See Figure 5.14 RD signal output delay time Data output hold time (in relation to WR) ns 15 td(BCLK-RD) th(WR-DB) ns ns 25 ns 0 ns 25 ns 0 (3) ns 40 ns 0 ns (Note 1) ns (Note 2) ns 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) × 10 - – 40 [ ns ] ----------------------------------f ( BCLK ) 2. n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1 − VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 79 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and when accessing external area) Read timing VCC1 = VCC2 = 5 V tcyc BCLK th(BCLK-CS) 2ns(min.) td(BCLK-CS) 25ns(max.) CSi td(BCLK-AD) 25ns(max.) th(BCLK-AD) 2ns(min.) ADi BHE td(BCLK-ALE) 15ns(max.) th(RD-AD) 0ns(min.) th(BCLK-ALE) -4ns(min.) ALE td(BCLK-RD) 25ns(max.) th(BCLK-RD) 0ns(min.) RD tac4(RD-DB) (n × t cyc -45)ns(max.) Hi-Z DBi tsu(DB-RD) 40ns(min.) Write timing th(RD-DB) 0ns(min.) tcyc BCLK td(BCLK-CS) 25ns(max.) th(BCLK-CS) 2ns(min.) td(BCLK-AD) 25ns(max.) th(BCLK-AD) 2ns(min.) CSi ADi BHE td(BCLK-ALE) 15ns(max.) th(WR-AD) (0.5 × tcyc -10)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-WR) 0ns(min.) td(BCLK-WR) 25ns(max.) WR, WRL WRH td(BCLK-DB) 40ns(min.) Hi-Z DBi tcyc = 1 td(DB-WR) {(n-0.5) × tcyc -40}ns(min.) f(BCLK) Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.18 th(BCLK-DB) 2ns(min.) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 80 of 113 n: 3 (when 2φ + 3φ) 4 (when 2φ + 4φ or 3φ + 4φ) 5 (when 4φ + 5φ) th(WR-DB) (0.5 × t cyc -10)ns(min.) M16C/63 Group 5. Electrical Characteristics VCC1 = Switching Characteristics (VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.2.4.5 Table 5.39 VCC2 = 5 V In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing External Area Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing External Area) Symbol Parameter Measuring Condition Standard Min. Unit Max. td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) (Note 4) ns (Note 2) ns th(WR-AD) Address output hold time (in relation to WR) td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time td(BCLK-RD) RD signal output delay time th(BCLK-RD) RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) th(BCLK-DB) Data output hold time (in relation to BCLK) (3) td(DB-WR) th(WR-DB) td(BCLK-HLDA) HLDA output delay time 25 ns 25 ns 0 ns 15 ns -4 See Figure 5.14 ns 25 ns 25 ns 40 ns 0 ns 0 ns 0 ns Data output delay time (in relation to WR) (Note 1) ns Data output hold time (in relation to WR) (3) (Note 2) ns 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 n × 10 - – 40 [ ns ] ----------------f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 m × 10 - – 10 [ ns ] -----------------f ( BCLK ) 3. 4. n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ. m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1−VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. Calculated according to the BCLK frequency as follows: 9 m × 10 - + 10 [ ns ] -----------------f ( BCLK ) R DBi C m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 81 of 113 M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and when inserting 1 to 3 recovery cycles and accessing external area) Read timing VCC1 = VCC2 = 5 V tcyc BCLK th(BCLK-CS) 2ns(min.) td(BCLK-CS) 25ns(max.) CSi th(BCLK-AD) 2ns(min.) td(BCLK-AD) 25ns(max.) ADi BHE td(BCLK-ALE) 15ns(max.) th(RD-AD) (m × tcyc+0)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-RD) 0ns(min.) td(BCLK-RD) 25ns(max.) RD tac4(RD-DB) (n × t cyc -45)ns(max.) Hi-Z DBi tsu(DB-RD) 40ns(min.) th(RD-DB) 0ns(min.) Write timing tcyc BCLK td(BCLK-CS) 25ns(max.) th(BCLK-CS) 2ns(min.) td(BCLK-AD) 25ns(max.) th(BCLK-AD) 2ns(min.) CSi ADi BHE td(BCLK-ALE) 15ns(max.) th(WR-AD) (m × tcyc -10)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-WR) 0ns(min.) td(BCLK-WR) 25ns(max.) WR, WRL WRH Hi-Z DBi tcyc = td(BCLK-DB) 40ns(max.) 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 5 V y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V Figure 5.19 Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 82 of 113 th(BCLK-DB) 2ns(min.) td(DB-WR) (n × t cyc -40)ns(min.) th(WR-DB) (m × tcyc -10)ns(min.) n: 3 (when 2φ + 3φ) 4 (when 2φ + 4φ or 3φ + 4φ) 5 (when 4φ + 5φ) m: 1 (when 1 recovery cycle inserted ) 2 (when 2 recovery cycles inserted) 3 (when 3 recovery cycles inserted) M16C/63 Group 5.3 5.3.1 5. Electrical Characteristics Electrical Characteristics (VCC1 = VCC2 = 3 V) Electrical Characteristics VCC1 = VCC2 = 3 V (1) Table 5.40 Electrical Characteristics (1) VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = -20 to 85°C/-40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol VOH VOH Parameter High output voltage VOL Min. Typ. Max. P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH = −1 mA VCC1 − 0.5 VCC1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOH = −1 mA VCC2 − 0.5 VCC2 HIGHPOWER IOH = −0.1 mA VCC1 − 0.5 VCC1 LOWPOWER IOH = −50 μA VCC1 − 0.5 VCC1 High output voltage High output voltage VOL Standard Measuring Condition XOUT XCOUT With no load applied 1.5 IOL = 1 mA 0.5 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOL = 1 mA 0.5 HIGHPOWER IOL = 0.1 mA 0.5 LOWPOWER IOL = 50 μA 0.5 Low output voltage XOUT XCOUT With no load applied V V V Low output P6_0 to P6_7, P7_0 to P7_7, voltage P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 Low output voltage Unit 0 V V V VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to KI7, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD, PMC0, PMC1, SCLMM, SDAMM, CEC 0.2 1.0 V VT+-VT- Hysteresis RESET 0.2 1.8 V 4.0 μA IIH High input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE VI = 3 V Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 83 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V Table 5.41 Electrical Characteristics (2) (1) VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol IIL Parameter Low input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, RPULLUP Pull-up resistance P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 RfXIN Feedback resistance XIN RfXCIN Feedback resistance XCIN VRAM RAM retention voltage Measuring Condition Min. Typ. VI = 0 V VI = 0 V In stop mode Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 84 of 113 Standard 50 1.8 100 Max. Unit −4.0 μA 500 kΩ 0.8 MΩ 8 MΩ V M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V Table 5.42 Electrical Characteristics (3) VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified. Symbol ICC Parameter Measuring Condition Power supply current High-speed mode In single-chip, mode, the output pin are open and other pins are VSS 40 MHz on-chip oscillator mode 125 kHz on-chip oscillator mode Low-power mode Wait mode f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) A/D converter stop f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) A/D converter operating (2) f(BCLK) = 20 MHz XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) A/D converter stop f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) PCLKSTP1 = FF (peripheral clock stop) f(BCLK) = 20 MHz (no division) XIN = 20 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) PCLKSTP1 = FF (peripheral clock stop) Main clock stop 40 MHz on-chip oscillator on divide-by-2 (f(BCLK) = 20 MHz) 125 kHz on-chip oscillator stop Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on, no division FMR22 = 1 (slow read mode) f(BCLK) = 32 MHz FMR 22 = FMR23 = 1 (in low-current consumption read mode) On flash memory (1) f(BCLK) = 32 kHz Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on PM25 = 1 (peripheral function clock fC operating) Topr = 25°C Real-time clock operating f(BCLK) = 32 MHz 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator stop PM25 = 0 (peripheral function clock fC stop) Topr = 25°C Min. Standard Typ. Max. Unit 9.5 mA 10.2 mA 9.2 mA 7.9 mA 7.6 mA 9.0 mA 450.0 μA 80.0 μA 5.3 μA 5.0 μA Stop mode Topr = 25°C 2.2 μA During flash memory program f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC1 = 5.0 V 20.0 mA During flash memory erase f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC1 = 5.0 V 30.0 mA Notes: 1. This indicates the memory in which the program to be executed exists. 2. A/D conversion is executed in repeat mode. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 85 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V 5.3.2 Timing Requirements (Peripheral Functions and Others) (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.2.1 Reset Input (RESET Input) Table 5.43 Reset Input (RESET Input) Symbol Standard Parameter Min. RESET input low pulse width tw(RSTL) Max. Unit μs 10 RESET input t w(RTSL) Figure 5.20 5.3.2.2 Table 5.44 Reset Input (RESET Input) External Clock Input External Clock Input (XIN Input) (1) Symbol Standard Parameter Min. Max. Unit tc External clock input cycle time 50 ns tw(H) External clock input high pulse width 20 ns tw(L) External clock input low pulse width 20 tr External clock rise time 9 ns tf External clock fall time 9 ns Note: 1. The condition is VCC1 = VCC2 = 2.7 to 3.0 V. XIN input tr t w(H) tf t w(L) tc Figure 5.21 External Clock Input (XIN Input) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 86 of 113 ns M16C/63 Group 5. Electrical Characteristics VCC1 Timing Requirements (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.2.3 Table 5.45 = VCC2 = 3 V Timer A Input Timer A Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 150 ns tw(TAH) TAiIN input high pulse width 60 ns tw(TAL) TAiIN input low pulse width 60 ns Table 5.46 Timer A Input (Gating Input in Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 600 ns tw(TAH) TAiIN input high pulse width 300 ns tw(TAL) TAiIN input low pulse width 300 ns Table 5.47 Timer A Input (External Trigger Input in One-Shot Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 300 ns tw(TAH) TAiIN input high pulse width 150 ns tw(TAL) TAiIN input low pulse width 150 ns Table 5.48 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and Programmable Output Mode) Symbol Standard Parameter Min. Max. Unit tw(TAH) TAiIN input high pulse width 150 ns tw(TAL) TAiIN input low pulse width 150 ns tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL) Figure 5.22 Timer A Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 87 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 Timing Requirements (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) Table 5.49 = VCC2 = 3 V Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 2 μs tsu(TAIN-TAOUT) TAiOUT input setup time 500 ns tsu(TAOUT-TAIN) TAiIN input setup time 500 ns Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) Figure 5.23 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 88 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 Timing Requirements (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.2.4 Table 5.50 = VCC2 = 3 V Timer B Input Timer B Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 150 ns tw(TBH) TBiIN input high pulse width (counted on one edge) 60 ns tw(TBL) TBiIN input low pulse width (counted on one edge) 60 ns tc(TB) TBiIN input cycle time (counted on both edges) 300 ns tw(TBH) TBiIN input high pulse width (counted on both edges) 120 ns tw(TBL) TBiIN input low pulse width (counted on both edges) 120 ns Table 5.51 Timer B Input (Pulse Period Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 600 ns tw(TBH) TBiIN input high pulse width 300 ns tw(TBL) TBiIN input low pulse width 300 ns Table 5.52 Timer B Input (Pulse Width Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 600 ns tw(TBH) TBiIN input high pulse width 300 ns tw(TBL) TBiIN input low pulse width 300 ns tc(TB) t w(TBH) TBiIN input t w(TBL) Figure 5.24 Timer B Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 89 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 Timing Requirements (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.2.5 Table 5.53 = VCC2 = 3 V Serial Interface Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 300 ns tw(CKH) CLKi input high pulse width 150 ns tw(CKL) CLKi input low pulse width 150 td(C-Q) TXDi output delay time th(C-Q) TXDi hold time tsu(D-C) th(C-D) ns 160 ns 0 ns RXDi input setup time 100 ns RXDi input hold time 90 ns tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi Figure 5.25 5.3.2.6 Table 5.54 Serial Interface External Interrupt INTi Input External Interrupt INTi Input Symbol Standard Parameter Min. Max. Unit tw(INH) INTi input high pulse width 380 ns tw(INL) INTi input low pulse width 380 ns t w(INL) INTi input t w(INH) Figure 5.26 External Interrupt INTi Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 90 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.3 VCC2 = 3 V Timing Requirements (Memory Expansion Mode and Microprocessor Mode) Table 5.55 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard Min. Max. Unit tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns tac2(RD-DB) Data input access time (for setting with wait) (Note 2) ns tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns tac4(RD-DB) Data input access time (for setting with 2 φ + 3 φ or more) (Note 4) ns tsu(DB-RD) Data input setup time 50 ns tsu(RDY-BCLK) RDY input setup time 40 ns tsu(HOLD-BCLK) HOLD input setup time 50 ns th(RD-DB) Data input hold time 0 ns th(BCLK-RDY) RDY input hold time 0 ns th(BCLK-HOLD) HOLD input hold time 0 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 60 [ ns ] --------------------f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n + 0.5 ) × 10 - – 60 [ ns ] ----------------------------------f ( BCLK ) 3. n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) × 10 - – 60 [ ns ] ----------------------------------f ( BCLK ) 4. n is 2 for 2 waits setting, 3 for 3 waits setting. Calculated according to the BCLK frequency as follows: 9 n × 10 - – 60 [ ns ] ----------------f ( BCLK ) n is 3 for 2 φ + 3 φ, 4 for 2 φ + 4 φ, 4 for 3 φ + 4 φ, 5 for 4 φ + 5 φ,. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 91 of 113 M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode VCC1 = VCC2 = 3 V (Effective in wait state setting) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to wait state and no wait state settings) BCLK tsu(HOLD-BCLK) th(BCLK-HOLD) HOLD input HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK-HLDA) td(BCLK-HLDA) Hi−Z Note: 1. These pins are high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register, and PM11 bit in PM1 register. Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.27 Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 92 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V 5.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor Mode) (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.4.1 Table 5.56 In No Wait State Setting Memory Expansion and Microprocessor Modes (in No Wait State Setting) Symbol Measuring Condition Parameter Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns 30 td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time td(BCLK-RD) RD signal output delay time th(BCLK-RD) RD signal output hold time ns 30 ns 0 ns 25 ns 30 ns −4 See Figure 5.28 ns 0 td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) ns 30 ns 0 ns 40 ns th(BCLK-DB) Data output hold time (in relation to BCLK) 0 ns td(DB-WR) Data output delay time (in relation to WR) (Note 1) ns th(WR-DB) Data output hold time (in relation to WR) (3) (Note 2) ns td(BCLK-HLDA) HLDA output delay time (3) 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 40 [ ns ] --------------------f f ( BCLK ) 2. f(BCLK) is 12.5 MHz or less. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1 − VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 93 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Figure 5.28 Ports P0 to P10 Measurement Circuit REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 94 of 113 30 pF M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V Memory Expansion Mode and Microprocessor Mode (in no wait state setting) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns(max.) 0ns(min.) CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns(max.) ADi BHE td(BCLK-ALE) 25ns(max.) 0ns(min.) th(BCLK-ALE) th(RD-AD) -4ns(min.) 0ns(min.) ALE th(BCLK-RD) td(BCLK-RD) 30ns(max.) 0ns(min.) RD tac1(RD-DB) (0.5 × tcyc -60)ns(max.) Hi-Z DBi tsu(DB-RD) th(RD-DB) 50ns(min.) 0ns(min.) Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns(max.) 0ns(min.) CSi tcyc ADi BHE td(BCLK-AD) th(BCLK-AD) 30ns(max.) 0ns(min.) td(BCLK-ALE) 25ns(max.) th(BCLK-ALE) -4ns(min.) th(WR-AD) (0.5 × tcyc -10)ns(min.) td(BCLK-WR) th(BCLK-WR) ALE 30ns(max.) 0ns(min.) WR, WRL, WRH td(BCLK-DB) 40ns(max.) 0ns(min.) Hi-Z DBi td(DB-WR) (0.5 × tcyc -40)ns(min.) tcyc = 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.29 th(BCLK-DB) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 95 of 113 th(WR-DB) (0.5 × tcyc -10)ns(min.) M16C/63 Group 5. Electrical Characteristics VCC1 Switching Characteristics (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.4.2 Table 5.57 = VCC2 = 3 V In 1 to 3 Waits Setting and When Accessing External Area Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When Accessing External Area) Symbol Measuring Condition Parameter Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time td(BCLK-RD) RD signal output delay time th(BCLK-RD) RD signal output hold time 30 30 ns ns -4 ns 30 ns 0 WR signal output delay time WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) td(DB-WR) 0 See Figure 5.28 td(BCLK-WR) Data output hold time (in relation to BCLK) ns 25 th(BCLK-WR) th(BCLK-DB) ns ns 30 ns 0 (3) ns 40 ns 0 ns Data output delay time (in relation to WR) (Note 1) ns th(WR-DB) Data output hold time (in relation to WR) (3) (Note 2) ns td(BCLK-HLDA) HLDA output delay time 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 ( n + 0.5 ) × 10 ------------------------------------ – 40 [ ns ] f ( BCLK ) 2. n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting. When n = 1, f(BCLK) is 12.5 MHz or less. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 ---------------------- – 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value. Hold time of data bus is expressed in t=−CR × ln(1−VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 96 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V Memory Expansion Mode and Microprocessor Mode (in 1 to 3 waits setting and when accessing external area) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns(max.) 0ns(min.) CSi tcyc ADi BHE td(BCLK-AD) th(BCLK-AD) 30ns(max.) 0ns(min.) td(BCLK-ALE) 25ns(max.) th(BCLK-ALE) th(RD-AD) -4ns(min.) 0ns(min.) ALE th(BCLK-RD) td(BCLK-RD) 0ns(min.) 30ns(max.) tac2(RD-DB) {(n+0.5) × t cyc-60}ns(max.) RD tac2(RD-DB) {(n+0.5) × t cyc-60}ns(max.) Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns(min.) 50ns(min.) Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns(max.) 0ns(min.) CSi tcyc th(BCLK-AD) td(BCLK-AD) 0ns(min.) 30ns(max.) ADi BHE td(BCLK-ALE) 25ns(max.) th(BCLK-ALE) th(WR-AD) -4ns(min.) (0.5 × tcyc -10)ns(min.) ALE th(BCLK-WR) td(BCLK-WR) 0ns(min.) 30ns(max.) WR, WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns(max.) 0ns(min.) Hi-Z DBi td(DB-WR) {(n-0.5) × tcyc -40}ns(min.) tcyc = (0.5 × tcyc -10)ns(min.) 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.30 th(WR-DB) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 97 of 113 n: 1 (when 1 wait) 2 (when 2 waits) 3 (when 3 waits) M16C/63 Group 5. Electrical Characteristics VCC1 Switching Characteristics (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) = VCC2 = 3 V 5.3.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus Table 5.58 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When Accessing External Area and Using Multiplexed Bus) (5) Symbol Parameter td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) Measuring Condition Standard Min. Max. 50 Unit ns 0 ns ns th(RD-AD) Address output hold time (in relation to RD) (Note 1) th(WR-AD) Address output hold time (in relation to WR) (Note 1) td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) 0 ns th(RD-CS) Chip select output hold time (in relation to RD) (Note 1) ns th(WR-CS) Chip select output hold time (in relation to WR) (Note 1) ns td(BCLK-RD) RD signal output delay time th(BCLK-RD) RD signal output hold time ns 50 40 0 ns ns ns td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) th(BCLK-DB) Data output hold time (in relation to BCLK) 0 ns td(DB-WR) Data output delay time (in relation to WR) (Note 2) ns th(WR-DB) Data output hold time (in relation to WR) (Note 1) ns td(BCLK-HLDA) HLDA output delay time 40 ns td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) 25 ns 40 See Figure 5.28 0 ns ns 50 ns th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) −4 ns td(AD-ALE) ALE signal output delay time (in relation to Address) (Note 3) ns th(AD-ALE) ALE signal output hold time (in relation to Address) (Note 4) ns td(AD-RD) RD signal output delay from the end of address 0 ns td(AD-WR) WR signal output delay from the end of address 0 ns tdz(RD-AD) Address output floating start time Notes: 1. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) × 10 - – 50 [ ns ] ----------------------------------f ( BCLK ) 3. n is 2 for 2 waits setting, 3 for 3 waits setting. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 40 [ ns ] --------------------f ( BCLK ) 4. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 15 [ ns ] --------------------f ( BCLK ) 5. When using multiplexed bus, set f(BCLK) 12.5 MHz or less. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 98 of 113 8 ns M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 3 V Memory Expansion Mode and Microprocessor Mode (in 2 or 3 waits setting, and when accessing external area and using multiplexed bus ) Read timing BCLK th(BCLK-CS) td(BCLK-CS) th(RD-CS) (0.5 × tcyc -10)ns(min.) tcyc 50ns(max.) 0ns(min.) CSi td(AD-ALE) (0.5 × tcyc -40ns(min.) ADi /DBi th(ALE-AD) (0.5 × tcyc -15ns(min.) Address Address Data input tdz(RD-AD) 8ns(max.) tsu(DB-RD) tac3(RD-DB) {(n-0.5) × tcyc -60}ns(max.) 50ns(min.) th(RD-DB) 0ns(min.) td(AD-RD) td(BCLK-AD) 0ns(min.) 50ns(max.) th(BCLK-AD) 0ns(min.) ADi BHE td(BCLK-ALE) 25ns(max.) th(BCLK-ALE) th(RD-AD) (0.5 × tcyc -10)ns(min.) -4ns(min.) ALE td(BCLK-RD) 40ns(max.) th(BCLK-RD) 0ns(min.) RD Write timing BCLK td(BCLK-CS) tcyc 50ns(max.) th(WR-CS) (0.5 × tcyc -10)ns(min.) th(BCLK-CS) 0ns(min.) CSi td(BCLK-DB) th(BCLK-DB) 50ns(max.) ADi /DBi Address 0ns(min.) Address Data output td(DB-WR) {(n-0.5) × t cyc-50}ns(min.) td(AD-ALE) (0.5 × tcyc -40ns(min.) th(WR-DB) (0.5 × tcyc -10)ns(min.) td(BCLK-AD) th(BCLK-AD) 50ns(max.) ADi BHE td(BCLK-ALE) 25ns(max.) 0ns(min.) th(BCLK-ALE) td(AD-WR) -4ns(min.) 0ns(min.) th(WR-AD) (0.5 × tcyc -10)ns(min.) ALE th(BCLK-WR) td(BCLK-WR) 40ns(max.) 0ns(min.) WR,WRL, WRH tcyc = 1 f(BCLK) Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.31 Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 99 of 113 n: 2 (when 2 waits) 3 (when 3 waits) M16C/63 Group 5. Electrical Characteristics VCC1 Switching Characteristics (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.3.4.4 Table 5.59 = VCC2 = 3 V In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area) Symbol Measuring Condition Parameter Standard Min. Max. Unit td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns th(RD-AD) Address output hold time (in relation to RD) 0 ns th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time th(BCLK-ALE) ALE signal output hold time 30 30 ns ns -4 th(BCLK-RD) RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) td(DB-WR) 0 See Figure 5.14 RD signal output delay time Data output hold time (in relation to BCLK) ns 25 td(BCLK-RD) th(BCLK-DB) ns ns 30 ns 0 ns 30 ns 0 (3) ns 40 ns 0 ns Data output delay time (in relation to WR) (Note 1) ns th(WR-DB) Data output hold time (in relation to WR) (3) (Note 2) ns td(BCLK-HLDA) HLDA output delay time 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 (----------------------------------n – 0.5 ) × 10 - – 40 [ ns ] f ( BCLK ) 2. n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ. Calculated according to the BCLK frequency as follows: 9 0.5 × 10 - – 10 [ ns ] --------------------f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1 − VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 100 of 113 R DBi C M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and when accessing external area) Read timing VCC1 = VCC2 = 3 V tcyc BCLK th(BCLK-CS) 0ns(min.) td(BCLK-CS) 30ns(max.) CSi td(BCLK-AD) 30ns(max.) th(BCLK-AD) 0ns(min.) ADi BHE td(BCLK-ALE) 25ns(max.) th(RD-AD) 0ns(min.) th(BCLK-ALE) -4ns(min.) ALE td(BCLK-RD) 30ns(max.) th(BCLK-RD) 0ns(min.) RD tac4(RD-DB) (n × t cyc-60)ns(max.) Hi-Z DBi tsu(DB-RD) 50ns(min.) Write timing th(RD-DB) 0ns(min.) tcyc BCLK td(BCLK-CS) 30ns(max.) th(BCLK-CS) 0ns(min.) td(BCLK-AD) 30ns(max.) th(BCLK-AD) 0ns(min.) CSi ADi BHE td(BCLK-ALE) 25ns(max.) th(WR-AD) (0.5 × t cyc -10)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-WR) 0ns(min.) td(BCLK-WR) 30ns(max.) WR, WRL WRH td(BCLK-DB) 40ns(min.) Hi-Z DBi tcyc = 1 td(DB-WR) {(n-0.5) × tcyc -40}ns(min.) f(BCLK) Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.32 th(BCLK-DB) 0ns(min.) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 101 of 113 n: 3 (when 2φ + 3φ) 4 (when 2φ + 4φ or 3φ + 4φ) 5 (when 4φ + 5φ) th(WR-DB) (0.5 × t cyc -10)ns(min.) M16C/63 Group 5. Electrical Characteristics VCC1 Switching Characteristics (VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) = VCC2 = 3 V 5.3.4.5 In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External Area Table 5.60 Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External Area) Symbol Measuring Condition Parameter td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (in relation to BCLK) th(RD-AD) th(WR-AD) td(BCLK-CS) Chip select output delay time th(BCLK-CS) Chip select output hold time (in relation to BCLK) td(BCLK-ALE) ALE signal output delay time Standard Min. Max. 30 ns 0 ns Address output hold time (in relation to RD) (Note 4) ns Address output hold time (in relation to WR) (Note 2) ALE signal output hold time RD signal output delay time th(BCLK-RD) RD signal output hold time td(BCLK-WR) WR signal output delay time th(BCLK-WR) WR signal output hold time td(BCLK-DB) Data output delay time (in relation to BCLK) ns ns 30 ns 0 ns 30 ns 0 Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) HLDA output delay time ns -4 th(BCLK-DB) Data output hold time (in relation to WR) 0 See Figure 5.14 td(DB-WR) td(BCLK-HLDA) ns 25 th(BCLK-ALE) th(WR-DB) ns 30 td(BCLK-RD) (3) (3) ns 40 ns 0 ns (Note 1) ns (Note 2) ns 40 ns Notes: 1. Calculated according to the BCLK frequency as follows: 9 n × 10 - – 40 [ ns ] ----------------f ( BCLK ) 2. 9 4. n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ. Calculated according to the BCLK frequency as follows: m × 10 ------------------- – 10 [ ns ] f ( BCLK ) 3. Unit m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR × ln(1 − VOL/VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output low level is t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2) = 6.7 ns. Calculated according to the BCLK frequency as follows: 9 m × 10 - + 10 [ ns ] -----------------f ( BCLK ) R DBi C m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and 3 when 3 recovery cycles are inserted. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 102 of 113 M16C/63 Group 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (in wait state setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and when inserting 1 to 3 recovery cycles and accessing external area) Read timing VCC1 = VCC2 = 3 V tcyc BCLK th(BCLK-CS) 0ns(min.) td(BCLK-CS) 30ns(max.) CSi th(BCLK-AD) 0ns(min.) td(BCLK-AD) 30ns(max.) ADi BHE td(BCLK-ALE) 25ns(max.) th(RD-AD) (m × tcyc+0)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-RD) 0ns(min.) td(BCLK-RD) 30ns(max.) RD tac4(RD-DB) (n × t cyc -60)ns(max.) Hi-Z DBi tsu(DB-RD) 50ns(min.) th(RD-DB) 0ns(min.) Write timing tcyc BCLK td(BCLK-CS) 30ns(max.) th(BCLK-CS) 0ns(min.) td(BCLK-AD) 30ns(max.) th(BCLK-AD) 0ns(min.) CSi ADi BHE td(BCLK-ALE) 25ns(max.) th(WR-AD) (m × tcyc -10)ns(min.) th(BCLK-ALE) -4ns(min.) ALE th(BCLK-WR) 0ns(min.) td(BCLK-WR) 30ns(max.) WR, WRL WRH Hi-Z DBi tcyc = td(BCLK-DB) 40ns(max.) 1 td(DB-WR) (n × t cyc -40)ns(min.) th(WR-DB) (m × tcyc -10)ns(min.) f(BCLK) Measuring conditions y VCC1 = VCC2 = 3 V y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V Figure 5.33 th(BCLK-DB) 0ns(min.) Timing Diagram REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 103 of 113 n: 3 (when 2φ + 3φ) 4 (when 2φ + 4φ or 3φ + 4φ) 5 (when 4φ + 5φ) m: 1 (when 1 recovery cycle inserted ) 2 (when 2 recovery cycles inserted) 3 (when 3 recovery cycles inserted) M16C/63 Group 5.4 5.4.1 5. Electrical Characteristics Electrical Characteristics (VCC1 = VCC2 = 1.8 V) Electrical Characteristics VCC1 = VCC2 = 1.8 V (1) Table 5.61 Electrical Characteristics (1) VCC1 = VCC2 = 1.8 to 2.7 V, VSS = 0 V at Topr = -20 to 85°C/-40 to 85°C, f(BCLK) = 5 MHz unless otherwise specified. Symbol VOH VOH Parameter High output voltage VOL Min. Typ. Max. P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH = −1 mA VCC1 − 0.5 VCC1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOH = −1 mA VCC2 − 0.5 VCC2 HIGHPOWER IOH = −0.1 mA VCC1 − 0.5 VCC1 LOWPOWER IOH = −50 μA VCC1 − 0.5 VCC1 High output voltage High output voltage VOL Standard Measuring Condition XOUT XCOUT With no load applied 1.5 IOL = 1 mA 0.5 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 IOL = 1 mA 0.5 HIGHPOWER IOL = 0.1 mA 0.5 LOWPOWER IOL = 50 μA 0.5 Low output voltage XOUT XCOUT With no load applied V V V Low output P6_0 to P6_7, P7_0 to P7_7, voltage P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 Low output voltage Unit 0 V V V VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to KI7, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD, PMC0, PMC1, SCLMM, SDAMM, CEC 0.02 0.1 V VT+-VT- Hysteresis RESET 0.05 0.15 V 2.0 μA IIH High input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE VI = 3 V Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 104 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 1.8 V Table 5.62 Electrical Characteristics (2) (1) VCC1 = VCC2 = 1.8 to 2.7 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 5 MHz unless otherwise specified. Symbol IIL Parameter Low input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, RPULLUP Pull-up resistance P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 RfXIN Feedback resistance XIN RfXCIN Feedback resistance XCIN VRAM RAM retention voltage Measuring Condition Min. Typ. VI = 0 V VI = 0 V Note: 1. When VCC1 ≠ VCC2, refer to 5 V, 3 V, or 1.8 V standard depending on the voltage. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 105 of 113 Standard 70 1.8 140 Max. Unit −2.0 μA 700 kΩ 0.8 MΩ 8 MΩ V M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 1.8 V Table 5.63 Electrical Characteristics (3) VCC1 = VCC2 = 1.8 to 2.7 V, VSS = 0 V at Topr = −20 to 85°C/−40 to 85°C, f(BCLK) = 5 MHz unless otherwise specified. Symbol ICC Parameter Measuring Condition Power supply current High-speed mode In single-chip, mode, the output pin are open and other pins are VSS 40 MHz on-chip oscillator mode 125 kHz on-chip oscillator mode Low-power mode Wait mode Stop mode f(BCLK) = 5 MHz (no division) XIN = 5 MHz (square wave), 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) A/D converter stop f(BCLK) = 5 MHz (no division), XIN = 5 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) A/D converter operating (2) f(BCLK) = 5 MHz XIN = 5 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) A/D converter stop f(BCLK) = 5 MHz (no division) XIN = 5 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 1 (drive capacity High) PCLKSTP1 = FF (peripheral clock stop) f(BCLK) = 5 MHz (no division) XIN = 5 MHz (square wave) 125 kHz on-chip oscillator stop CM15 = 0 (drive capacity Low) PCLKSTP1 = FF (peripheral clock stop) Main clock stop 40 MHz on-chip oscillator on, divide-by-8 (f(BCLK) = 5 MHz) 125 kHz on-chip oscillator stop Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on, no division FMR22 = 1 (slow read mode) f(BCLK) = 32 MHz FMR 22 = FMR23 = 1 (in low-current consumption read mode) on flash memory (1) f(BCLK) = 32 kHz Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator on PM25 = 1 (peripheral function clock fC operating) Topr = 25°C Real-time clock operating f(BCLK) = 32 MHz Main clock stop 40 MHz on-chip oscillator stop 125 kHz on-chip oscillator stop PM25 = 0 (peripheral function clock fC stop) Topr = 25°C Topr = 25°C Notes: 1. This indicates the memory in which the program to be executed exists 2. A/D conversion is executed in repeat mode. REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 106 of 113 Min. Standard Typ. Max. Unit 2.6 mA 3.3 mA 2.6 mA 2.2 mA 2.2 mA 2.8 mA 450.0 μA 80.0 μA 5.3 μA 5.0 μA 2.2 μA M16C/63 Group 5. Electrical Characteristics VCC1 = VCC2 = 1.8 V 5.4.2 Timing Requirements (Peripheral Functions and Others) (VCC1 = VCC2 = 1.8 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.4.2.1 Reset Input (RESET Input) Table 5.64 Reset Input (RESET Input) Symbol Standard Parameter Min. RESET input low pulse width tw(RSTL) Max. Unit μs 10 RESET input t w(RTSL) Figure 5.34 5.4.2.2 Table 5.65 Reset Input (RESET Input) External Clock Input External Clock Input (XIN Input) (1) Symbol Standard Parameter Min. Max. Unit tc External clock input cycle time 100 ns tw(H) External clock input high pulse width 40 ns tw(L) External clock input low pulse width 40 tr External clock rise time 9 ns tf External clock fall time 9 ns Note: 1. The condition is VCC1 = VCC2 = 1.8 to 2.7 V. XIN input tr t w(H) tf t w(L) tc Figure 5.35 External Clock Input (XIN Input) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 107 of 113 ns M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 1.8 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.4.2.3 Table 5.66 VCC2 = 1.8 V Timer A Input Timer A Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 500 ns tw(TAH) TAiIN input high pulse width 200 ns tw(TAL) TAiIN input low pulse width 200 ns Table 5.67 Timer A Input (Gating Input in Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 1000 ns tw(TAH) TAiIN input high pulse width 500 ns tw(TAL) TAiIN input low pulse width 500 ns Table 5.68 Timer A Input (External Trigger Input in One-Shot Timer Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 800 ns tw(TAH) TAiIN input high pulse width 400 ns tw(TAL) TAiIN input low pulse width 400 ns Table 5.69 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and Programmable Output Mode) Symbol Standard Parameter Min. Max. Unit tw(TAH) TAiIN input high pulse width 400 ns tw(TAL) TAiIN input low pulse width 400 ns tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL) Figure 5.36 Timer A Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 108 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 1.8 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) Table 5.70 VCC2 = 1.8 V Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TA) TAiIN input cycle time 3 μs tsu(TAIN-TAOUT) TAiOUT input setup time 800 ns tsu(TAOUT-TAIN) TAiIN input setup time 800 ns Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) Figure 5.37 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 109 of 113 M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 1.8 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.4.2.4 Table 5.71 VCC2 = 1.8 V Timer B Input Timer B Input (Counter Input in Event Counter Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 300 ns tw(TBH) TBiIN input high pulse width (counted on one edge) 120 ns tw(TBL) TBiIN input low pulse width (counted on one edge) 120 ns tc(TB) TBiIN input cycle time (counted on both edges) 600 ns tw(TBH) TBiIN input high pulse width (counted on both edges) 240 ns tw(TBL) TBiIN input low pulse width (counted on both edges) 240 ns Table 5.72 Timer B Input (Pulse Period Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 1000 ns tw(TBH) TBiIN input high pulse width 500 ns tw(TBL) TBiIN input low pulse width 500 ns Table 5.73 Timer B Input (Pulse Width Measurement Mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high pulse width 500 ns tw(TBL) TBiIN input low pulse width 500 ns 1000 tc(TB) t w(TBH) TBiIN input t w(TBL) Figure 5.38 Timer B Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 110 of 113 ns M16C/63 Group 5. Electrical Characteristics VCC1 = Timing Requirements (VCC1 = VCC2 = 1.8 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified) 5.4.2.5 Table 5.74 VCC2 = 1.8 V Serial Interface Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 800 ns tw(CKH) CLKi input high pulse width 400 ns tw(CKL) CLKi input low pulse width 400 td(C-Q) TXDi output delay time th(C-Q) TXDi hold time tsu(D-C) th(C-D) ns 240 ns 0 ns RXDi input setup time 200 ns RXDi input hold time 90 ns tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi Figure 5.39 5.4.2.6 Table 5.75 Serial Interface External Interrupt INTi Input External Interrupt INTi Input Symbol Standard Parameter Min. Max. Unit tw(INH) INTi input high pulse width 1000 tw(INL) INTi input low pulse width 1000 tr(INT) INTi input rising time 100 μs tf(INT) INTi input falling time 100 μs t w(INL) INTi input t w(INH) Figure 5.40 External Interrupt INTi Input REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 111 of 113 ns ns M16C/63 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions The information on the latest package dimensions or packaging may be obtained from “Packages“ on the Renesas Technology Website. JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JD-B Previous Code 100P6F-A MASS[Typ.] 1.8g HD *1 D 80 51 81 50 HE *2 E NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. ZE Reference Symbol 100 31 30 Index mark c F A1 A ZD A2 1 L *3 e y JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A bp x Detail F Previous Code 100P6Q-A / FP-100U / FP-100UV D E A2 HD HE A A1 bp c e x y ZD ZE L Dimension in Millimeters Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0° 10° 0.65 0.13 0.10 0.575 0.825 0.4 0.6 0.8 MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Dimension in Millimeters Symbol c E *2 HE b1 D E A2 HD HE A A1 bp b1 c c1 100 26 1 ZE Terminal cross section 25 Index mark ZD y e *3 bp A1 c A A2 F L x L1 Detail F REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 112 of 113 e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 M16C/63 Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA100-5.5x5.5-0.5 RENESAS Code PTLG0100KA-A Previous Code 100F0M MASS[Typ.] 0.1g b1 D S w S B w S A AB b ZD A S AB e A e K J H G B E F E D C B ZE A y S x4 2 3 4 5 6 7 Index mark v S (Laser mark) JEITA Package Code P-LQFP80-12x12-0.50 1 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A Index mark 8 9 10 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y ZD ZE Nom Max 5.5 5.5 0.15 0.20 1.05 0.5 0.21 0.25 0.29 0.29 0.34 0.39 0.08 0.10 0.5 0.5 MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 40 61 bp E c *2 HE c1 b1 Reference Dimension in Millimeters Symbol ZE Terminal cross section 80 21 1 20 ZD Index mark bp c A *3 A1 y e A2 F L x L1 Detail F REJ03B0271-0100 Rev.1.00 Sep 15, 2009 Page 113 of 113 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 REVISION HISTORY Rev. Date 0.30 0.40 Jul 15, 2009 Aug 18, 2009 0.41 Aug 25, 2009 1.00 Sep 15, 2009 Page 3 6 7 12 13 14 107 112 6 7 52 M16C/63 Group Datasheet Description Summary First Edition issued. Table 1.2 “Specifications for the 100-Pin Package (2/2)” partially modified Table 1.5 “Product List” partially modified Figure 1.1 “Part No., with Memory Size and Package” partially modified Figure 1.7 “Pin Assignment for the 100-Pin Package” added Table 1.6 “Pin Names for the 100-Pin Package (1/2)” partially modified Table 1.7 “Pin Names for the 100-Pin Package (2/2)” partially modified Table 5.65 “External Clock Input (XIN Input)” partially modified Appendix 1. “Package Dimensions” PTLG0100KA-A added Table 1.5 “Product List” Part No. partially modified Figure 1.3 “Marking Diagram (Top View) (2/2)” added Table 5.6 “A/D Conversion Characteristics (1/2)” note 3 added All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation. HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. A-1 Sales Strategic Planning Div. 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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2009. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2