RAiO RA8808 - Orient Display

RAiO
RA8808
128x64 Driver
for Dot Matrix LCD
Specification
Version 1.2
December 15, 2009
RAiO Technology Inc.
©Copyright RAiO Technology Inc. 2009
RAiO TECHNOLOGY INC.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Update History
Version
Date
1.0
March 26, 2009
1.1
October 23, 2009
1.2
December 15, 2009
RAiO TECHNOLOGY INC.
Description
Preliminary version
Update Section 6-3-3 LCD Driver
1. Add Section 6-3-4 Temperature Compensation.
2. Updata Figure 8-2、Figure 8-3.
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RA8808
Preliminary Version 1.2
Chapter
128x64 Driver for Dot Matrix LCD
Contents
Page
1. Overview ................................................................................................... 5
2. Features .................................................................................................... 5
3. Pin Configuration ..................................................................................... 5
3-1 Block Diagram ...................................................................................................... 5
3-2 PAD Diagram ........................................................................................................ 6
3-3 PAD Center Coordinates ..................................................................................... 7
4. Pin Description ....................................................................................... 12
4-1
4-2
4-3
4-4
4-5
MPU Interface ..................................................................................................... 12
LCD Panel Interface ........................................................................................... 14
Clock ................................................................................................................... 15
Power .................................................................................................................. 15
MISC .................................................................................................................... 16
5. Electrical Characteristics ...................................................................... 17
5-1 Maximum Absolute Limit................................................................................... 17
5-2 DC Characteristics ............................................................................................. 17
5-3 AC Characteristics ............................................................................................. 18
6. Operating Principles and Methods ....................................................... 21
6-1 MPU Interface ..................................................................................................... 21
6-1-1
6-1-2
6-1-3
6-1-4
6800 Interface....................................................................................................................... 21
8080 Interface....................................................................................................................... 22
3-Wire SPI Interface............................................................................................................. 23
IIC Interface .......................................................................................................................... 24
6-2 RC Oscillator ...................................................................................................... 26
6-3 LCD Driver and Power Supply Circuit .............................................................. 26
6-3-1
6-3-2
6-3-3
6-3-4
Booster Circuit..................................................................................................................... 26
Voltage Follower.................................................................................................................. 28
LCD Driver ............................................................................................................................ 28
Temperature Compensation...............................................................................................28
6-4 I/O Buffer............................................................................................................. 29
6-4-1 In Parallel Mode ................................................................................................................... 29
6-4-2 In Serial Mode ...................................................................................................................... 29
6-5 Input Register ..................................................................................................... 29
6-5-1 In Parallel Mode ................................................................................................................... 29
6-5-2 In Serial Mode ...................................................................................................................... 29
6-6 Output Register .................................................................................................. 30
6-6-1 In Parallel Mode ................................................................................................................... 30
6-6-2 In Serial Mode ...................................................................................................................... 30
6-7 Reset ................................................................................................................... 31
6-8 Busy Flag ............................................................................................................ 31
6-9 Display ON/OFF Flip – Flop ............................................................................... 32
6-10 X Page Register ................................................................................................ 32
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-11 Y Address Counter ........................................................................................... 32
6-12 Display Data RAM............................................................................................. 32
6-13 Display Start Line Register .............................................................................. 32
7. Display Control Instruction ................................................................... 33
7-1
7-2
7-3
7-4
7-5
7-6
7-7
Display ON/OFF .................................................................................................. 33
Set Address (Y Address) ................................................................................... 34
Set Page (X Address) ......................................................................................... 34
Display Start Line (Z Address) .......................................................................... 34
Status Read......................................................................................................... 34
Write Display Data.............................................................................................. 35
Read Display Data .............................................................................................. 35
8. Application Circuit ................................................................................. 36
8-1 Timing Diagram (1/64 DUTY) ............................................................................. 36
8-2 LCD Panel Interface Application Circuit........................................................... 37
8-2-1 128X64 .................................................................................................................................. 37
8-2-2 256X64 .................................................................................................................................. 38
Appendix A. COG/Module Application..................................................... 39
Appendix B. ITO ......................................................................................... 40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
1. Overview
The RA8808 is a LCD driver LSI with 128(Segment) x 64(Common) driver output for dot matrix liquid
crystal graphic display systems. This device consists of the display RAM,128-bit segment drivers, 64-bit
common drivers and decoder logic. It has the internal display RAM for storing the display data
transferred from an 8-bit 8080/6800 micro controller or 3-wire-SPI/IIC controller and generates the dot
matrix liquid crystal driving signals corresponding to stored data.
2. Features
‹
‹
‹
‹
‹
Dot matrix LCD segment driver with 128
channel output, and common driver with
64 channel output
Internal timing generator circuit for
dynamic display
Selection of master/slave mode for
combine two RA8808 controller to support
256x64 dot Matrix
Applicable LCD common duty: 1/48, 1/64
Support 6800/8080 8-bit parallel MPU
interface
Support 3-wires SPI and IIC serial MPU
interface.
Two 512 bytes (4096-bits) Display SRAM
LCD driving voltage: 8V ~17V
Built-in 2X~4X Voltage Booster and
Voltage Follower
Power supply voltage: +2.7V ~ 5.5V
High voltage CMOS process
Bare gold bump chip available
‹
‹
‹
‹
‹
‹
‹
3. Pin Configuration
3-1 Block Diagram
M CL FRM
DB7~0
RS
E
RW
Register
Block
Scan
Block
CS1
CS2B
CS3
CS4B
PS
MPUIF
Block
MODE
MS
512x8
Display RAM
A
SEG
Drivers
SEG127~0
COM
Drivers
COM63~0
512x8
Display RAM
B
DS
SHL
ADC
RSTB
RA
RB
Power Circuit &
Test
RC
Oscillator
CLK_OUT TEST[2~0]
VOUT
V[4:0]A
C[2:1]N
C[3:1]P
V[4:0]
Figure 3-1 : RA8808 Block Diagram
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COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
P1
B
Chip Size
Bump Size
Bump Pitch
Bump Height
B
P1
C
RAiO TECHNOLOGY INC.
A
B
61
A
70
69
68
6/40
B
P2
A
B
A
PT6: PAD 75~76
PT7: PAD 108~109
15 ± 3 μm
9166 μm x 1171 μm
PAD 1~16, PAD 126~141 (COM Pads)
PAD 142~301 (SEG/COM Pads)
PAD 17~125 (MCU/Power Pads)
Symbol
尺寸與座標
A
20 μm
B
25 μm
C
75 μm
P1
(-4078.1, -259.57)
P2
(4056, 198.84)
PT1 : PAD 1~16, PAD 126~141, PAD 142~157, PAD 158~178,
PAD 179~199, PAD 200~221, PAD 222~243 , PAD 244~264,
PAD 265~285, PAD 286~301
48 μm
PT2 : PAD 17~55, PAD 56~65, PAD 66~75, PAD 76~108,
PAD 76~108, PAD 109~125
72 μm
PT3 : PAD 55~56
PT4: PAD 65~66
76.6 μm
77.02 μm
PT5: PAD 157~158, PAD 178~179, PAD 199~200, PAD 221~222,
PAD 243~244, PAD 264~265, PAD 285~286
96 μm
125
124
123
122
121
120
119
118
117
116
Y
115
114
113
112
111
110
PT6
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
Preliminary Version 1.2
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
PT4
76
75
(0,0)
74
Logo
73
72
RA8808
71
RA8808
67
RAiO
66
65
64
63
PT3
62
9166 x 1171
60
59
58
57
PT2
56
55
54
53
52
51
50
49
48
47
46
45
44
PT1
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRM
CL
M
CLK_OUT
VDD
MS
GND
VDD
MODE
PS
ADC
VDD
GND
CS4B
CS3
VDD
RSTB
RS
E
RW
GND
CS2B
CS1
VDD
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
VDD
VDD
VDDP
VDDP
VDDP
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AGND
GNDP
GNDP
GNDP
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
C3P
C3P
C3P
C3P
C1N
C1N
C1N
C1N
C1P
C1P
C1P
C1P
C2N
C2N
C2N
C2N
C2P
C2P
C2P
C2P
V0A
V1A
V2A
V3A
V4A
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VDD
VDD
VDD
SHL
GND
DS
GND
TEST0
TEST1
TEST2
RA
RB
M
CL
FRM
RA8808
128x64 Driver for Dot Matrix LCD
3-2 PAD Diagram
Top View
X
PT5
PT7
P2
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
Figure 3-2 : RA8808 PAD Diagram
Table 3-1 : Bump Size and Pitch
66 μm x 22 μm
22 μm x 66 μm
37 μm x 46 μm
102.3 μm
112 μm
B
C
Figure 3-3 : Fixed Point Dimension
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COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
3-3 PAD Center Coordinates
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
1
COM47
-4439.51
384.62
32
VDD
-2848
-464.37
2
COM46
-4439.51
336.62
33
RSTB
-2776
-464.37
3
COM45
-4439.51
288.62
34
RS
-2704
-464.37
4
COM44
-4439.51
240.62
35
E
-2632
-464.37
5
COM43
-4439.51
192.62
36
RW
-2560
-464.37
6
COM42
-4439.51
144.62
37
GND
-2488
-464.37
7
COM41
-4439.51
96.62
38
CS2B
-2416
-464.37
8
COM40
-4439.51
48.62
39
CS1
-2344
-464.37
9
COM39
-4439.51
0.62
40
VDD
-2272
-464.37
10
COM38
-4439.51
-47.38
41
GND
-2200
-464.37
11
COM37
-4439.51
-95.38
42
DB0
-2128
-464.37
12
COM36
-4439.51
-143.38
43
DB1
-2056
-464.37
13
COM35
-4439.51
-191.38
44
DB2
-1984
-464.37
14
COM34
-4439.51
-239.38
45
DB3
-1912
-464.37
15
COM33
-4439.51
-287.38
46
DB4
-1840
-464.37
16
COM32
-4439.51
-335.38
47
DB5
-1768
-464.37
17
FRM
-3928
-464.37
48
DB6
-1696
-464.37
18
CL
-3856
-464.37
49
DB7
-1624
-464.37
19
M
-3784
-464.37
50
VDD
-1552
-464.37
20
CLK_OUT
-3712
-464.37
51
VDD
-1480
-464.37
21
VDD
-3640
-464.37
52
VDD
-1408
-464.37
22
MS
-3568
-464.37
53
VDDP
-1336
-464.37
23
GND
-3496
-464.37
54
VDDP
-1264
-464.37
24
VDD
-3424
-464.37
55
VDDP
-1192
-464.37
25
MODE
-3352
-464.37
56
AVDD
-1115.4
-464.37
26
PS
-3280
-464.37
57
AVDD
-1043.4
-464.37
27
ADC
-3208
-464.37
58
AVDD
-971.4
-464.37
28
VDD
-3136
-464.37
59
AVDD
-899.4
-464.37
29
GND
-3064
-464.37
60
AVDD
-827.4
-464.37
30
CS4B
-2992
-464.37
61
AGND
-755.4
-464.37
31
CS3
-2920
-464.37
62
AGND
-683.4
-464.37
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
63
AGND
-611.4
-464.37
94
C2P
1655.92
-464.37
64
AGND
-539.4
-464.37
95
C2P
1727.92
-464.37
65
AGND
-467.4
-464.37
96
V0A
1799.92
-464.37
66
GNDP
-390.38
-464.37
97
V1A
1871.92
-464.37
67
GNDP
-318.38
-464.37
98
V2A
1943.92
-464.37
68
GNDP
-246.38
-464.37
99
V3A
2015.92
-464.37
69
GND
-174.38
-464.37
100
V4A
2087.92
-464.37
70
GND
-102.38
-464.37
101
V4
2159.92
-464.37
71
GND
-30.38
-464.37
102
V4
2231.92
-464.37
72
VOUT
41.62
-464.37
103
V3
2303.92
-464.37
73
VOUT
113.62
-464.37
104
V3
2375.92
-464.37
74
VOUT
185.62
-464.37
105
V2
2447.92
-464.37
75
VOUT
257.62
-464.37
106
V2
2519.92
-464.37
76
C3P
359.92
-464.37
107
V1
2591.92
-464.37
77
C3P
431.92
-464.37
108
V1
2663.92
-464.37
78
C3P
503.92
-464.37
109
V0
2775.92
-464.37
79
C3P
575.92
-464.37
110
V0
2847.92
-464.37
80
C1N
647.92
-464.37
111
VDD
2919.92
-464.37
81
C1N
719.92
-464.37
112
VDD
2991.92
-464.37
82
C1N
791.92
-464.37
113
VDD
3063.92
-464.37
83
C1N
863.92
-464.37
114
SHL
3135.92
-464.37
84
C1P
935.92
-464.37
115
GND
3207.92
-464.37
85
C1P
1007.92
-464.37
116
DS
3279.92
-464.37
86
C1P
1079.92
-464.37
117
GND
3351.92
-464.37
87
C1P
1151.92
-464.37
118
TEST0
3423.92
-464.37
88
C2N
1223.92
-464.37
119
TEST1
3495.92
-464.37
89
C2N
1295.92
-464.37
120
TEST2
3567.92
-464.37
90
C2N
1367.92
-464.37
121
RA
3639.92
-464.37
91
C2N
1439.92
-464.37
122
RB
3711.92
-464.37
92
C2P
1511.92
-464.37
123
M
3783.92
-464.37
93
C2P
1583.92
-464.37
124
CL
3855.92
-464.37
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
125
FRM
3927.92
-464.37
156
COM30
3312
442.07
126
COM0
4439.51
-335.38
157
COM31
3264
442.07
127
COM1
4439.51
-287.38
158
SEG0
3168
442.07
128
COM2
4439.51
-239.38
159
SEG1
3120
442.07
129
COM3
4439.51
-191.38
160
SEG2
3072
442.07
130
COM4
4439.51
-143.38
161
SEG3
3024
442.07
131
COM5
4439.51
-95.38
162
SEG4
2976
442.07
132
COM6
4439.51
-47.38
163
SEG5
2928
442.07
133
COM7
4439.51
0.62
164
SEG6
2880
442.07
134
COM8
4439.51
48.62
165
SEG7
2832
442.07
135
COM9
4439.51
96.62
166
SEG8
2784
442.07
136
COM10
4439.51
144.62
167
SEG9
2736
442.07
137
COM11
4439.51
192.62
168
SEG10
2688
442.07
138
COM12
4439.51
240.62
169
SEG11
2640
442.07
139
COM13
4439.51
288.62
170
SEG12
2592
442.07
140
COM14
4439.51
336.62
171
SEG13
2544
442.07
141
COM15
4439.51
384.62
172
SEG14
2496
442.07
142
COM16
3984
442.07
173
SEG15
2448
442.07
143
COM17
3936
442.07
174
SEG16
2400
442.07
144
COM18
3888
442.07
175
SEG17
2352
442.07
145
COM19
3840
442.07
176
SEG18
2304
442.07
146
COM20
3792
442.07
177
SEG19
2256
442.07
147
COM21
3744
442.07
178
SEG20
2208
442.07
148
COM22
3696
442.07
179
SEG21
2112
442.07
149
COM23
3648
442.07
180
SEG22
2064
442.07
150
COM24
3600
442.07
181
SEG23
2016
442.07
151
COM25
3552
442.07
182
SEG24
1968
442.07
152
COM26
3504
442.07
183
SEG25
1920
442.07
153
COM27
3456
442.07
184
SEG26
1872
442.07
154
COM28
3408
442.07
185
SEG27
1824
442.07
155
COM29
3360
442.07
186
SEG28
1776
442.07
RAiO TECHNOLOGY INC.
9/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
187
SEG29
1728
442.07
218
SEG60
192
442.07
188
SEG30
1680
442.07
219
SEG61
144
442.07
189
SEG31
1632
442.07
220
SEG62
96
442.07
190
SEG32
1584
442.07
221
SEG63
48
442.07
191
SEG33
1536
442.07
222
SEG64
-48
442.07
192
SEG34
1488
442.07
223
SEG65
-96
442.07
193
SEG35
1440
442.07
224
SEG66
-144
442.07
194
SEG36
1392
442.07
225
SEG67
-192
442.07
195
SEG37
1344
442.07
226
SEG68
-240
442.07
196
SEG38
1296
442.07
227
SEG69
-288
442.07
197
SEG39
1248
442.07
228
SEG70
-336
442.07
198
SEG40
1200
442.07
229
SEG71
-384
442.07
199
SEG41
1152
442.07
230
SEG72
-432
442.07
200
SEG42
1056
442.07
231
SEG73
-480
442.07
201
SEG43
1008
442.07
232
SEG74
-528
442.07
202
SEG44
960
442.07
233
SEG75
-576
442.07
203
SEG45
912
442.07
234
SEG76
-624
442.07
204
SEG46
864
442.07
235
SEG77
-672
442.07
205
SEG47
816
442.07
236
SEG78
-720
442.07
206
SEG48
768
442.07
237
SEG79
-768
442.07
207
SEG49
720
442.07
238
SEG80
-816
442.07
208
SEG50
672
442.07
239
SEG81
-864
442.07
209
SEG51
624
442.07
240
SEG82
-912
442.07
210
SEG52
576
442.07
241
SEG83
-960
442.07
211
SEG53
528
442.07
242
SEG84
-1008
442.07
212
SEG54
480
442.07
243
SEG85
-1056
442.07
213
SEG55
432
442.07
244
SEG86
-1152
442.07
214
SEG56
384
442.07
245
SEG87
-1200
442.07
215
SEG57
336
442.07
246
SEG88
-1248
442.07
216
SEG58
288
442.07
247
SEG89
-1296
442.07
217
SEG59
240
442.07
248
SEG90
-1344
442.07
RAiO TECHNOLOGY INC.
10/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
249
SEG91
-1392
442.07
280
SEG122
-2928
442.07
250
SEG92
-1440
442.07
281
SEG123
-2976
442.07
251
SEG93
-1488
442.07
282
SEG124
-3024
442.07
252
SEG94
-1536
442.07
283
SEG125
-3072
442.07
253
SEG95
-1584
442.07
284
SEG126
-3120
442.07
254
SEG96
-1632
442.07
285
SEG127
-3168
442.07
255
SEG97
-1680
442.07
286
COM63
-3264
442.07
256
SEG98
-1728
442.07
287
COM62
-3312
442.07
257
SEG99
-1776
442.07
288
COM61
-3360
442.07
258
SEG100
-1824
442.07
289
COM60
-3408
442.07
259
SEG101
-1872
442.07
290
COM59
-3456
442.07
260
SEG102
-1920
442.07
291
COM58
-3504
442.07
261
SEG103
-1968
442.07
292
COM57
-3552
442.07
262
SEG104
-2016
442.07
293
COM56
-3600
442.07
263
SEG105
-2064
442.07
294
COM55
-3648
442.07
264
SEG106
-2112
442.07
295
COM54
-3696
442.07
265
SEG107
-2208
442.07
296
COM53
-3744
442.07
266
SEG108
-2256
442.07
297
COM52
-3792
442.07
267
SEG109
-2304
442.07
298
COM51
-3840
442.07
268
SEG110
-2352
442.07
299
COM50
-3888
442.07
269
SEG111
-2400
442.07
300
COM49
-3936
442.07
270
SEG112
-2448
442.07
301
COM48
-3984
442.07
271
SEG113
-2496
442.07
272
SEG114
-2544
442.07
273
SEG115
-2592
442.07
274
SEG116
-2640
442.07
275
SEG117
-2688
442.07
276
SEG118
-2736
442.07
277
SEG119
-2784
442.07
278
SEG120
-2832
442.07
279
SEG121
-2880
442.07
RAiO TECHNOLOGY INC.
11/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
4. Pin Description
4-1 MPU Interface
Pin Name
I/O
Description
In Parallel Mode :
Data Bus
These are data bus for data transfer between MPU(6800/8080) and
RA8808.
In Serial Mode :
Pin
DB7
DB6
DB5
DB4
DB0~DB7
I/O
DB3
DB2
DB1
DB0
E
RW
RS
RAiO TECHNOLOGY INC.
Description
These pins are not used and must be connected to low.
In IIC Interface :
These pins are used as the IIC device address input.
(SA[2:0])
In SPI Interface :
These pins are not used and must be connected to
high or low.
In IIC Interface :
This pin is not used and must be connected to low.
In SPI Interface :
This pin is used as Chip selection, active low. (ZCS)
In IIC Interface :
This pin is used as Bi-direction serial Data.(SDA)
In SPI Interface :
This pin is used as Bi-direction serial Data.(SDA)
In IIC Interface :
This pin is used as serial clock.(SCL)
In SPI Interface :
This pin is used as serial clock.(SCK)
I
In Parallel Mode :
Enable or Read Control
When use 6800 series interface, this pin is used as Enable, active high.
When use 8080 series interface, this pin is used as data read, active low.
In Serial Mode :
This pin is not used and must be connected to low.
I
In Parallel Mode :
Read-Write Control or Write Control
When use 6800 series interface, this pin is used as data read/write
control. Active high for read and active low for write.
When use 8080 series interface, this pin is used as data write, active low.
In Serial Mode :
This pin is not used and must be connected to low.
I
In Parallel Mode :
Data or Instruction
RS = H Î DB0~DB7 : Display RAM data
RS = L Î DB0~DB7 : Instruction data
In Serial Mode :
This pin is not used and must be connected to low.
12/40
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RA8808
Preliminary Version 1.2
CS1
CS2B
CS3
CS4B
RSTB
128x64 Driver for Dot Matrix LCD
I
In Parallel Mode :
Chip selection for left side (Note *)
In order to interface left side data for input or output, the terminals have
to be
CS1 = H, CS2B = L.
In Serial Mode :
These pins are not used and must be connected to high or low.
I
In Parallel Mode :
Chip selection for right side (Note *)
In order to interface right side data for input or output, the terminals have
to be
CS3 = H, CS4B = L.
In Serial Mode :
These pins are not used and must be connected to high or low.
I
Reset Signal
When RSTB = L,
_ON/OFF register becomes set by 0. (display off)
_Display start line register becomes set by 0.(Z-address 0 set, display
from line 0)
After releasing reset, this condition can be changed only by instruction.
Parallel/Serial MPU Interface Selection
PS
H
L
I
PS
Parallel/Serial
Parallel
Serial
MPU Interface Selection(Combine with PS)
PS
H
H
L
L
I
MODE
MODE
H
L
H
L
MPU Interface
6800 series
8080 series
3-wire SPI
IIC
Note :
Because the two sides are independent for display the data, they must have their own chip
selections. Please refer to the figure below :
Left Side
Right Side
RAiO
64
瑞佑科技
Tech.
RA8808
RA8808
64
64
Figure 4-1
RAiO TECHNOLOGY INC.
13/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
4-2 LCD Panel Interface
Pin Name
I/O
Description
LCD Segment Driver Output
Display RAM data 1 : On, Display RAM data 0 : Off
Relation of display RAM & M :
SEG0~
SEG127
M
L
L
H
H
O
Data
L
H
L
H
Output Level
V2
V0
V3
GND
Common Signal Output for LCD Driving
Relation of common signal & M :
M
L
L
H
H
Common Signal
L
H
L
H
Output Level
V1
GND
V4
V0
COM0~
COM63
O
M
I/O
Alternating Signal Input for LCD Driving.
The input/output selection is determined by MS.
I/O
Display Synchronous Signal
Display data is latched at rising time of the CL signal and increments the
Z-address counter at CL falling time.
The input/output selection is determined by MS.
I/O
Synchronous Control Signal
Presets the 6-bit Z counter and synchronizes the common signal with the
frame signal when the frame signal becomes high.
The input/output selection is determined by MS.
CL
FRM
Master/Slave Mode Selection
MS
H
L
I
MS
Master/Slave Mode
Master
Slave
When in Master mode, M, CL, FRM are output pins.
When in Slave mode, M, CL, FRM are input pins. (Note *)
Note :
Because RA8808 support two RA8808 chips combination for display, it can support maximum
display range 256x64. The combination condition just refer to the figure below :
256
128
R
64
COM0~COM31
SEG0~SEG63
128
A
i
SEG64~SEG127
SEG0~SEG63
RA8808
CL FRM
FRM CL
COM32~COM63
SEG64~SEG127
RA8808
Master
M
O
Slave
M
Figure 4-2
RAiO TECHNOLOGY INC.
14/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
4-3 Clock
Pin Name
I/O
Description
In internal clock mode, this pin connects to external resistor for RC
circuit.
In external clock mode, this pin is an input of external clock.
Internal Clock Mode
I
RA
External Clock Mode
RA8808
RA8808
RA
RA
RB
R
50pF
External Clock
RB
Open
RB
O
In internal clock mode, this pin connects to external resistor for RC
circuit.
In external clock mode, this pin must keep floating.
CLK_OUT
O
Internal system clock output for cascade application or others for user.
4-4 Power
Pin Name
I/O
VOUT
O
Regulator Voltage Output
VDD
VDDP
P
Digital Power
GND
GNDP
P
Digital Ground
AVDD
P
Analog Power
AGND
P
Analog Ground
C1N
C1P
I
Capacitor Input
These are used to connect a capacitor for internal Booster.
C2N
C2P
I
Capacitor Input
These are used to connect a capacitor for internal Booster.
C3P
I
Capacitor Input
These are used to connect a capacitor for internal Booster.
V0A~V4A
I
Voltage Input
V0~V4
O
Voltage Source of LCD Driver
The relationship of the power is V0 > V1 > V2 > V3 > V4 > GND
RAiO TECHNOLOGY INC.
Description
15/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
4-5 MISC
Pin Name
I/O
Description
Selection of Segment Data Direction
ADC
I
ADC
H
L
Common Data Shift Direction
SEG0 Î SEG1 … ÎSEG127
SEG127 Î SEG126 … Î SEG0
Selection of Common Data Shift Direction
SHL
I
SHL
H
L
Common Data Shift Direction
COM0 Î COM1 … ÎCOM63
COM63 Î COM62 … Î COM0
Selection of Display Duty
DS
I
TEST0
TEST1
TEST2
I
RAiO TECHNOLOGY INC.
DS
H
L
Duty
1/64
1/48
These pins must contact to GND in normal mode.
16/40
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
5. Electrical Characteristics
5-1 Maximum Absolute Limit
Table 5-1
Characteristic
Symbol
Operation voltage
Value
VDD
Unit
-0.3 - +7.0
V
-0.3 - VDD+0.3
V
VLCD
8~17
V
Operation temperature
VOPR
-30 - +85
°C
Storage temperature
VSTG
-55 - +125
°C
VB
Driver supply voltage
Note
5-2 DC Characteristics
Table 5-2
(VDD = +5V / +3.3V ± 10%, VSS = 0V, Ta = -30 to +80°C)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Note
VIH1
–
0.7VDD
–
VDD
V
(1)
VIH2
–
0.55VDD
–
VDD
V
(2)
VIL1
–
0
–
0.3VDD
V
(1)
VIL2
–
0
–
0.2VDD
V
(2)
Output high voltage
VOH
IOH = 1.2mA
0.8VDD
–
–
V
Output low voltage
VOL
IOL = 1.6mA
–
–
0.2VDD
V
Input leakage current
ILKG
VIN = VSS ~ VDD
-1.0
–
1.0
uA
(3)
IDD1
Display with
display off
–
1.1
--
mA
(4)
IDD2
Static display
with data
–
1.3
--
mA
(4)
RON
VDD-VSS = 15V
ILOAD = ± 0.1mA
–
–
1.5
kΩ
(5)
Input high voltage
Input low voltage
Operating current
On resistance
Note :
1. RSTB.
2. CL, FRM, M, MODE, PS, ADC, SHL, DS, CS1, CS2B, CS3, CS4B, E, RW, RS, DB0 - DB7
3. Except M, CL, FRM
4. VDD= 5V, 128x64 COG module, FCLK = 448kHz, frame frequency = 72.6Hz, booster setting
with 4X, V0/V1/V2/V3/V4 = 8.80 / 7.74 / 6.77 / 1.94 / 0.97, display data = 0x55.
5. V0 > V1 = V0 - 1/9 (V0-VSS) > V2 = V0 - 2/9 (V0-VSS) > V3 = VSS + 2/9 (V0-VSS) > V4 = V0 + 1/9
(V0- VSS) > VSS
RAiO TECHNOLOGY INC.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
5-3 AC Characteristics
Table 5-3 : 6800 Interface
Description
Symbol
Min
Typ
Max
Unit
E cycle
tC
1000
–
–
ns
E high level width
tWH
450
–
–
ns
E low level width
tWL
450
–
–
ns
E rise time
tR
–
–
25
ns
E fall time
tF
–
–
25
ns
Address set-up time
tASU
140
–
–
ns
Address hold time
tAH
10
–
–
ns
Data set-up time
tDSU
200
–
–
ns
Data delay time
tD
–
–
320
ns
Data hold time (write)
tDHW
10
–
–
ns
Data hold time (read)
tDHR
20
–
–
ns
tC
E
tWL
2.0
0.8
tWH
tF
tR
RW
RS, CS1,
CS2B, CS3,
CS4B
tASU
tAH
tASU
tAH
2.0
0.8
tDSU
tDHW
DB0-7
Figure 5-1 : MPU 6800 Write Timing
tC
tWL
E
2.0
0.8
tWH
tF
tR
tASU
RW
RS, CS1,
CS2B, CS3,
CS4B
tAH
2.0
0.8
tD
tDHR
DB0-7
Figure 5-2 : MPU 6800 Read Timing
RAiO TECHNOLOGY INC.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Table 5-4 : 8080 Interface
Description
Rating
Symbol
Unit
Min.
Max.
Cycle time
tCYC8
1000
--
ns
Strobe Pulse width
tCC8
50
--
ns
Address setup time
tAS8
0
--
ns
Address hold time
tAH8
20
--
ns
Data setup time
tDS8
30
--
ns
Data hold time
tDH8
20
--
ns
Data output access time
tACC8
0
20
ns
Data output hold time
tOH8
0
10
ns
E
Condition
tc = one system clock period
tCYC8
tCC8
RW
tAH8
tAS8
RS,CS1,
CS2B,CS3,
CS4B
tDS8
tDH8
DB0-7
Figure 5-3 : MPU 8080 Write Timing
tCYC8
tCC8
E
RW
tAH8
tAS8
RS,CS1,
CS2B,CS3,
CS4B
tACC8
tOH8
DB0-7
Figure 5-4 : MPU 8080 Read Timing
RAiO TECHNOLOGY INC.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Table 5-5 : 3-Wire SPI Interface
Item
Signal
Access Time
ZCS Setup Time
Clock Low Pulse Width
Clock High Pulse Width
Data Setup Time
Data Hold Time
ZCS
SCK
SDA
Symbol
Rating
Min.
Max.
3.6
20
100
100
20
10
Condition
tCYC3
tCSH3
tCKL3
tCKH3
tDS3
tDH3
Unit
ms
ns
tCYC3
ZCS
tCSH3
SDA
AB
tDS3
RS
R/W
DB7~0
tDH3
SCK
tCKL3
tCKH3
Figure 5-5 : 3-Wire SPI Timing
Table 5-6 : IIC Interface
Item
Signal
Symbol
SCL Clock Frequency
Bus Free Time Between STOP
and START
Low Period of SCL Clock
High Period of SCL Clock
Data Setup Time
Data Hold Time
SCL
tHIGH
tBUF
Rating
Unit
fSCL
Min.
100
Max.
400
SCL/SDA
tBUF
1
-
μs
SCL
SCL
SCL/SDA
SCL/SDA
tLOW
tHIGH
tDSIIC
tDHIIC
200
200
100
100
-
ns
ns
ns
ns
KHz
tDHIIC
SDA
SCL
tDSIIC
tLOW
Start
Stop
Figure 5-6 : IIC Timing
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6. Operating Principles and Methods
6-1 MPU Interface
6-1-1 6800 Interface
6800
MPU
RA8808
A0
VDD
RS
VDD
CS1
CS3
A1-A7
VMA
PS
CS2B
Decoder
CS4B
D0-D7
MODE
DB0~DB7
EN
E
R/W
RW
RES
RSTB
50pF
Figure 6-1 : 6800 (8-bit) MPU Interface
The RA8808 supports 6800 MPU interface. The Register/Status Read/Write and Memory
read/Write waveform just like the below figure :
DB[7:0]
Data
DB[7:0]
RS
RS
E
E
RW
RW
CS1/CS3
CS1/CS3
CS2B/CS4B
CS2B/CS4B
Memory Write
DB[7:0]
Data
Memory Read
Data
DB[7:0]
RS
RS
E
E
RW
RW
CS1/CS3
CS1/CS3
CS2B/CS4B
CS2B/CS4B
Data
Status Read
Register Write
Figure 6-2 : 6800 Interface
RAiO TECHNOLOGY INC.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-1-2 8080 Interface
8080
MPU
RA8808
A0
RS
VDD
VDD
CS1
A1-A7
IORQ
Decoder
D0-D7
CS3
CS2B
PS
CS4B
MODE
DB0~DB7
RD
E
WR
RW
RES
RSTB
50pF
Figure 6-3 : 8080 (8-bit) MPU Interface
The RA8808 also support 8080 MPU interface. The Register/Status Read/Write and Memory
read/Write waveform just like the below figure:
DB[7:0]
Data
DB[7:0]
RS
RS
E
E
RW
RW
CS1/CS3
CS1/CS3
CS2B/CS4B
CS2B/CS4B
Memory Write
DB[7:0]
Data
Memory Read
Data
DB[7:0]
RS
RS
E
E
RW
RW
CS1/CS3
Data
CS1/CS3
CS2B/CS4B
CS2B/CS4B
Register Write
Status Read
Figure 6-4 : 8080 Interface
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-1-3 3-Wire SPI Interface
MPU
RA8808
VDD
MODE
PS
VDD VDD VDD
1KΩ~10KΩ
IO0
SCK (DB0)
IO1
SDA (DB1)
IO2
ZCS (DB2)
50pF
Figure 6-5 : The MPU Interface Diagram of 3-Wire SPI
The SPI is available through the chip select line (ZCS), serial transfer clock line (SCK), serial
input/output line (SDA). The SPI can be configured in command/memory write mode or
status/memory read mode by setting most three bits of first byte. Before a data transmission begins,
ZCS which is low active must be set to low until the transmission is finished. When the SPI module
is in command/memory write mode (Figure 6-6), a byte is received from the controller to RA8808
via SDA under the control of the SCK from the controller. When the SPI module is in status/memory
read mode (Figure 6-7), a byte is sent from RA8808 to the controller via SDA under the control of
the SCK from the controller.
Transfer End
Transfer Start
ZCS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
8
7
1
2
3
4
5
6
7
8
SCK
MSB
SDA
AB RS RW
LSB
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
MSB
LSB
DB DB DB DB DB DB DB DB
7 6
5
4
3
2
1
0
COMMAND/
COMMAND/
MEMORY WRITEDATA
MEMORY WRITE DATA
FROM CONTROLLER TO RA8808
AB 0:DEVICE A,
1:DEVICE B
RS 0:COMMAND/STATUS, 1:MEMORY
FROM RA8808 TO CONTROLLER
RW 0:WRITE,
1:READ
Figure 6-6 : Command/Memory Write on SPI-Bus
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Transfer End
Transfer Start
ZCS
1
2
3
4
5
6
7
8
1
2
3
4
6
5
8
1
LSB
MSB
7
2
3
4
5
6
7
8
SCK
MSB
SDA
DB DB DB DB DB DB DB DB
6
5
4
3
2
1
0
7
AB RS RW
LSB
DB DB DB DB DB DB DB DB
7
6
5
4
3
2
1
0
STATUS/
STATUS/
MEMORY READ DATA
MEMORY READ DATA
FROM CONTROLLER TO RA8808
AB 0:DEVICE A,
1:DEVICE B
RS 0:COMMAND/STATUS, 1:MEMORY
FROM PM8808 TO CONTROLLER
RW 0:WRITE,
1:READ
Figure 6-7 : Status/Memory Read on SPI-Bus
6-1-4 IIC Interface
MPU
RA8808
MODE
PS
DB7
DB6
VDD
SA2 (DB5)
SA1 (DB4)
SA0 (DB3)
VDD VDD
1KΩ~10KΩ
DB2
IO0
SCL (DB0)
IO1
SDA (DB1)
50pF
Figure 6-8 : The MPU Interface Diagram of IIC
The IIC is available through the serial transfer clock line (SCL) and the serial input/output(SDA).
The IIC can be configured in command/memory write mode or status/memory read mode by setting
first byte that including device ID (Table 6-1), read bit and write bit. When the IIC module is in
command/memory write mode (Figure 6-9), a byte that from the controller to PM8808 is received
via SDA under the control of the SCL from the controller and RA8808 sends a acknowledge signal
at ninth SCL clock. When the SPI module is in status/memory read mode (Figure 6-10), a byte that
from RA8808 to the controller is sent via SDA under the control of the SCL from the controller and
the controller sends a acknowledge signal to PM8808 after receiving a byte data.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Table 6-1 : IIC DEVICE ID
Device ID
BIT5
BIT4
BIT3
00b
BIT2
BIT1
BIT0
0 : DEVICE A
SA[2:0] SLAVE ADDRESS
1 : DEVICE B
For Example : If you set slave address 000b, the Device A ID will be 10_0000b and the
Device B ID will be 10_0001b.
START
STOP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
6
5
7
8
9
SCL
MSB
SDA
RS RW
DEVICE ID
A
LSB
DB DB DB DB DB DB DB DB
7
0
6
5
4
3
2
1
S
MSB
LSB
DB DB DB DB DB DB DB DB
7
6
5
4
3
2
1
0
A
A
P
COMMAND/
COMMAND/
MEMORY WRITE DATA
MEMORY WRITE DATA
RS 0:COMMAND/STATUS, 1:MEMORY
FROM CONTROLLER TO RA8808
RW 0:WRITE,
FROM RA8808 TO CONTROLLER
1:READ
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
Figure 6-9 : Command/Memory Write on IIC-Bus
START
STOP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
6
5
7
8
9
SCL
MSB
SDA
DEVICE ID
RS RW
A
LSB
DB DB DB DB DB DB DB DB
7
0
6
5
4
3
2
1
S
FROM CONTROLLER TO RA8808
LSB
DB DB DB DB DB DB DB DB
7
6
5
4
3
2
1
0
A
STATUS/
STATUS/
MEMORY READ DATA
MEMORY READ DATA
A
P
RS 0:COMMAND/STATUS, 1:MEMORY
RW 0:WRITE,
FROM RA8808 TO CONTROLLER
MSB
1:READ
A/A: ACKNOWLEDGE/NOT ACKNOWLEDGE
Figure 6-10 : Status/Memory Read on IIC-Bus
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-2 RC Oscillator
The RC Oscillator generates system clock of the RA8808 by the oscillation resister R and capacitor C.
The capacitor C is embedded. Resistor R must be connected between RA and RB pins when use
internal clock mode. The FRM, CL, M are generated by the frequency(system clock) from the
oscillation circuit. If VDD = 5V, for generating 440KHz system clock(FRM frequency ~70Hz), RA and
RB pins must be connected to a 51KΩ resistor. The oscillation circuit is as following:
RA8808
RA8808
RA
RA
RB
50pF
R
External Clock
RB
Open
Figure 6-12 : External Clock Mode
Figure 6-11 : Internal Clock Mode
6-3 LCD Driver and Power Supply Circuit
The LCD Driver power system operation method is descripted the bellow Figure 6-13. The power
supply system is a low power consumption circuit for dot matrix LCD.
D[n:0]
Data
Latch
LP
V0
V1
CK_BS
Booster
COM /
Segment
Driver
V2
Voltage
Follower
V3
V4
VOUT V0A V1A V2A V3A V4A
CxP
CxN
SEG[127:0]
DOFF
C1
R-String
C1
COM[63:0]
C1
C1
C1
C1
GND
C1=1μF
Figure 6-13 : LCD Driver and Power Supply Circuit Block
6-3-1 Booster Circuit
The power supply circuit is consist of Boosters, internal voltage follower. The booster can produce
2X, 3X, 4X step-up of “VDD - GND” voltage levels. When VOUT is equal to 2 × VDD, the capacitor
1uF is connected to C1P and C1N pin. When VOUT is equal to 3 × VDD, the capacitor 1uF is
additional connected to C2P and C2N pin. When VOUT is equal to 4 × VDD, the capacitor 1uF is
additional connected to C3P and C1N pin. The application circuit for booster can refer the
description of Figure 6-14. Note to the maximum rating voltage in the booster application circuit
carefully.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
C1=1μF
VDD
VDD
C2P
C1
C1P
C1
C1N
C2P
C1
C2N
C3P
RA8808
C1N
RA8808
RA8808
C1P
C1
VDD
C1P
C1
C1N
C2P
C2N
C2N
C3P
C3P
C1
VOUT
C1
VOUT
C1
GND
4X Step-up Voltage Circuit
VOUT
C1
GND
GND
3X Step-up Voltage Circuit
2X Step-up Voltage Circuit
VOUT=4xVDD=12V
VOUT=3xVDD=9V
VOUT=2xVDD=6V
VDD=3V
VDD=3V
VDD=3V
GND=0V
GND=0V
GND=0V
4X Step-up Voltage Relationships
3X Step-up Voltage Relationships
2X Step-up Voltage Relationships
Figure 6-14 : Application Circuit of Booster
Normally, if use the internal Driver Power, then the application circuit is follow Figure 6-13. If use
external VOUT, that means do not use the internal Booster, then the connection is show as Figure
6-15.
VDD
VOUT
External
Power Supply
VOUT
C3P
C2N
C3P
C2N
C2P
C1N
C1P
V0A
V1A
V2A
V3A
V4A
C2P
C1N
C1P
V0A
R-String
V1A
V2A
V3A
V4A
C1
V0
V0
C1
External
Power
Supply
V1
C1
V2
C1
V3
C1
V4
VSS
V1
V2
V3
V4
VSS
Figure 6-15 : External VOUT
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Figure 6-16 : Use External Voltage Follower
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-3-2 Voltage Follower
The internal Voltage Follower provides V0~V4 power for LCD Driver circuit. Of course, the user
could select internal or external Voltage Follower. The relationship of V0~V4 and VOUT is as
following:
VOUT > V0 > V1 > V2 > V3 > V4 > GND
Figure 6-13 shows the circuit of using internal Voltage Follower. For external V0~V4, the connection
is show as Figure 6-16.The internal voltage follower is included to V0,V1,V2,V3,V4 for differential
input voltages V0A,V1A,V2A,V3A,V4A.
6-3-3 LCD Driver
The Segment/Common Driver of RA8808 is used to latch the data of pre-stage, then send to Level
Shifter for combination. The combined data will follow the Timing Generator to control the switchs
then pass the V0~V4 to Common and Segment.
The LCD Bias of RA8808 is adjustable by external R-string so that user can adjust the display
quality.Please refer to Figure 8-2 and Figure 8-3.
6-3-4 Temperature Compensation
The temperature compensation of RA8808 is achieved by external circuit. Please refer to the Figure
6-17, R1 and R3 + R2//RT of voltage divider decided to transistor VB; R2//RT for the temperature
compensation, characteristics such as Figure 6-18.
※The following information is for reference only. When using different LCD specifications or
different characteristics of the parts (ex: Q, R, RT, ...), you may need to adjust R1, R2, R3, RT
resistance according to the actual application.
Figure 6-17 : The Reference Circuit of Temperature Compensation
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
R
R2
RT
R2//RT
T
Figure 6-18 : The Characteristic of Temperature Compensation
6-4 I/O Buffer
6-4-1 In Parallel Mode
Input buffer controls the status between the enable and disable of chip. Unless the CS1 and
CS2B(Left side chip) or the CS3 and CS4B(Right side chip) are in active mode, input or output of
data and instruction does not execute. Therefore internal state is not change. But RSTB, ADC can
operate regardless CS1 and CS2B or CS3 and CS4B.
6-4-2 In Serial Mode
Input buffer also controls the status between the enable and disable of chip. Unless the serial data
is decoded and the status is DEVICE A(Left side chip) or DEVICE B(Right side chip), input or
output of data and instruction does not execute. Therefore internal state is not change. Just the
same, RSTB, ADC can operate regardless the status DEVICE A or DEVICE B.
6-5 Input Register
6-5-1 In Parallel Mode
Input register is provided to interface with MPU which is different operating frequency. Input register
stores the data temporarily before writing it into display RAM. When CS1 and CS2B or CS3 and
CS4B are in the active mode, RW and RS select the input register, the data from MPU is written
into input register. And then, write it into display RAM. Data latched for falling of the E signal when
in 6800 series MPU IF or rising of the RW signal when in 8080 series MPU IF and write
automatically into the display data RAM by internal operation.
6-5-2 In Serial Mode
Input register is provided to interface with MPU which is different operating frequency. Input register
stores the data temporarily before writing it into display RAM. When serial data is decoded and the
status is DEVICE A or DEVICE B and RW and RS select the input register, the data from MPU is
written into input register. And then, write it into display RAM automatically by internal operation.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-6 Output Register
6-6-1 In Parallel Mode
Output register stores the data temporarily from display data RAM when CS1 and CS2B or CS3
and CS4B are in active mode and RW=H and RS=H when in 6800 series MPU IF or E=L and
RS=H when in 8080 series MPU IF, stored data in display data RAM is latched in output register.
When CS1 and CS2B or CS3 and CS4B are in active mode and RW=H and RS=L when in 6800
series MPU IF or E=L and RS=L when in 8080 series MPU IF, status data (busy check) can read
out. To read the contents of display data RAM, twice access of read instruction is needed. In first
access, data in display data RAM is latched into output register. In second access, MPU can read
data which is latched. That is, to read the data in display data RAM, it needs dummy read. But
status read is not needed dummy read.
Table 6-2
MPU
6800
8080
RW = L
RW = H
RW = L
E=L
RW = L
RW = L
RW = H
E=L
RS
L
Function
Instruction write
Status read (busy check)
Data write (from input register to display data
RAM)
Data read (from display data RAM to output
register)
H
6-6-2 In Serial Mode
Output register stores the data temporarily from display data RAM when the status is DEVICE A or
DEVICE B and RW=H and RS=H, stored data in display data RAM is latched in output register.
When the status is DEVICE A or DEVICE B RW=H and RS=L, status data (busy check) can read
out. To read the contents of display data RAM, twice access of read instruction is needed. In first
access, data in display data RAM is latched into output register. In second access, MPU can read
data which is latched. That is, to read the data in display data RAM, it needs dummy read. But
status read is not needed dummy read.
SCK /
SCL
Address
N
Output
Register
SDA
N+1
N+2
Data at address N
Read data
(dummy)
Data at address N + 1
Read
data at
address N
N+3
Data at address N + 2
Read
data at
address N + 1
Figure 6-19 : Serial Mode Read Cycle
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-7 Reset
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving
instruction from MPU.
When RSTB becomes low, following procedure is occurred.
_ Display off
_ Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read
instruction. The Conditions of power supply at initial power up are shown in Table 6-3.
Table 6-3 : Power Supply Initial Conditions
Item
Symbol
Min
Typ
Max
Unit
Reset
T ime
tRS
1.0
-
-
µs
Rise
T ime
tR
4.5V
VDD
tRS
tR
0.7V DD
RSTB
-
-
200
0.3VDD
ns
6-8 Busy Flag
Busy Flag indicates that RA8808 is operating or no operating. When busy flag is high, RA8808 is in
internal operating. When busy flag is low, RA8808 can accept the data or instruction. DB7 indicates
busy flag of the RA8808.
RS
RW
E
N
Address
N+1
Output
Register
N+2
Data at address N Data at address N + 1
Busy
Check
DB0-DB7
Write
Busy
address N check
Read data Busy
(dummy) check
Read
Busy
data at
check
address N
Data read
address
N+1
Figure 6-20 : MPU Read Cycle
E
Busy
Flag
T Busy
1/fCLK≦ T BUSY≦ 3/f CLK
fCLK is CLK_OUT frequency
Figure 6-21 : Busy Flag
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
6-9 Display ON/OFF Flip – Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low),
selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set
(logic high), non selective voltage appears on segment output terminals regardless of display RAM
data. The display on/off flip-flop cans changes status by instruction. The display data at all segments
disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction.
The display on/off flip-flop synchronized by CL signal.
6-10 X Page Register
X page register designates pages of the internal display data RAM. Count function is not available. An
address is set by instruction.
6-11 Y Address Counter
Y address counter designates address of the internal display data RAM. An address is set by
instruction and is increased by 1 automatically by read or write operations of display data.
6-12 Display Data RAM
Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of
liquid crystal display, write data 1. The other way, off state, writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
_ ADC = H Æ S0 ~ S127
_ ADC = L Æ S127 ~ S0
ADC terminal connect the VDD or GND.
6-13 Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display.
Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register.
Latched data is transferred to the Z address counter while FRM is high, presetting the Z address
counter. It is used for scrolling of the liquid crystal display screen.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
7. Display Control Instruction
The display control instructions control the internal state of the RA8808. Instruction is received from
MPU to RA8808 for the display control. The following table shows various instructions.
Table 7-1
Instruction
DB7
DB6
Display on/off
L
L
Set Address
(Y address)
L
H
Set page
(X address)
H
L
Display start
line (Z address)
H
H
Status Read
DB7
DB6
Status read
Data Write
Write display
data
Data Read
Read display
data
DB5
H
DB4
DB3
H
H
DB2
DB1
H
H
DB0
L/H
Y address (0 ~ 63)
H
H
H
Sets the X address at the
X address register.
Page (0 ~ 7)
Indicates the display data
RAM displayed at the top
of the screen.
Display start line (0 ~ 63)
DB5
DB4
DB3
DB2
DB1
Function
Controls the display on
or off.
Internal status and
display RAM data is not
affected. L: OFF, H: ON
Sets the Y address in the
Y address counter.
DB0
Function
Busy
L
On/
Off
Reset
L
L
L
L
Read status.
BUSY L: Ready
H: In operation
ON/OFF L: Display ON
H: Display OFF
RESET L: Normal
H: Reset
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Function
Writes data(DB7~0)into
display data RAM. After
writing instruction, Y
address is increased by
1 automatically.
Write data
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Function
Reads data(DB7~0) from
display data RAM to the
data bus.
After reading instruction,
Y address is increased
by 1 automatically.
Read data
7-1 Display ON/OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
1
1
D
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the
screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing
D = 0 into D = 1.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
7-2 Set Address (Y Address)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Y address (AC0 ~ AC5) of the display data RAM is set in the Y address counter. An address is set by
instruction and increased by 1 automatically by read or write operations of display data.
7-3 Set Page (X Address)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
1
1
AC2
AC1
AC0
X address(AC0 ~ AC2) of the display data RAM is set in the X address register. Writing or reading to
or from MPU is executed in this specified page until the next page is set.
7-4 Display Start Line (Z Address)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
AC5
AC4
AC3
AC2
AC1
AC0
Z address (AC0 ~ AC5) of the display data RAM is set in the display start line register and displayed
at the top of the screen. When the display duty cycle is 1/64 or others(1/48 ~ 1/64), the data of total
line number of LCD screen, from the line specified by display start line instruction, is displayed.
7-5 Status Read
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BUSY
0
ON/OFF
RESET
0
0
0
0
‹ BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
‹ ON/OFF
When ON/OFF is 1, the display is off.
When ON/OFF is 0, the display is on.
‹ RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
7-6 Write Display Data
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data (D0 ~ D7) into the display data RAM. After writing instruction, Y address is increased by 1
automatically.
7-7 Read Display Data
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D7
D6
D5
D4
D3
D2
D1
D0
Reads data (D0 ~ D7) from the display data RAM. After reading instruction, Y address is increased by
1 automatically.
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
8. Application Circuit
8-1 Timing Diagram (1/64 DUTY)
64
2
1
3
64
1
2
3
64
1
CL
Input
FRM
1 Frame
1 Frame
M
V0
COM0
V1
V4
GND
V1
Common
COM1
V4
GND
V0
V1
V4
V4
GND
V0
COM63
V1
V4
V4
V0
V1
V1
V4
GND
V0
SEG0
V2
V2
V3
V3
GND
V0
Segment
V2
V2
SEG127
V3
V3
GND
Figure 8-1 : Timing Diagram
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
8-2 LCD Panel Interface Application Circuit
8-2-1 128X64
COM0
COM31
LCD Panel
(128x64 dots)
COM32
COM63
SEG0
SEG127
RW
E
RS
RSTB
CS3
CS1
CS2B
PS
CS4B
MS
MODE
DS
ADC
SHL
V0
V4
AGND
GND
AVDD
V4A
VDD
C3P
V0A
C1P
VOUT
TEST0
TEST1
RA
RB
TEST2
RA8808
C1P~C3P
V0A~V4A
MODE
V0~V4
VDD GND
VOUT
CS3
CS1
RW
E
RS
RSTB
50pF
DB[7:0]
51kΩ
PS
VDD
VDD
VDD
1μF
1μF
V0
C1P
C1N
1μF
C2P
V3
V4
*
10KΩ
CS1
C3P
1μF
V2
1μF
X
5
V0A V1A V2A V3A
VOUT
1μF
V1
0.1μF
X
5
*
*
C2N
*
*10KΩ
6800 MPU
CS3
V4A
*
VDD
*
RW
50~
300 pF
* : Reserved / Option
E
50~
300 pF
* 0Ω
* 0Ω
VDD
PS
* 0Ω MODE
* 0Ω
Figure 8-2 : 128X64 Application Circuit
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
8-2-2 256X64
COM0
COM31
LCD Panel
(256x64 dots)
COM32
COM63
SEG127
VOUT2
VDD
CS2B
CS4B
DB[7:0]
CS3
CS1
V0
VDD
VOUT2
1μ
F
V0-2
V1-2 V2-2 V3-2 V4-2
1μF
X
5
CS2B
*
CS4B
*
RS
RSTB
*
*
CS1
V4A
*
CS3
V0A V1A V2A V3A
0.1μF
X
5
E
For RA8808 - # 2
VDD
1μF
MS
V0-2~V4-2
V0A~V4A
RW
For RA8808 - # 1
V4
V4A
C3P
V0A
C1P-2~C3P-2
V0-1~V4-1
V0A~V4A
C1P
VOUT
RA
CLK_OUT
RS
RSTB
DB[7:0]
RW
E
CS1
CS3
CS2B
CS4B
V0
MS
V4
V4A
C3P
V0A
C1P
C1P-1~C3P-1
VOUT1
RA8808 - #2
DB[7:0]
50pF
VOUT
RB
RA
51KΩ
FRM
RW
E
RS
RSTB
M
CL
M
CL
FRM
RA8808 - #1
SEG127
SEG0
RB
SEG0
VOUT1
1μF
C1P-1
V0-1 V1-1 V2-1 V3-1 V4-1
1μF
X
5
C1P-2
1μF
1μF
C1N-1
C2N-1
6800 MPU
E
50~
300 pF
1μF
C3P-2
C3P-1
1μF
RW
50~
300 pF
C1N-2
VDD
1μF
C2P-1
Reserved
*
*
10KΩ
10KΩ
C2P-2
CS2B
150pF
*
CS4B
*
150pF
1μF
CS1
CS3
C2N-2
* : Reserved / Option
Figure 8-3 : 256X64 Application Circuit
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Appendix A. COG/Module Application
128x64
STN Panel
RA8808
FPC
FPC Connector
R-String
Booster-Caps
PCB
MCU I/F
Figure A-1 : 128X64 Module
192x64 or 256x64
STN Panel
RA8808
FPC
FPC Connector
Booster-Caps
R-String
PCB
MCU I/F
Figure A-2 : 192x64 / 256x64 Module
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RA8808
Preliminary Version 1.2
128x64 Driver for Dot Matrix LCD
Appendix B. ITO
Tbale B-1 : Maximum ITO Resistance of COG
PAD Name
ITO(Ohm)
PAD Name
ITO(Ohm)
PAD Name
ITO(Ohm)
100
DS
200
RA
500
100
DB[7..0]
500
RB
500
VOUT
120
E
500
CLK_OUT
500
C1N, C1P
100
RW
500
MS
500
C2N, C2P
100
RS
500
M
500
C3P
120
CS1, CS2B
500
CL
500
V0~V4
120
CS3, CS4B
500
FRM
500
V0A~V4A
120
RSTB
500
TEST[2..0]
500
ADC
200
MODE
500
SHL
200
PS
500
VDD , VDDP,
AVDD
GND , GNDP.
AGND
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