NHD‐3.12‐25664UCB2 Graphic OLED Display Module NHD‐ 3.12‐ 25664‐ UC‐ B‐ 2‐ Newhaven Display 3.12” diagonal size 256 x 64 pixel resolution Model Emitting Color: Blue +2.95V power supply Newhaven Display International, Inc. 2511 Technology Drive, Suite 101 Elgin IL, 60124 Ph: 847‐844‐8795 Fax: 847‐844‐8796 www.newhavendisplay.com [email protected] [email protected] Document Revision History Revision 0 1 Date 5/1/2011 2/22/2013 Description Initial Product Release Electrical characteristics and mechanical drawing updated Functions and Features • • • • • 256 x 64 pixel resolution Built‐in SSD1322 controller Parallel or serial MPU interface Single, low voltage power supply RoHS compliant [2] Changed by ‐ JN L A I Mechanical Drawing 1 2 3 4 A Rev D 1 Date T N F N O C 6 Description E D I B C 5 B C D Date 02/22/13 Unit Gen. Tolerance ±0.3mm 2 A 3 4 mm 5 Model: NHD-3.12-25664UCB2 6 The drawing contained herein is the exclusive property of Newhaven Display International, Inc. and shall not be copied, reproduced, and/or disclosed in any format without permission. [3] Interface Description Parallel Interface: Pin No. Symbol External Connection Power Supply Power Supply ‐ MPU MPU 1 2 3 4 5 VSS VDD NC D/C R/W or /WR 6 E or /RD MPU 7‐14 15 16 17 18 19 20 DB0 – DB7 NC /RES /CS NC BS1 BS0 MPU ‐ MPU MPU ‐ MPU MPU Function Description Ground Supply Voltage for OLED and logic. No Connect Register select signal. D/C=0: Command, D/C=1: Data 6800‐interface: Read/Write select signal, R/W=1: Read R/W: =0: Write 8080‐interface: Active LOW Write signal. 6800‐interface: Operation enable signal. Falling edge triggered. 8080‐interface: Active LOW Read signal. 8‐bit Bi‐directional data bus lines. No Connect Active LOW Reset signal. Active LOW Chip Select signal. No Connect MPU Interface Select signal. MPU Interface Select signal. Serial Interface: Pin No. Symbol 1 2 3 4 VSS VDD NC D/C External Connection Power Supply Power Supply ‐ MPU 5‐6 7 8 9 10‐14 15 16 17 18 19 20 VSS SCLK SDIN NC VSS NC /RES /CS NC BS1 BS0 Power Supply MPU MPU ‐ Power Supply ‐ MPU MPU ‐ MPU MPU Function Description Ground Supply Voltage for OLED and logic. No Connect Register select signal. D/C=0: Command, D/C=1: Data Tie LOW for 3‐wire Serial Interface. Ground Serial Clock signal. Serial Data Input signal. No Connect Ground No Connect Active LOW Reset signal. Active LOW Chip Select signal. No Connect MPU Interface Select signal. MPU Interface Select signal. MPU Interface Pin Selections Pin Name BS1 BS0 6800 Parallel 8‐bit interface 8080 Parallel 8‐bit interface 1 1 1 0 3‐wire Serial Interface 0 1 4‐wire Serial Interface 0 0 [4] U Interface Pin n Assignmentt Summery MPU Bu us Interrface 8‐bit 6800 8‐bit 8080 3‐wire SPI 4‐wire SPI Data/C Command Inte erface D7 D6 D D5 D4 D3 D2 D1 D[7:0] D[7:0] Tie LOW NC SDIN Tie LOW NC SDIN D0 SCLK SCLK Control Signals E R/W /CS D/C E R/W /CS D/C /RD /WR /CS D/C Tie LLOW /CS Tie LOW Tie LLOW /CS D/C //RES / /RES / /RES / /RES / /RES Wirring Diagrams [5] Electrical Characteristics Item Operating Temperature Range Storage Temperature Range Symbol Top Tst Supply Voltage Supply Current (logic) VDD IDD Supply Current (display) ICC Sleep Mode Current “H” Level input “L” Level input “H” Level output “L” Level output Condition Absolute Max Absolute Max Ta=25°C, VDD=3.0V 50% ON, VDD=3.0V 100% ON, VDD=3.0V IDD+ICCSLEEP Vih Vil Voh Vol Min. ‐40 ‐40 Typ. ‐ ‐ Max. +85 +90 Unit ⁰C ⁰C ‐ ‐ ‐ ‐ ‐ 0.8*VDD VSS 0.9*VDD VSS 3.0 6 155 250 ‐ ‐ ‐ ‐ ‐ 3.3 5 165 265 110 VDD 0.2*VDD VDD 0.1*VDD V mA mA mA µA V V V V Optical Characteristics Item Viewing Angle – Top Viewing Angle – Bottom Viewing Angle – Left Viewing Angle – Right Contrast Ratio Response Time (rise) Response Time (fall) Brightness Lifetime Symbol AV AV AH AH Cr Tr Tf Condition Min. ‐ ‐ ‐ ‐ 2000:1 ‐ ‐ 60 10,000 Typ. 80 80 80 80 ‐ 10 10 80 ‐ Max. ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ Unit ⁰ ⁰ ⁰ ⁰ ‐ us us cd/m2 Hrs ‐ ‐ 50% checkerboard Ta=25°C, 50% checkerboard Note: Lifetime at typical temperature is based on accelerated high‐temperature operation. Lifetime is tested at average 50% pixels on and is rated as Hours until Half‐Brightness. The Display OFF command can be used to extend the lifetime of the display. Luminance of active pixels will degrade faster than inactive pixels. Residual (burn‐in) images may occur. To avoid this, every pixel should be illuminated uniformly. [6] Built‐in SSD1322 controller Instruction Table Instruction Enable Grayscale Table Set Column Address Write RAM Command Read RAM Command Set Row Address Set Remap Set Display Start Line Set Display Offset Display Mode Enable Partial Display D/C 0 HEX 00 DB7 0 DB6 0 Code DB5 DB4 0 0 DB3 0 DB2 0 DB1 0 DB0 0 0 1 1 0 15 A[6:0] B[6:0] 5C 0 * * 0 0 A6 B6 1 0 A5 B5 0 1 A4 B4 1 0 A3 B3 1 1 A2 B2 1 0 A1 B1 0 1 A0 B0 0 0 5D 0 1 0 1 1 1 0 1 0 1 1 0 1 1 75 A[6:0] B[6:0] A0 A[5:0] B[4] 0 * * 1 0 * 1 A6 B6 0 0 * 1 A5 B5 1 A5 0 1 A4 B4 0 A4 B4 0 A3 B3 0 0 0 1 A2 B2 0 A2 0 0 A1 B1 0 A1 0 1 A0 B0 0 A0 1 0 1 0 1 0 A1 A[6:0] A2 A[6:0] A4/A7 1 * 1 * 1 0 A6 0 A6 0 1 A5 1 A5 1 0 A4 0 A4 0 0 A3 0 A3 0 0 A2 0 A2 X2 0 A1 1 A1 X1 1 A0 0 A0 X0 0 1 1 A8 A[6:0] B[6:0] 1 0 0 0 A6 B6 1 A5 B5 0 A4 B4 1 A3 B3 0 A2 B2 0 A1 B1 0 A0 B0 [7] Description Enable the Grayscale table settings. (see command 0xB8) Set column start and end address A[6:0]: Column start address. Range: 0‐119d B[6:0]: Column end address. Range: 0‐119d RESET value 0 119d Enable MCU to write Data into RAM Enable MCU to read Data from RAM Set row start and end address A[6:0]: Row start address. Range: 0‐127d B[6:0]: Row end address. Range: 0‐127d 0 127d 0 0 0 0 0 0 A[0] = 0; Horizontal Address Increment A[0] = 1; Vertical Address Increment A[1] = 0; Disable Column Address remap A[1] = 1; Enable Column Address remap A[2] = 0; Disable Nibble remap A[2] = 1; Enable Nibble remap A[4] = 0; Scan from COM0 to COM[N‐1] A[4] = 1; Scan from COM[N‐1] to COM0 A[5] = 0; Disable COM split Odd/Even A[5] = 1; Enable COM split Odd/Even B[4] = 0; Disable Dual COM mode B[4] = 1; Enable Dual COM mode Note: A[5] must be 0 if B[4] is 1. Set display RAM display start line register from 0‐127. 0 Set vertical shift by COM from 0~127. 0 0xA4 = Entire display OFF 0xA5 = Entire display ON, all pixels Grayscale level 15 0xA6 = Normal display 0xA7 = Inverse display Turns ON partial mode. A[6:0] = Address of start row B[6:0] = Address of end row (B[6:0] > A[6:0]) 0xA6 0 0 1 0 A9 AB A[0] AE~AF 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1 A0 X0 Exit Partial Display mode A[0] = 0; External VDD A[0] = 1; Internal VDD regulator 1 0xAE = Sleep Mode ON (display OFF) 0xAF = Sleep Mode OFF (display ON) 0 1 0 1 B1 A[7:0] B3 A[7:0] 1 A7 1 A7 0 A6 0 A6 1 A5 1 A5 1 A4 1 A4 0 A3 0 A3 0 A2 0 A2 0 A1 1 A1 1 A0 1 A0 A[3:0] = P1. Phase 1 period of 5‐31 DCLK clocks A[7:4] = P2. Phase 2 period of 3‐15 DCLK clocks 9 7 Set GPIO 0 1 B5 A[3:0] 1 * 0 * 1 * 1 * 0 A3 1 A2 0 A1 1 A0 Set Second Precharge Period Set Grayscale Table 0 1 0 1 1 1 1 1 1 1 B6 A[3:0] B8 A1[7:0] A2[7:0] . . . A14[7:0] A15[7:0] 1 * 1 A15 A25 . . . A145 A155 1 * 1 A14 A24 . . . A144 A154 0 A3 1 A13 A23 . . . A143 A153 1 A2 0 A12 A22 . . . A142 A152 1 A1 0 A11 A21 . . . A141 A151 0 A0 0 A10 A20 . . . A140 A150 0 B9 1 1 1 0 0 1 Exit Partial Display Function Selection Set Sleep Mode ON/OFF Set Phase Length Set Display Clock Divide Ratio / Oscillator Frequency Select Default 1 0 * * 0 1 A17 A16 A27 A26 . . . . . . A147 A146 A157 A156 1 0 [8] A[3:0] = 0000; divide by 1 A[3:0] = 0001; divide by 2 A[3:0] = 0010; divide by 4 A[3:0] = 0011; divide by 8 A[3:0] = 0100; divide by 16 A[3:0] = 0101; divide by 32 A[3:0] = 0110; divide by 64 A[3:0] = 0111; divide by 128 A[3:0] = 1000; divide by 256 A[3:0] = 1001; divide by 512 A[3:0] = 1010; divide by 1024 A[3:0] >= 1011; invalid A[7:4] = Set the Oscillator Frequency. Frequency increases with the value of A[7:4]. Range 0000b~1111b. A[1:0] = 00; GPIO0 input disabled A[1:0] = 01; GPIO0 input enabled A[1:0] = 10; GPIO0 output LOW A[1:0] = 11; GPIO0 output HIGH A[3:2] = 00; GPIO1 input disabled A[3:2] = 01; GPIO1 input enabled A[3:2] = 10; GPIO1 output LOW A[3:2] = 11; GPIO1 output HIGH Sets the second precharge period A[3:0] = DCLKs 0 1100b 10b 10b 1000b Sets the gray scale pulse width in units of DCLK. Range 0‐180d. A1[7:0] = Gamma Setting for GS1 A2[7:0] = Gamma Setting for GS2 . . . A14[7:0] = Gamma Setting for GS14 A15[7:0] = Gamma Setting for GS15 Note: 0 < GS1 < GS2 < GS3 … < GS14 < GS15 The setting must be followed by command 0x00. Sets Linear Grayscale table Linear Gray Scale Table Set Precharge Voltage 0 1 BB A[4:0] 1 * 0 * 1 * 1 A4 1 A3 0 A2 1 A1 1 A0 Set VCOMH Voltage 0 1 BE A[3:0] 1 * 0 * 1 * 1 * 1 A3 1 A2 1 A1 0 A0 Set Contrast Control Master Contrast Control 0 1 0 1 C1 A[7:0] C7 A[3:0] 1 A7 1 * 1 A6 1 * 0 A5 0 * 0 A4 0 * 0 A3 0 A3 0 A2 1 A2 0 A1 1 A1 1 A0 1 A0 Set Multiplex Ratio Set Command Lock 0 1 0 1 CA A[6:0] FD A[2] 1 * 1 0 1 A6 1 0 0 A5 1 0 0 A4 1 1 1 A3 1 0 0 A2 1 A2 1 A1 0 1 0 A0 1 0 GS0 pulse width = 0 GS0 pulse width = 0 GS0 pulse width = 8 GS0 pulse width = 16 . . . GS0 pulse width = 104 GS0 pulse width = 112 Set precharge voltage level. A[4:0] = 0x00; 0.20*VCC . . A[4:0] = 0x3E; 0.60*VCC Sets the VCOMH voltage level A[3:0] = 0x00; 0.72*VCC . . A[3:0] = 0x04; 0.8*VCC . . A[3:0] = 0x07; 0.86*VCC Double byte command to select 1 out of 256 contrast steps. Contrast increases as the value increases. A[3:0] = 0x00; Reduce output for all colors to 1/16 A[3:0] = 0x01; Reduce output for all colors to 2/16 . . A[3:0] = 0x0E; Reduce output for all colors to 15/16 A[3:0] = 0x0F; no change Set MUX ratio to N+1 MUX N=A[6:0]; from 16MUX to 128MUX (0 to 14 are invalid) A[2] = 0; Unlock OLED to enable commands A[2] = 1; Lock OLED from entering commands For detailed instruction information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1322.pdf [9] 0x17 0x04 0x7F 0x0f 127d 0x12 MPU Interface For detailed timing information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1322.pdf 6800‐MPU Parallel Interface The parallel interface consists of 8 bi‐directional data pins, R/W, D/C, E, and /CS. A LOW on R/W indicates write operation, and HIGH on R/W indicates read operation. A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write. The E input serves as data latch signal, while /CS is LOW. Data is latched at the falling edge of E signal. Function Write Command Read Status Write Data Read Data E ↓ ↓ ↓ ↓ R/W 0 1 0 1 /CS 0 0 0 0 D/C 0 0 1 1 8080‐MPU Parallel Interface The parallel interface consists of 8 bi‐directional data pins, /RD, /WR, D/C, and /CS. A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write. A rising edge of /RS input serves as a data read latch signal while /CS is LOW. A rising edge of /WR input serves as a data/command write latch signal while /CS is LOW. Function Write Command Read Status Write Data Read Data /RD /WR 1 ↑ ↑ 1 ↑ 1 ↑ 1 /CS 0 0 0 0 D/C 0 0 1 1 Alternatively, /RD and /WR can be kept stable while /CS serves as the data/command latch signal. Function Write Command Read Status Write Data Read Data /RD /WR 1 0 1 0 0 1 1 0 /CS ↑ ↑ ↑ ↑ D/C 0 0 1 1 [10] Serial Interface (4‐wire) The 4‐wire serial interface consists of serial clock SCLK, serial data SDIN, D/C, and /CS. D0 acts as SCLK and D1 acts as SDIN. D2 should be left open. D3~D7, E, and R/W should be connected to GND. Function Write Command Write Data /RD Tie LOW Tie LOW /WR Tie LOW Tie LOW /CS 0 0 D/C 0 1 D0 ↑ ↑ SDIN is shifted into an 8‐bit shift register on every rising edge of SCLK in the order of D7, D6,…D0. D/C is sampled on every eighth clock and the data byte in the shift register is written to the GDRAM or command register in the same clock. Note: Read is not available in serial mode. Serial Interface (3‐wire) The 3‐wire serial interface consists of serial clock SCLK, serial data SDIN, and /CS. D0 acts as SCLK and D1 acts as SDIN. D2 should be left open. D3~D7, E, R/W, and D/C should be connected to GND. Function Write Command Write Data /RD Tie LOW Tie LOW /WR Tie LOW Tie LOW /CS 0 0 D/C Tie LOW Tie LOW D0 ↑ ↑ SDIN is shifted into an 9‐bit shift register on every rising edge of SCLK in the order of D/C, D7, D6,…D0. D/C (first bit of the sequential data) will determine if the following data byte is written to the Display Data RAM (D/C = 1) or the command register (D/C = 0). Note: Read is not available in serial mode. For detailed protocol information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1322.pdf [11] Example Initialization Sequence: Set_Command_Lock(0x12); // Unlock Basic Commands (0x12/0x16) Set_Display_On_Off(0x00); // Display Off (0x00/0x01) Set_Column_Address(0x1C,0x5B); Set_Row_Address(0x00,0x3F); Set_Display_Clock(0x91); // Set Clock as 80 Frames/Sec Set_Multiplex_Ratio(0x3F); // 1/64 Duty (0x0F~0x3F) Set_Display_Offset(0x00); // Shift Mapping RAM Counter (0x00~0x3F) Set_Start_Line(0x00); // Set Mapping RAM Display Start Line (0x00~0x7F) Set_Remap_Format(0x14); // Set Horizontal Address Increment // Column Address 0 Mapped to SEG0 // Disable Nibble Remap // Scan from COM[N‐1] to COM0 // Disable COM Split Odd Even // Enable Dual COM Line Mode Set_GPIO(0x00); // Disable GPIO Pins Input Set_Function_Selection(0x01); // Enable Internal VDD Regulator Set_Display_Enhancement_A(0xA0,0xFD); // Enable External VSL Set_Contrast_Current(0x9F); // Set Segment Output Current Set_Master_Current(0x0F); // Set Scale Factor of Segment Output Current Control //Set_Gray_Scale_Table(); // Set Pulse Width for Gray Scale Table Set_Linear_Gray_Scale_Table(); //set default linear gray scale table Set_Phase_Length(0xE2); // Set Phase 1 as 5 Clocks & Phase 2 as 14 Clocks Set_Display_Enhancement_B(0x20); // Enhance Driving Scheme Capability (0x00/0x20) Set_Precharge_Voltage(0x1F); // Set Pre‐Charge Voltage Level as 0.60*VCC Set_Precharge_Period(0x08); // Set Second Pre‐Charge Period as 8 Clocks Set_VCOMH(0x07); // Set Common Pins Deselect Voltage Level as 0.86*VCC Set_Display_Mode(0x02); // Normal Display Mode (0x00/0x01/0x02/0x03) Set_Partial_Display(0x01,0x00,0x00); // Disable Partial Display Set_Display_On_Off(0x01); [12] Quality Information Test Item Content of Test High Temperature storage Test the endurance of the display at high storage temperature. Test the endurance of the display at low storage temperature. Test the endurance of the display by applying electric stress (voltage & current) at high temperature. Test the endurance of the display by applying electric stress (voltage & current) at low temperature. Test the endurance of the display by applying electric stress (voltage & current) at high temperature with high humidity. Test the endurance of the display by applying electric stress (voltage & current) during a cycle of low and high temperatures. Test the endurance of the display by applying vibration to simulate transportation and use. Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature / Humidity Operation Thermal Shock resistance Vibration test Atmospheric Pressure test Static electricity test Test Condition Test the endurance of the display by applying atmospheric pressure to simulate transportation by air. Test the endurance of the display by applying electric static discharge. Note +90⁰C , 240hrs 2 ‐40⁰C , 240hrs 1,2 +85⁰C 240hrs 2 ‐40⁰C , 240hrs 1,2 +60⁰C , 90% RH , 240hrs 1,2 ‐40⁰C,30min ‐> 25⁰C,5min ‐> 85⁰C,30min = 1 cycle 100 cycles 10‐22Hz , 15mm amplitude. 22‐500Hz, 1.5G 30min in each of 3 directions X,Y,Z 115mbar, 40hrs 3 VS=800V, RS=1.5kΩ, CS=100pF One time 3 Note 1: No condensation to be observed. Note 2: Conducted after 2 hours of storage at 25⁰C, 0%RH. Note 3: Test performed on product itself, not inside a container. Evaluation Criteria: 1: Display is fully functional during operational tests and after all tests, at room temperature. 2: No observable defects. 3: Luminance >50% of initial value. 4: Current consumption within 50% of initial value Precautions for using OLEDs/LCDs/LCMs See Precautions at www.newhavendisplay.com/specs/precautions.pdf Warranty Information and Terms & Conditions http://www.newhavendisplay.com/index.php?main_page=terms Newhaven Display International, Inc. reserves the right to alter this product or specification at any time without notification. [13]