NHD‐2.7‐12864UCY3 Graphic OLED Display Module NHD‐ 2.7‐ 12864‐ UC‐ Y‐ 3‐ Newhaven Display 2.7” diagonal size 128 x 64 pixel resolution Model Emitting Color: Yellow +3V power supply Newhaven Display International, Inc. 2511 Technology Drive, Suite 101 Elgin IL, 60124 Ph: 847‐844‐8795 Fax: 847‐844‐8796 www.newhavendisplay.com [email protected] [email protected] Document Revision History Revision 0 1 2 Date 5/1/2011 7/01/2011 2/25/2013 Description Initial Product Release Updated Pin Measurement on Mechanical Drawing Electrical characteristics and mechanical drawing updated Functions and Features • • • • • 128 x 64 pixel resolution Built‐in SSD1325 controller Parallel or serial MPU interface Single, low voltage power supply RoHS compliant [2] Changed by ‐ MC JN L A I Mechanical Drawing 1 2 3 4 A Rev D 1 Date T N F N O C 6 Description E D I B C 5 B C D Date 02/25/13 2 A 3 4 Gen. Tolerance Unit ±0.3mm mm 5 Model: NHD-2.7-12864UCY3 6 The drawing contained herein is the exclusive property of Newhaven Display International, Inc. and shall not be copied, reproduced, and/or disclosed in any format without permission. [3] Interface Description Parallel Interface: Pin No. Symbol External Connection Power Supply Power Supply ‐ MPU MPU 1 2 3 4 5 VSS VDD NC D/C R/W or /WR 6 E or /RD MPU 7‐14 15 16 17 18 19 20 DB0 – DB7 NC /RES /CS NC BS2 BS1 MPU ‐ MPU MPU ‐ MPU MPU Function Description Ground Supply Voltage for OLED and logic. No Connect Register select signal. D/C=0: Command, D/C=1: Data 6800‐interface: Read/Write select signal, R/W=1: Read R/W: =0: Write 8080‐interface: Active LOW Write signal. 6800‐interface: Operation enable signal. Falling edge triggered. 8080‐interface: Active LOW Read signal. 8‐bit Bi‐directional data bus lines. No Connect Active LOW Reset signal. Active LOW Chip Select signal. No Connect MPU Interface Select signal. MPU Interface Select signal. Serial Interface: Pin No. Symbol 1 2 3 4 5‐6 7 8 9 10‐14 15 16 17 18 19 20 VSS VDD NC D/C VSS SCLK SDIN NC VSS NC /RES /CS NC BS2 BS1 External Connection Power Supply Power Supply ‐ MPU Power Supply MPU MPU ‐ Power Supply ‐ MPU MPU ‐ MPU MPU Function Description Ground Supply Voltage for OLED and logic. No Connect Register select signal. D/C=0: Command, D/C=1: Data Ground Serial Clock signal. Serial Data Input signal. No Connect Ground No Connect Active LOW Reset signal. Active LOW Chip Select signal. No Connect MPU Interface Select signal. MPU Interface Select signal. MPU Interface Pin Selections Pin Name BS2 BS1 6800 Parallel 8‐bit interface 1 0 8080 Parallel 8‐bit interface 1 1 Serial Interface 0 0 [4] U Interface Pin n Assignmentt Summery MPU Bu us Interrface 8‐bit 6800 8‐bit 8080 SPI Data/C Command Inte erface D7 D6 D D5 D4 D3 D2 D1 D[7:0] D[7:0] Tie LOW NC SDIN D0 SCLK Control Siignals E R/W /CS D/C E R/W /CS D/C /RD /WR /CS D/C Tie LLOW /CS D/C /RESS /RESS /RESS /RESS Wirring Diagrams [5] Electrical Characteristics Item Operating Temperature Range Storage Temperature Range Symbol Top Tst Supply Voltage Supply Current (logic) VDD IDD Supply Current (display) ICC Sleep Mode Current “H” Level input “L” Level input “H” Level output “L” Level output Condition Absolute Max Absolute Max Ta=25°C, VDD=3.3V 50% ON, VDD=3.3V 100% ON, VDD=3.3V IDD+ICCSLEEP Vih Vil Voh Vol Min. ‐40 ‐40 Typ. ‐ ‐ Max. +85 +90 Unit ⁰C ⁰C ‐ ‐ ‐ ‐ ‐ 0.8*VDD VSS 0.9*VDD VSS 3.3 4 175 295 2 ‐ ‐ ‐ ‐ 3.5 4 185 310 10 VDD 0.2*VDD VDD 0.1*VDD V mA mA mA µA V V V V Optical Characteristics Item Viewing Angle – Top Viewing Angle – Bottom Viewing Angle – Left Viewing Angle – Right Contrast Ratio Response Time (rise) Response Time (fall) Brightness Lifetime Symbol AV AV AH AH Cr Tr Tf Condition Min. ‐ ‐ ‐ ‐ 2000:1 ‐ ‐ 70 40,000 Typ. 80 80 80 80 ‐ 10 10 100 ‐ Max. ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ Unit ⁰ ⁰ ⁰ ⁰ ‐ us us cd/m2 Hrs ‐ ‐ 50% checkerboard Ta=25°C, 50% checkerboard Note: Lifetime at typical temperature is based on accelerated high‐temperature operation. Lifetime is tested at average 50% pixels on and is rated as Hours until Half‐Brightness. The Display OFF command can be used to extend the lifetime of the display. Luminance of active pixels will degrade faster than inactive pixels. Residual (burn‐in) images may occur. To avoid this, every pixel should be illuminated uniformly. [6] Built‐in SSD1325 controller Instruction Table Instruction Code DB5 DB4 0 1 A5 A4 B5 B4 1 1 A5 A4 B5 B4 0 0 A5 A4 0 0 D/C 0 0 0 0 0 0 0 0 0 HEX 15 A[5:0] B[5:0] 75 A[6:0] B[6:0] 81 A[6:0] 84~86 DB7 0 * * 0 * * 1 * 1 DB6 0 * * 1 A6 B6 0 A6 0 Set Remap 0 0 A0 A[6:0] 1 * 0 A6 1 * Set Display Start Line Set Display Offset Display Mode 0 0 0 0 0 A1 A[6:0] A2 A[6:0] A4/A7 1 * 1 * 1 0 A6 0 A6 0 Set Multiplex Ratio Master configuration 0 0 0 0 A8 A[6:0] AD A[1:0] 1 * 1 * Set Display ON/ OFF 0 AE~AF 1 Set Column Address Set Row Address Set Contrast Control Set Current Range DB3 0 A3 B3 0 A3 B3 0 A3 0 DB2 1 A2 B2 1 A2 B2 0 A2 1 DB1 0 A1 B1 0 A1 B1 0 A1 X1 DB0 1 A0 B0 1 A0 B0 1 A0 X0 0 A4 0 * 0 A2 0 A1 0 A0 1 A5 1 A5 1 0 A4 0 A4 0 0 A3 0 A3 0 0 A2 0 A2 X2 0 A1 1 A1 X1 1 A0 0 A0 X0 0 A6 0 * 1 A5 1 * 0 A4 0 * 1 A3 1 * 0 A2 1 * 0 A1 0 A1 0 A0 1 A0 0 1 0 X3 1 1 1 [7] Description RESET value Set column start and end address A[5:0]: Column start address. Range: 0‐63d B[5:0]: Column end address. Range: 0‐63d 0 63d Set row start and end address A[6:0]: Row start address. Range: 0‐79d B[6:0]: Row end address. Range: 0‐79d 0 79d Double byte command to select 1 out of 128 contrast steps. Contrast increases as the value increases. 0x40 0x84 = Quarter Current Range 0x85 = Half Current Range 0x86 = Full Current Range A[0] = 0; Disable Column Address remap A[0] = 1; Enable Column Address remap A[1] = 0; Disable Nibble remap A[1] = 1; Enable Nibble remap A[2] = 0; Horizontal Address Increment A[2] = 1; Vertical Address Increment A[4] = 0; Disable COM remap A[4] = 1; Enable COM A[6] = 0; Disable COM split Odd/Even A[6] = 1; Enable COM split Odd/Even Set display RAM display start line register from 0‐79. 0x84 Set vertical shift by COM from 0~79. 0 0 0 0 0 0 0 0xA4 = Normal display 0xA5 = Entire display ON, all pixels Grayscale level 15 0xA6 = Entire display OFF 0xA7 = Inverse display Set MUX ratio to N+1 MUX N=A[6:0]; from 16MUX to 80MUX (0 to 14 are invalid) 0xA4 A[0] = 0; Disable DC‐DC converter A[0] = 1; Enable DC‐DC converter A[1] = 0; Disable internal VCOMH A[1] = 1; Enable internal VCOMH 0xAE = Display OFF (sleep mode) 0xAF = Display ON 1 1 AEh 80 Set VCOMH Voltage Set Precharge Voltage 0 0 0 0 BE A[5:0] BC A[7:0] 1 * 1 A7 0 * 0 A6 1 A5 1 A5 1 A4 1 A4 1 A3 1 A3 1 A2 1 A2 1 A1 0 A1 0 A0 0 A0 Set Phase Length 0 0 0 0 0 0 0 0 B1 A[3:0] A[7:4] B2 A[7:0] B3 A[3:0] A[7:4] 1 * A7 1 A7 1 * A7 0 * A6 0 A6 0 * A6 1 * A5 1 A5 1 * A5 1 * A4 1 A4 1 * A4 0 A3 * 0 A3 0 A3 * 0 A2 * 0 A2 0 A2 * 0 A1 * 1 A1 1 A1 * 1 A0 * 0 A0 1 A0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B8 A[2:0] B[2:0] B[6:4] C[2:0] C[6:4] D[2:0] D[6:4] E[2:0] E[6:4] F[2:0] F[6:4] G[2:0] G[6:4] H[2:0] H[6:4] CF A[7:6] 1 * * * * * * * * * * * * * * * 1 A7 0 * * B6 * C6 * D6 * E6 * F6 * G6 * H6 1 A6 0 * * B5 * C5 * D5 * E5 * F5 * G5 * H5 0 * 0 * * B4 * C4 * D4 * E4 * F4 * G4 * H4 0 * 1 * * * * * * * * * * * * * * * 1 * 0 A2 B2 * C2 * D2 * E2 * F2 * G2 * H2 * 1 * 0 A1 B1 * C1 * D1 * E1 * F1 * G1 * H1 * 1 * 0 A0 B0 * C0 * D0 * E0 * F0 * G0 * H0 * 1 * 0 E3 1 1 1 0 0 0 1 1 Set Row Period Set Display Clock Divide Ratio / Oscillator Frequency Set Grayscale Table Set Biasing Current for DC‐DC converter NOP Sets the VCOMH voltage level 000000‐011111. A[5:0] = 1xxxxx = 1.0*VREF Sets the precharge voltage level 00000000‐00011111 A[7:0] = 1xxxxxxx connects to VCOMH A[7:0] = 001xxxxx equals 1.0*VREF A[3:0] = P1. Phase 1 period of 1‐15 DCLK clocks A[7:4] = P2. Phase 2 period of 1‐15 DCLK clocks 00011000 Sets number of DCLKs (K) per row. Range 2‐158DCLKs. K = P1 + P2 + GS15 pulse width (RESET values: 3 + 5 + 29) 37DCLKs (0x25) A[3:0] = Define the divide ratio of the display clocks. Range 1‐16 Divide ratio = A[3:0] +1 A[7:4] = Set the Oscillator Frequency. Frequency increases with the value of A[7:4]. Range 0000b~1111b. 3 5 2 0 Sets the gray scale level. Range 1‐15 A[2:0] = L1 B[2:0] = L2 B[6:4] = L3 C[2:0] = L4 C[6:4] = L5 D[2:0] = L6 D[6:4] = L7 E[2:0] = L8 E[6:4] = L9 F[2:0] = L10 F[6:4] = L11 G[2:0] = L12 G[6:4] = L13 H[2:0] = L14 H[6:4] = L15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xF0 = HIGH 0x70 = LOW 0xF0 Command for No Operation For detailed instruction information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1325.pdf [8] 010001 MPU Interface For detailed timing information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1325.pdf 6800‐MPU Parallel Interface The parallel interface consists of 8 bi‐directional data pins, R/W, D/C, E, and /CS. A LOW on R/W indicates write operation, and HIGH on R/W indicates read operation. A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write. The E input serves as data latch signal, while /CS is LOW. Data is latched at the falling edge of E signal. Function Write Command Read Status Write Data Read Data E ↓ ↓ ↓ ↓ R/W 0 1 0 1 /CS 0 0 0 0 D/C 0 0 1 1 8080‐MPU Parallel Interface The parallel interface consists of 8 bi‐directional data pins, /RD, /WR, D/C, and /CS. A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write. A rising edge of /RS input serves as a data read latch signal while /CS is LOW. A rising edge of /WR input serves as a data/command write latch signal while /CS is LOW. Function Write Command Read Status Write Data Read Data /RD /WR 1 ↑ ↑ 1 ↑ 1 ↑ 1 /CS 0 0 0 0 D/C 0 0 1 1 Alternatively, /RD and /WR can be kept stable while /CS serves as the data/command latch signal. Function Write Command Read Status Write Data Read Data /RD /WR 1 0 1 0 0 1 1 0 /CS ↑ ↑ ↑ ↑ D/C 0 0 1 1 [9] Serial Interface The serial interface consists of serial clock SCLK, serial data SDIN, D/C, and /CS. D0 acts as SCLK and D1 acts as SDIN. D2 should be left open. D3~D7, E, and R/W should be connected to GND. Function Write Command Write Data /RD /WR 0 0 0 0 /CS 0 0 D/C 0 1 D0 ↑ ↑ SDIN is shifted into an 8‐bit shift register on every rising edge of SCLK in the order of D7, D6,…D0. D/C is sampled on every eighth clock and the data byte in the shift register is written to the GDRAM or command register in the same clock. Note: Read is not available in serial mode. For detailed protocol information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1325.pdf [10] Example Initialization Sequence: Set_Display_On_Off_12864(0x00); // Display Off (0x00/0x01) Set_Display_Clock_12864(0x91); // Set Clock as 135 Frames/Sec Set_Multiplex_Ratio_12864(0x3F); // 1/64 Duty (0x0F~0x5F) Set_Display_Offset_12864(0x4C); // Shift Mapping RAM Counter (0x00~0x5F) Set_Start_Line_12864(0x00); // Set Mapping RAM Display Start Line (0x00~0x5F) Set_Master_Config_12864(0x00); // Disable Embedded DC/DC Converter (0x00/0x01) Set_Remap_Format_12864(0x50); // Set Column Address 0 Mapped to SEG0 // Disable Nibble Remap // Horizontal Address Increment // Scan from COM[N‐1] to COM0 // Enable COM Split Odd Even Set_Current_Range_12864(0x02); // Set Full Current Range Set_Gray_Scale_Table_12864(); // Set Pulse Width for Gray Scale Table Set_Contrast_Current_12864(brightness); // Set Scale Factor of Segment Output Current Control Set_Frame_Frequency_12864(0x51); // Set Frame Frequency Set_Phase_Length_12864(0x55); // Set Phase 1 as 5 Clocks & Phase 2 as 5 Clocks Set_Precharge_Voltage_12864(0x10); // Set Pre‐Charge Voltage Level Set_Precharge_Compensation_12864(0x20,0x02); // Set Pre‐Charge Compensation Set_VCOMH_12864(0x1C); // Set High Voltage Level of COM Pin Set_VSL_12864(0x0D); // Set Low Voltage Level of SEG Pin Set_Display_Mode_12864(0x00); // Normal Display Mode (0x00/0x01/0x02/0x03) Fill_RAM_12864(0x00); // Clear Screen Set_Display_On_Off_12864(0x01); // Display On (0x00/0x01) [11] Quality Information Test Item Content of Test High Temperature storage Test the endurance of the display at high storage temperature. Test the endurance of the display at low storage temperature. Test the endurance of the display by applying electric stress (voltage & current) at high temperature. Test the endurance of the display by applying electric stress (voltage & current) at low temperature. Test the endurance of the display by applying electric stress (voltage & current) at high temperature with high humidity. Test the endurance of the display by applying electric stress (voltage & current) during a cycle of low and high temperatures. Test the endurance of the display by applying vibration to simulate transportation and use. Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature / Humidity Operation Thermal Shock resistance Vibration test Atmospheric Pressure test Static electricity test Test Condition Test the endurance of the display by applying atmospheric pressure to simulate transportation by air. Test the endurance of the display by applying electric static discharge. Note +90⁰C , 240hrs 2 ‐40⁰C , 240hrs 1,2 +85⁰C 240hrs 2 ‐40⁰C , 240hrs 1,2 +60⁰C , 90% RH , 240hrs 1,2 ‐40⁰C,30min ‐> 25⁰C,5min ‐> 85⁰C,30min = 1 cycle 100 cycles 10‐22Hz , 15mm amplitude. 22‐500Hz, 1.5G 30min in each of 3 directions X,Y,Z 115mbar, 40hrs 3 VS=800V, RS=1.5kΩ, CS=100pF One time 3 Note 1: No condensation to be observed. Note 2: Conducted after 2 hours of storage at 25⁰C, 0%RH. Note 3: Test performed on product itself, not inside a container. Evaluation Criteria: 1: Display is fully functional during operational tests and after all tests, at room temperature. 2: No observable defects. 3: Luminance >50% of initial value. 4: Current consumption within 50% of initial value Precautions for using OLEDs/LCDs/LCMs See Precautions at www.newhavendisplay.com/specs/precautions.pdf Warranty Information and Terms & Conditions http://www.newhavendisplay.com/index.php?main_page=terms Newhaven Display International, Inc. reserves the right to alter this product or specification at any time without notification. [12]