Video ICs SECAM chroma signal processor for VHS VCRs BA7207AS / BA7207AK The BA7207AS and BA7207AK are LSI components that incorporate the contain circuitry required for SECAM chroma signal processing. The ICs have both recording and playback systems and each includes a bell filter, a bandpass filter, a limiter amplifier, a multiply-by-four circuit, a divide-by-four circuit, and a sync-gate circuit. Applications •SECAM and VHS format video cassette recorders and camcorders •1)Features All filters required for SECAM chroma signal pro- 3) Built-in switch circuit for selecting PAL chroma or SECAM chroma for the PB / REC system output. cessing are provided. 2) Built-in chroma killer circuit. •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Power supply voltage Power dissipation Operating temperature VCC BA7207AS BA7207AS V – 25 ~ + 75 mW °C – 25 ~ + 65 Tstg Storage temperature 7 850 (QFP44)∗2 Topr BA7207AK Unit 1400 (SDIP32)∗1 Pd BA7207AK Limits – 55 ~ + 125 °C ∗1 Reduced by 14mW for each increase in Ta of 1°C over 25°C . ∗2 When mounted on a 70mm × 70mm, t = 1.6mm glass epoxy board, reduced by 8.5W for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (Ta = 25°C) Parameter Operating power supply voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V 1 Video ICs BA7207AS / BA7207AK •Block diagram VREG TRAP RECOUT CREF2 ABELO CREF1 LAIN VCC LAO CTL CREF3 RECH PBIN BWL 32 PALRIN × 4O BA7207AS (SDIP32) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 MODE CONTOROL VREG PAL SCM ×2 P ×2 2.2MHz BPF LIM R EQ P P PB SYNC GATE 4.3MHz BPF - B P R 4.3MHz BPF—A LIM P 1.1MHz BPF R R ÷4 REC SYNC GATE R BELL R P DET VCO SCM PAL SYNC GATE TIMING GENERATOR 15 16 DIV SYNCIN CTL SGADJ PALPIN PBOUT 14 SGC VCO 13 LAO 12 VCC 11 N.C. 10 LAIN GND DET AMPOUT 9 N.C. GND1 8 SCMPIN 7 CREF1 6 N.C. 5 ABELO FADJ2 4 CREF2 MUL BA7207AK (SQFP44) 3 FADJ1 2 RECOUT 1 RECIN FREQUENCY ADJUSTER 33 32 31 30 29 28 27 26 25 24 23 VCC TRAP 34 22 CREF3 21 RECH 20 PBIN 19 N.C. 18 BWL 17 N.C. 16 SYNCIN 15 N.C. 14 DIV 13 PALPIN 12 SGC LIM PALRIN MODE CONTROL 35 PAL SCM VREG 36 N.C. 37 × 4O VREG ×2 38 RECIN 39 4.3MHz BPF—A 2 BELL FREQUENCY ADJUSTER DET VCO SYNC GATE TIMING GENERATOR 1 2 3 4 5 6 7 8 9 10 11 DET N.C. VCO PBOUT SGADJ SCM PAL N.C. 44 P SCMPIN FADJ2 REC SYNC GATE ÷4 N.C. 43 PB SYNC GATE GND FADJ1 4.3MHz BPF—B AMPOUT 42 R GND1 MUL P R R 41 1.1MHz BPF EQ R P 40 N.C. LIM R P N.C. P ×2 2.2MHz BPF P R Video ICs BA7207AS / BA7207AK •Pin descriptions Pin No. Pin name 1 (40) 2 (42) RECIN MUL Function Recording system input. Input the REC system chroma signal. PB sync gate output. Test pin. Outputs the chroma signal after it is multiplied by four and passed through the sync gate. Normally connected to VCC to prevent interference. FADJ1 Filter fo adjustment pin 1. Used to adjust fo for the equalizer, 1.1MHz BPF and 2.2MHz BPF. Connect a resistor and variable resistor from this pin to GND. 4 (44) FADJ2 Filter fo adjustment pin 2. Used to adjust fo for the bell filter, 4.3MHz BPF-A and 4.3MHz BPF-B. Connect a resistor and variable resistor from this pin to GND. 5 (1) GND1 Ground. 3 (43) PB system preamplifier output. Pin No. Pin name 17 (18) BWL Chroma killer mode setting . "L" sets the IC in chroma killer mode. 18 (20) PBIN PB system input . Input chroma signal for the PB system. 19 (21) RECH 7 (3) 8 (5) 9 (7) 10 (9) GND Bias terminal for the limiter amplifier before × 2. CTL SECAM / PAL output switch. Selects the signal output for the REC / PB terminal. Set to open or "H" for SECAM output mode, "L" for PAL mode. 22 (24) LAO Limiter amplifier output. Test pin. Outputs the amplitude-limited chroma signal. Normally connected to VCC to prevent interference. 23 (25) VCC Power supply. 24 (27) LAIN 21 (23) SCMPIN Ground. PB system output amplifier input. Input the level-adjusted PB system SECAM chroma signal. REC / PB mode switch. Set to open or "H" for REC mode, "L" for PB mode. 20 (22) CREF3 Connect to GND via a capacitor. 6 (2) AMPOUT Connect to GND via a variable resistor to adjust the level, and input to pin 8. Function Limiter amplifier input. Input the de-emphasised chroma signal. Limiter amplifier bias pin 1. 25 (29) CREF1 Connect to GND via a capacitor. DET Phase comparator output. Connect to GND via a RC LPF to obtain the error voltage. 26 (31) ABELO VCO VCO oscillator frequency control pin. The error voltage is input via a resistor. Connected to GND via free-running frequency setting resistor. 27 (32) CREF2 Connect to GND via a capacitor. PB system output. 11 (10) PBOUT Outputs the PB system chroma signal. 12 (11) SGADJ Fine adjustment for the sync gate phase. The voltage from a resistor divider is used for fine adjustment of the gate phase of the sync gate. Normally open. 13 (12) Sync gate timing output. Test pin. Outputs the REC sync gate timing. Normally open. REC BELL output. When in REC mode, de-emphasised chroma signal is output via REC BELL. When in PB mode, the PB system chroma signal is output after being multiplied by four. Limiter amplifier bias pin 2. REC system output. 28 (33) RECOUT REC system chroma signal output. 29 (34) TRAP TRAP connection. Connect TRAP that rejects spurious signal component after × 2 multiplication. PAL REC system input. SGC PAL PB system input. 30 (35) PALRIN PAL REC system chroma signal input. 31 (36) VREG 14 (13) PALPIN Input chroma signal for the PAL PB system. 15 (14) 16 DIV Divide-by-four divider output. Test pin. Outputs the chroma signal after it has been divided by four. Normally connected to VCC to prevent interference. Delayed sync signal input. 32 (38) × 40 Regulated voltage output. Output for the regulated 2.5V reference voltage used for internal biasing. Connect to GND via a bypass capacitor. × 4 multiply output. Test pin. Outputs the chroma signal after it is multiplied by four. Normally connected to VCC to prevent interference. BA7207AK pin numbers are given in brackets. SYNCIN Input the synchronously-separated composite 3 Video ICs BA7207AS / BA7207AK •Input / output circuits 1pin (40pin) 2pin (42pin) 3pin (43pin) VCC VCC VCC VCC VCC 40k RECIN FADJ1 MUL 40k GND GND GND GND 4pin (44pin) 5pin (1pin) 6pin (2pin) VCC VCC VCC VCC GND1 FADJ2 GND AMPOUT 5k GND GND GND 7pin (3pin) 8pin (5pin) 9pin (7pin) VCC VCC 20k 20k GND SCMPIN SCMPIN GND 30k GND 4 30k GND Video ICs BA7207AS / BA7207AK 10pin (9pin) 11pin (10pin) 12pin (11pin) VCC VCC VCC VCC 50k 5k VCC 12k 100k SGADJ VCO GND PBOUT GND 2.2k 50k GND GND GND 13pin (12pin) 14pin (13pin) 15pin (14pin) VCC VCC VCC VCC 20k 10k PALPIN SGC 30k 10k DIV GND GND GND 16pin 17pin (18pin) 18pin (20pin) VCC VCC VCC 20k 50k 15k PBIN BWL SYNCIN 35k 20k GND GND GND 19pin (21pin) 20pin (22pin) 21pin (23pin) VCC VCC VCC 50k 50k RECH CTL CREF3 GND GND GND 5 Video ICs BA7207AS / BA7207AK 22pin (24pin) 23pin (25pin) 24pin (27pin) VCC VCC LAIN VCC VCC 2k VCC LAO GND GND GND 25pin (29pin) 26pin (31pin) 27pin (32pin) VCC VCC VCC VCC 2k 2k CREF2 CREF1 30k 30k ABELO GND GND 1.8k GND 28pin (33pin) GND GND 29pin (34pin) 30pin (35pin) VCC VCC VCC VCC 20k 560 PALRIN TRAP 200 RECOUT 30k 1.8k GND GND GND 31pin (36pin) 32pin (38pin) VCC VCC VCC VCC VREG × 4O 3k 3k GND 5.3k GND Pin numbers in parentheses are for the BA7207AK. 6 Video ICs BA7207AS / BA7207AK •Electrical characteristics (unless otherwise noted, Ta = 25°C, V CC Parameter = 5.0V) Symbol Min. Typ. Max. Unit Conditions IREC 39.2 56.0 72.8 mA REC mode PB mode Measurement circuit [Total device] REC mode supply current PB mode supply current Fig.1 IPB 46.9 67.0 87.1 mA VREG 2.38 2.53 2.68 V VCO free-running frequency fosc 13.8 15.625 17.4 kHz Capture range "H" CRH 1.8 — — kHz Delayed sync input Fig.1 Capture range "L" CRL — — – 1.8 kHz Delayed sync input Fig.1 Lock range "H" LRH 2.2 — — kHz Delayed sync input Fig.1 Lock range "L" LRL — — – 2.2 kHz Delayed sync input Fig.1 Cyan level (cyan frequency) Fig.1 Regulator voltage Fig.1 Fig.1 [Sync-gate block] Fig.1 [REC system] RECOUT output amplitude VREC 187.5 250.0 312.5 mVP-P Unwanted spectrum rejection 4MHz component HDR4 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 3MHz component HDR3 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 2MHz component HDR2 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 Output switch voltage gain GRS –1 0 1 dB V30 = 0.3VP-P, 627kHz Fig.1 Output switch frequency characteristic fRS –1 0 1 dB V30 = 0.3VP-P, 5MHz / 100kHz Fig.1 Output switch crosstalk 1 CTR1 — – 60 — dB V18 = 25mVP-P, 1.0715MHz Fig.1 Output switch crosstalk 2 CTR2 — – 60 — dB V30 = 0.3VP-P, 627kHz Fig.1 Cyan level (cyan frequency) Fig.1 [PB system] PB output amplitude VPB 202.5 270.0 337.5 mVP-P Unwanted spectrum rejection 3MHz component HDP3 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 2MHz component HDP2 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 1MHz component HDP1 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 GP1 5 6 7 dB V8 = 0.3VP-P, 4.3MHz Fig.1 fP1 –1 Output switch voltage gain 1 Output switch frequency characteristic 1 Output switch crosstalk 1 CTP1 Output switch voltage gain 2 GP2 –1 fP2 –1 Output switch frequency characteristic 2 — 0 1 dB V8 = 0.3VP-P, 5MHz / 100kHz Fig.1 – 60 — dB V8 = 0.3VP-P, 4.3MHz Fig.1 0 1 dB V14 = 0.3VP-P, 4.43MHz Fig.1 0 1 dB V14 = 0.3VP-P, 5MHz / 100kHz Fig.1 Output switch crosstalk 2 CTP2 — – 60 — dB V14 = 0.3VP-P, 4.43MHz Fig.1 RECIN crosstalk CTRIN — – 40 – 30 dB V1 = 0.5VP-P, 4.286MHz Fig.1 High level voltage VH 2.5 — — V Low level voltage VL — — 1.5 V [Control system] Pins 14, 17, 19, 21 and 30 (Pins 13,18,21,23 and 35)∗ Pins 14, 17, 19, 21 and 30 (Pins 13,18,21,23 and 35)∗ Fig.1 Fig.1 ∗ BA7207AK pin numbers are given in brackets. 7 Video ICs BA7207AS / BA7207AK Parameter Typ. Max. Unit Conditions Measurement circuit Symbol Min. 1.1MHz voltage gain GF11 – 2.8 0.7 4.2 dB V18 = 25mVP-P, 1.0715MHz Fig.1 0.5MHz voltage gain GF12 – 6.5 – 3.0 0.5 dB V18 = 25mVP-P, 0.5MHz Fig.1 3.2MHz voltage gain GF13 — – 35.0 – 26.0 dB V18 = 25mVP-P, 3.2145MHz Fig.1 4.3MHz voltage gain GF31 – 11.3 – 7.8 – 4.3 dB V1 = 500mVP-P, 4.286MHz Fig.1 3.2MHz voltage gain GF32 – 16.1 – 12.6 – 9.1 dB V1 = 500mVP-P, 3.2MHz Fig.1 5.5MHz voltage gain GF33 – 14.0 – 10.5 – 7.0 dB V1 = 500mVP-P, 5.5MHz Fig.1 [Filter block] 〈1.1MHz BPF characteristic〉 〈4.3MHz BPF - A characteristic〉 〈REC BELL + 4.3MHz BPF - A characteristic〉 GRB1 – 0.7 2.8 6.3 dB V1 = 170mVP-P, 4.286MHz Fig.1 4.1MHz voltage gain GRB2 – 7.0 – 3.5 0 dB V1 = 170mVP-P, 4.1MHz Fig.1 4.5MHz voltage gain GRB3 – 7.2 – 3.7 – 0.2 dB V1 = 170mVP-P, 4.5MHz Fig.1 4.3MHz voltage gain 〈PB BELL + 4.3MHz BPF - A characteristic〉 4.3MHz voltage gain GPB1 – 20.9 – 17.4 – 13.9 dB V1 = 800mVP-P, 4.286MHz Fig.1 4.1MHz voltage gain GPB2 – 16.2 – 12.7 – 9.2 dB V1 = 800mVP-P, 4.1MHz Fig.1 4.5MHz voltage gain GPB3 – 15.3 – 11.8 – 8.3 dB V1 = 800mVP-P, 4.5MHz Fig.1 1.1MHz voltage gain GRE1 – 4.0 – 0.5 3.0 dB V18 = 95mVP-P, 1.0715MHz Fig.1 1.0MHz voltage gain GRE2 4.1 7.6 11.1 dB V18 = 95mVP-P, 1.0MHz Fig.1 1.2MHz voltage gain GRE3 6.7 10.2 13.7 dB V18 = 95mVP-P, 1.2MHz Fig.1 1.1MHz voltage gain GPE1 2.5 6.0 9.5 dB V18 = 25mVP-P, 1.0715MHz Fig.1 1.0MHz voltage gain GPE2 – 5.1 – 1.6 1.9 dB V18 = 25mVP-P, 1.0MHz Fig.1 1.2MHz voltage gain GPE3 – 8.9 – 5.4 – 1.9 dB V18 = 25mVP-P, 1.2MHz Fig.1 〈REC EQ + 1.1MHz BPF characteristic〉 〈PB EQ + 1.1MHz BPF characteristic〉 •Guaranteed design parameters (unless otherwise noted, Ta = 25°C, V CC Parameter = 5.0V, delayed sync input) Symbol Min. Typ. Max. Unit TDR 1.3 2.4 3.5 µs DIV (pin 14 / pin 15), REC mode PB sync-gate phase TDP 0.5 1.6 2.7 µs MUL (pin 2 / pin 42), PB mode REC sync-gate amplitude TWR 4.9 5.2 5.5 µs DIV (pin 15 / pin 14), REC mode PB sync-gate amplitude TWP 6.1 6.4 6.7 µs MUL (pin 2 / pin 42), PB mode REC sync-gate phase Conditions The pin numbers in brackets are for the BA7207AS and the BA7207AK respectively. 8 Video ICs BA7207AS / BA7207AK Reference design data •(unless otherwise noted, Ta = 25°C, V Parameter CC = 5.0V, fo (REC BELL) = 4.286MHz, fo (PB EQ) = 1.0715MHz) Symbol Min. Typ. Max. Unit Conditions 1.1MHz gain GF11 — 1.0 — dB VIN = 0.3VP-P, 1.0715MHz 0.5MHz suppression ratio GF12 — – 4.0 — dB VIN = 0.3VP-P, 0.5MHz 3.2MHz suppression ratio GF13 — – 30.0 — dB VIN = 0.3VP-P, 3.2145MHz Groupe delay time DF1 370 470 nS VIN = 0.3VP-P, 1.0715MHz 2.2MHz gain GF21 — – 6.0 — dB VIN = 0.3VP-P, 2.143MHz 1.1MHz suppression ratio GF22 — – 25.0 — dB VIN = 0.3VP-P, 1.0715MHz 3.2MHz suppression ratio GF23 — – 25.0 — dB VIN = 0.3VP-P, 3.2145MHz Groupe delay time DF2 180 230 280 ns VIN = 0.3VP-P, 2.143MHz 4.3MHz gain GF31 — 7.0 — dB VIN = 0.1VP-P, 4.286MHz 3.2MHz suppression ratio GF32 — – 3.0 — dB VIN = 0.1VP-P, 3.2MHz 5.5MHz suppression ratio GF33 — – 3.0 Groupe delay time DF3 160 4.3MHz gain GF41 3.5MHz suppression ratio GF42 〈1.1MHzBPF〉 420 〈2.2MHzBPF〉 〈4.3MHz BPF - A〉 — dB VIN = 0.1VP-P, 5.5MHz 210 260 nS VIN = 0.1VP-P, 4.286MHz — 9.0 — dB VIN = 0.1VP-P, 4.286MHz — – 3.0 — dB VIN = 0.1VP-P, 3.5MHz 5.2MHz suppression ratio GF43 — – 3.0 — dB VIN = 0.1VP-P, 5.2MHz Groupe delay time DF4 250 300 350 nS VIN = 0.1VP-P, 4.286MHz 4.3MHz gain GRB1 — 19.5 — dB VIN = 0.3VP-P, 4.286MHz 4.1MHz suppression ratio GRB2 — – 5.0 — dB VIN = 0.3VP-P, 4.1MHz 4.5MHz suppression ratio GRB3 — – 5.5 — dB VIN = 0.3VP-P, 4.5MHz 4.3MHz gain GPB1 — – 19.5 — dB VIN = 0.3VP-P, 4.286MHz 4.1MHz gain GPB2 — 5.0 — dB VIN = 0.3VP-P, 4.1MHz 4.5MHz gain GPB3 — 5.5 — dB VIN = 0.3VP-P, 4.5MHz Center frequency ratio dfOB –1 0 1 % dfOB = (fO (PB) – fO (REC) ) / fO (REC) 1.1MHz gain GRE1 — 19.5 — dB VIN = 0.3VP-P, 1.0715MHz 1.0MHz suppression ratio GRE2 — – 8.0 — dB VIN = 0.3VP-P, 1.0MHz 1.2MHz suppression ratio GRE3 — – 11.0 — dB VIN = 0.3VP-P, 1.2MHz 1.1MHz gain GPE1 — – 19.5 — dB VIN = 0.3VP-P, 1.0715MHz 1.0MHz gain GPE2 — 8.0 — dB VIN = 0.3VP-P, 1.0MHz 1.2MHz gain GPE3 — 11.0 — dB VIN = 0.3VP-P, 1.2MHz Center frequency ratio dfOE –1 0 1 % dfOE = (fO (REC) – fO (PB) ) / fO (PB) 〈4.3MHz BPF - B〉 〈REC BELL〉 〈PB BELL〉 〈PB EQ〉 〈REC EQ〉 9 Video ICs BA7207AS / BA7207AK •Measurement circuits BA7207AS (SDIP32) 1 N 1 2 SW30b N N 1 2 2 SW21 SW19 OSC30 OSC18 1 2 1 2 SW30a 0.01µ VREG SW18 RECOUT Vcc 0.1µ 27p 0.1µ I23 0.1µ 47µ A Vcc 0.1µ 32 47µ 31 30 0.01µ 0.1µ Vcc + 0.01µ 29 28 27 26 25 24 23 22 21 20 19 18 17 RECH CTL BWL MODE CONTOROL Vreg PAL ×2 SCM LIM R ×2 2.2MHz BPF LIM P P 1.1MHz BPF EQ R 4.3MHz BPF - B P P 4.3MHz BPF - A R BELL ÷4 PB SYNC GATE REC SYNC GATE R R R P DET SYNC GATE TIMING GENERATOR VCO SCM PAL FREQUENCY ADJUSTER 1 2 3 SW2 0.01µ 1 OSC1 2 1 3.9k V 4 SW3 2 1 5 7 8 9 0.01µ 2k VR2 12 13 14 15 0.47µ + 7.5k 1 2 1 2 33k PBOUT 1 SGC SW14a 1 3 OSC8 470 12µ 100P 3.3k 0.01 µ SW8 470 16 SW15 4700p AMPOUT Vcc 11 10k 8.5k 7.5k 10 100k SW4 2 2k VR1 8.5k 6 SW16 2 V SG16 Vcc 2 OSC14 560p SW14b 1 N 2 1.5V Fig. 1 10 2.5V Video ICs BA7207AS / BA7207AK BA7207AK (QFP44) 1 N 1 N 2 2 1 N 2 1 N 2 REC OUT SW21 SW30b SW19 SW4b 2.5V 1.5V VCC 0.1µ 0.1µ I23 33 OSC30 31 30 47µ VCC + 29 28 27 26 25 24 23 0.1µ 27p ~ 1 32 A 0.1µ 0.01µ VCC 47µ 2 34 SW30a 22 LIM 0.01µ MODE CONTROL 35 PAL SCM VREG VREG 36 21 20 0.01µ 0.1µ 37 VCC 19 38 2.2MHz BPF ×2 ×2 ~ OSC1 41 1 OSC18 17 R BELL P 4.3MHz BPF—B PB SYNC GATE REC SYNC GATE ÷4 16 R 1 SW16 P FREQUENCY ADJUSTER DET SYNC GATE TIMING GENERATOR VCO 42 SW2 2 2 ~ 18 R R P 4.3MHz BPF—A 40 0.01µ 1.1MHz BPF EQ R P 39 LIM P R P SW18 100p 15 1 2 SG16 14 SCM PAL 43 13 0.01µ 3.9k 44 SW3 VCC 1 2 12 SW4 1 SW14a 1 2 SW15 1 2 ~ OSC14 2k VR1 8.5k 7.5k 2k VR2 8.5k 1 2 3 4 5 6 7 8 9 10 11 2 3.3k VCC 100k 0.01µ 7.5k 470 SW8 1 2 PB SG OUT 12µ 470 ~ 3 OSC8 10k + 33k 4700p 0.47µ 560p AMP OUT PB OUT SGC REC SG OUT Fig. 2 11 Video ICs BA7207AS / BA7207AK operation •(1)Circuit Recording system (REC) The input to REC IN is passed through the 4.3MHz BPF-A to remove unwanted frequency components, and is flattened by REC BELL which has an anti-bell characteristic. The flattened signal is wave-shaped by the limiter amplifer, and processed by the divide-by-four and sync gate circuits. Finally, unwanted frequency components are removed by the 1.1MHz BPF and the REC EQ prepares the signal for recording playback and the signal is output on REC OUT. Refer to Fig. 3. Composite video signal 4.3MHz BPF - A 1 100pF ( 40 REC BELL 26 ( ) 24 31 ) ( 27 REC SYNC GATE ÷4 LIMAMP 1.1MHz BPF RECOUT REC EQ AMP 28 ( ) 33 ) BA7207AS (BA7207AK) Fig. 3 (2) Playback system (PB) The input to PB IN is passed through the 1.1MHz BPF to remove unwanted frequency components, and is flattened by the PB EQ circuit. The amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency is multiplied by four by the multiplier circuit. Unwanted frequency components generated by the multiplier circuit are removed by the 2.2MHz BPF and 4.3MHz BPF-A. The signal is wave-shaped by the limiter amplifier, and has gate applied to it by the sync gate circuit then is passed through the 4.3MHz BPF-B to remove unwanted frequency components. The PB BELL circuit restores the original bell characteristic and the signal is output on PB OUT. Refer to Fig. 4. RF chroma signal LPF 18 fcⱌ2.2MHz ( AMP 20 1.1MHz BPF PB EQ LIMAMP 2.2MHz BPF ×2 ) 4.3MHz BPF - A ×2 26 ( 31 24 ( ) LIMAMP 27 PB SYNC GATE 4.3MHz BPF - B PB BELL PBOUT ( ) 6 AMP 2 ) 8 TRAP ( AMP 5 ) 11 ( 10 ) BA7207AS (BA7207AK) Fig. 4 (3) Sync gate timing circuit REC and PB SYNC gate operation is as follows. The gate closes closes in synchronous with the SYNC IN input pulse during the synchronous signal pulse (SYNC) horizontal scan interval (64µs period). During vertical retrace (32µS period), the input pulse period becomes shorter than the horizontal scan interval. This is detected by the builtin vertical synchronous detector circuit which closes the gate. Refer to Fig. 5. Horizontal scan interval Vertical retrace interval 64µs 32µs 4µs SYNCIN ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, REC / PBOUT ,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, Fig. 5 12 ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, Video ICs BA7207AS / BA7207AK •Application examples BA7207AS (SDIP32) PAL REC C. REC C OUT VCC SCM / PAL 100 0.1µ ∆ 0.01 27p 0.01 REC / PB 0.1 0.1 47 32 31 30 0.01 29 28 27 26 25 24 LPF ∆ + 0.01 0.1 47 23 PBIN B/W 0.01 22 21 20 19 18 17 MODE CONTOROL Vreg PAL SCM LIM R 2.2MHz BPF ×2 ×2 LIM P P 1.1MHz BPF EQ R 4.3MHz BPF - A R BELL PB SYNC GATE 4.3MHz BPF - B P P ÷4 REC SYNC GATE R R R P DET SYNC GATE TIMING GENERATOR VCO SCM PAL FREQUENCY ADJUSTER 3 4 5 VR2 ∗ ∗ 7.5k BELL fo ADJ 100p ∆ EQ fo ADJ VR1 ∗ ∗ 2KVR × 2 7.5k 6 7 8 9 VR3 10 11 0.01 0.01 10k 1k 12 13 14 15 16 100k 12 0.47 4700p 2 PBOUT LEVEL 1 0.01 ∆ 100p 33k ∗ SYNC IN PALPB C PB C OUT RECIN 560p ∗ To cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient ± 100ppm / °C. ∆: Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of ± 10% or Ic and a temperature coefficient of ± 30ppm / °C ( – 55°C to + 125°C) A (CG). Fig. 6 13 Video ICs BA7207AS / BA7207AK BA7207AK (QFP44) PAL REC C. REC C OUT. VCC SCM/PAL REC/PB PBIN B/W 100µ 0.01µ 0.01µ 0.1µ 0.1µ + 0.01µ 0.01µ 47µ ∆ 33 32 31 30 29 28 27 26 25 24 23 VCC 34 22 LIM 47µ 0.1µ MODE CONTROL 35 PAL SCM 21 0.01µ 27p 36 20 Vreg LPF 0.1µ 37 19 ∆ 2.2MHz BPF ×2 38 ×2 4.3MHz BPF—A 41 ∆ 18 R 17 R P 100p 40 1.1MHz BPF EQ R P 39 LIM P R P R BELL P 4.3MHz BPF—B PB SYNC GATE REC SYNC GATE ÷4 16 R P FREQUENCY ADJUSTER DET SYNC GATE TIMING GENERATOR VCO ∗ 2k VR 7.5k 13 44 12 VR2 ∗ ∗ 1 2 PBOUT LEVEL 7.5k BELL of ADJ EQ of ADJ ∗ 0.01µ SCM PAL 43 2k VR ∆ 14 42 VR1 100p 15 3 VR3 4 5 7 6 8 9 10k 1k 10 11 100k 0.01µ 12µ + 33k 4700p ∗ 0.01µ 0.47µ SYNC IN PALPB C. PB C OUT RECIN 580p ∗ To cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient ± 100ppm / °C. ∆: Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of ± 10% or Ic and a temperature coefficient of ± 30ppm / °C ( – 55°C to + 125°C) A (CG). Fig. 7 •Control pin logic Pin REC / PB setting switch RECH (19pin / 21pin) Low High (Open) PB REC Output select switch CTL (21pin / 23pin) PAL SECAM Chroma killer switch BWL (17pin / 18pin) Chroma killer NORMAL (BA7207AS / BA7207AK) 14 Video ICs Set to PB mode and input a 25mVP-P, 1.0715MHz sine wave to PBIN. Adjust the variable resistor connected between FADJ1 and GND to maximize the REC OUT output. This adjustment also adjusts the 1.1MHz and 2.2MHz band-pass filters. The value of the variable resistor must be at least 2kΩ. If it is less than this, adjustment may not be possible. (2) Bell filter fo adjustment Set to REC mode and input a 170mV P-P, 4.286MHz sine wave to RECIN. Adjust the variable resistor connected between FADJ2 and GND to maximize the AMP OUT output. This adjustment also adjusts the 4.3MHz and 4.3MHz A and B band-pass filters. The value of the variable resistor must be at least 2kΩ. If it is less than this, adjustment may not be possible. (3) Test pins The MUL, DIV, LAO and 4XO pins are test terminals. By connecting these pins to GND via a 3.6kΩ resistor, it is possible to monitor there waveforms. When unused, connect these pins to VCC to prevent interference. (4) REC / PB input levels The frequency characteristics of the built-in filters can change. For this reason use the following input signal levels: RECIN: 540mVP-P + / – 6dB (cyan level) PBIN: 75mVP-P + / – 6dB (cyan level) (6) PBIN input If there is a chroma component imposed on the FM brightness signal, use a low-pass filter (with an fc of about 2.2MHz) to remove the FM brightness signal component, and ensure that only the chroma component is input to PBIN. (7) RECIN input In the case of composite video input, connect a 100pF capacitor to ensure that only the chroma component is input to RECIN. (8) Sync-gate phase adjustment Perform fine adjustment of the sync-gate phase by applying a voltage to the SGADJ terminal, or using a resistor divider connected between VCC and GND. The adjustment sensitivity is shown in Fig. 6. SGADJ pin voltage when open: VSGADJ = 2.5V Input impedance Z = 125kΩ GATE PHASE ADJUSTMENT: TDR (µS) notes •(1)Operation Equalizer fo adjustment BA7207AS / BA7207AK + 3.2 0 0.32µS / 0.1V – 3.2 1.5 2.5 3.5 SGADJ PIN APPLY VOLTAGE: VSGADJ (V) (5) Capacitor connected to VREG Use a ceramic with a static capacitance of 0.1µF. The filter may not operate correctly with other capacitance values. Fig. 8 Sync-gate phase 15 Video ICs BA7207AS / BA7207AK •Electrical characteristic curves 1.1 1.0 0.9 7.5 8.0 8.5 9.0 5.0 4.5 4.0 3.5 9.5 FADJ1 RESISTANCE VALUE: RADJ1 (kΩ) 8.5 9.0 fo 1.05 40 60 80 4.20 0 100 100 18PIN PB IN LEVEL: VIPB (mVP-P) Fig. 12 PB EQ fO frequency variation characteristics – 20 – 40 – 50 – 60 – 70 – 80 – 90 – 110 0 Fundamental frequency 2MHz component component 1.0 2.0 3MHz component 3.0 FREQUENCY: f (MHz) Fig. 13 REC OUT spurious characteristics 300 Fundamental frequency component 400 500 5.0 PB IN f = 1.0715MHz V = 25mVP-P – 30 8MHz component – 40 6MHz component – 50 – 60 1MHz component 3MHz component – 70 – 80 5MHz component 7MHz component – 90 – 100 4MHz component 4.0 200 Fig. 11 REC / BELL fO frequency variation – 10 – 30 – 100 20 fo 1PIN REC IN LEVEL: VIREC (mVP-P) PB OUT LEVEL: VOPB (dBm) 1.07 0 4.25 9.5 RECIN f = 4.286MHz V = 170mVP-P – 20 REC OUT LEVEL: VOREC (dBm) 28PIN PB EQ FREQUENCY: fo (MHz) 8.0 – 10 Conditions VCC = 5.0V fo = 1.0715MHz V = 25mVP-P 1.06 4.30 Fig. 10 REC / PB BELL fO frequency adjustment range 1.09 1.08 4.35 4.15 7.5 Conditions VCC = 5.0V fo = 4.286MHz V = 170mVP-P FADJ2 RESISTANCE VALUE: RADJ2 (kΩ) Fig. 9 REC / PB EQ fO frequency adjustment range 16 6PIN REC BELL FREQUENCY: fo (MHz) 1.2 1.04 4.40 5.5 REC / PB BELL FREQUENCY: fo (MHz) REC / PB EQ FREQUENCY: fo (MHz) 1.3 – 110 0 2MHz component 1 2 3 4 5 6 7 8 9 FREQUENCY: f (MHz) Fig. 14 PB OUT spurious characteristics 10 Video ICs BA7207AS / BA7207AK •External dimensions (Units: mm) BA7207AS BA7207AK 28.0 ± 0.3 14.0 ± 0.3 10.0 ± 0.2 33 23 10.16 22 34 44 12 0.3 ± 0.1 1.778 0.5 ± 0.1 SDIP32 0° ~ 15° 2.15 ± 0.1 1 0.8 11 0.35 ± 0.1 1.2 14.0 ± 0.3 16 0.05 0.51Min. 3.2 ± 0.2 4.7 ± 0.3 1 10.0 ± 0.2 17 8.4 ± 0.3 32 0.15 ± 0.1 0.15 QFP44 17