CXA1203M/N
8mm VCR PAL JOG
Description
The CXA1203M/N compensates the color alignment
in variable speed mode for PAL-system 8mm VCRs.
This IC is also available for the SECAM system with
the built-in SECAM detector and BELL and C-BELL
filters.
Features
• Color alignment compensation which does not
require 1H delay line
• No AFC (fH) adjustment necessary
• Built-in SECAM detector
• Built-in BELL and C-BELL filters
• Available for the PAL-M system
CXA1203M
24 pin SOP (Plastic)
CXA1203N
24 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
7.0
• Supply voltage
VCC
• Operating temperature Topr –20 to +75
• Storage temperature
Tstg –55 to +150
• Allowable power dissipation
PD CXA1203M
567
Functions
V-Invert circuit, TH/DL APC, 2fsc PLL, SQ DET,
EX burst circuit, AFC (fH), Timing generator,
SECAM detector, BELL filter, C-BELL filter
CXA1203N
536
V
°C
°C
mW
mW
Recommended Operating Conditions
Supply voltage
4.5 to 5.5
(5.0V typ.)
Structure
Silicon monolithic IC
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01Z33-PS
VCO
1/2FHM
XSHP
DL GAIN
ADJ
AFC
ID
LPF3
12
11
10
9
8
7
6
5
4
1/2FHMP
SECAM
ACK
PB C IN
VCC
TEST
RST
Normal
75% C
SECAM
DLDP
1/2
FHT
LPF2
S/H
SECAM
JUMP
Jump
P. D.
Secam
P. D.
BF
Gen
TH/DL
(1/2FHTA)
BF Xch
DL MAIN
SW
CW
TH
13
SECAM
LPF
EDGE
TRIG
75%
MASK1
PAL-M
EDGE
TRIG
14
SW
PAL
SWD
1/2FHM
15
BF
MASK 75 – 1
75%
MASK2
MASK
75 – 2
V-I2
16
LPF2
TH/DL
PAL-M
17
SQ ID
D 75%
→ 150%
LIM2
CONV1
Dummy
SWD SECAM
1/2FHT DETPLS
D
fsc IN
18
DL APC
LPF
AFC
LPF
3
Clamp
CLP PLS
U ERRI
D ERRI
SQ
P.D.
TH/DL
(1/2FHTA)
AMP
19
C OUT
HD
2
Peak
Hold
BF
HD
CLG PLS
LPF
S/H
PAL-M
LPF1
V-I1
PB (PAL)
PB (Se)
REC (Se)
×2
BELL
C-BELL
20
IREF
C Sync
1
H ID
MODE
21
SECAM
IN
–90°
LIM
SA CONT
XFHM
1/2FHM
1/2
REC
PB
LIM1
TH/DL
BELL IN
22
VREG
GND
–2–
BELL IN
CONT
SECAM IN
FM
LPF1
DEMOD
Normal
1/2FHM
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
D
24
PB
XPB
23
BELL
FILTER
MODE
φADJ
Block Diagram and Pin Configuration
CXA1203M/N
CXA1203M/N
Pin Description
Pin
No.
1
Symbol
VCC
Voltage
DC
AC
5.0V
(typ.)
—
Equivalent circuit
Description
—
Supply voltage pin
3.0V
VCC
Input pin of PAL playback
chrominance signal.
The chroma ACK operates to
cut off the output at Pin 15
when the DC bias voltage at
Pin 2 is 0.7V or less.
60k
2
350mVp-p
150mVp-p
(burst)
PB C
IN
PR
47k
2
15.2p
20k
VCC
3
SECAM
ACK
3.8V
(H)
0V
(L)
10k
(Sub)
—
8k
PR
20k
3
SECAM detector output pin.
H → SECAM
L → PAL
The SECAM or PAL mode is
fixed by applying an external
DC voltage.
SECAM: 3.0 to 5.0V
PAL: 0 to 1.0V
VCC
(×2)
4
1/2
FHMP
—
Output pin of the pulse
obtained by dividing down the
AFC (fH-PLL) output by 2.
PR
3.2V
4
(×2)
1.7V
4k/2
28k
VCC
3.5V
5
75% C
—
PR
(×3)
(Sub)
5
1.0V
8k
(×3)
20k/3
–3–
Connecting pin of the
charging and discharging
capacity to produce the
triangular wave chronized
with the C Sync signal.
All timing pulses used in the
IC are produced from this
triangular wave.
CXA1203M/N
Pin
No.
Symbol
Voltage
DC
Equivalent circuit
AC
Description
VCC
6
DLDP
2.8V
(H)
1.4V
(L)
Input pin to switch the polarity
of the 1/2FHT pulse for the
SECAM detector.
Output pin of the AFC ID
signal in TEST mode∗1.
PR
6
1.4Vp-p
8k
100k
7
SECAM
JUMP
2.8V
(H)
1.4V
(L)
VCC
(Sub)
1.4Vp-p
PR
7
20k
20k
10k
10k
4k
VCC
8
SECAM
LPF
PR
2.5V
—
100k
8
(Sub)
10k
10k
VCC
9
1k
20k
2.0V
—
Connecting pin of the time
constant of the LPF for the
SECAM detector.
2k
4k
AFC
LPF
Output pin to switch the
polarity of the 1/2FHT pulse.
Mode selection∗1 is possible
by applying an external DC
voltage.
PAL-M: 0 to 0.5V
Normal: OPEN
RESET: 3.6 to 4.1V
TEST: 4.3 to 5.0V
PR
9
6.5k
(Sub)
(Sub)
(×4)
(×2)
4k/2
–4–
1k
Connecting pin of the time
constant of the LPF for the
AFC (fH-PLL).
CXA1203M/N
Pin
No.
Symbol
Voltage
DC
Equivalent circuit
AC
VCC
HD
20k
(×2)
PR
4.0V
10
Description
—
Output pin of the HD pulse
produced in the AFC (fH-PLL).
10
0.4V
(×2)
1k
(Sub)
20k
11
46k
20k
Input pin of the composite
sync signal.
The internal threshold voltage
is 2.0V and the polarity is
active HIGH.
2.0V
C Sync
PR
11
12
GND
—
—
GND pin
—
VCC
(×32)
13
VREG
4.2V
—
13
23p
8k
Connected to
about 30
elements
Output pin of the regulated
voltage source in the IC
(4.2V).
40k
VCC
(Sub)
14
IREF
2.1V
—
PR
14
(×2)
IREF
10k
–5–
4k
Connecting pin of the
standard resistance to
produce the reference
current source in the IC.
CXA1203M/N
Pin
No.
Symbol
Voltage
DC
Equivalent circuit
AC
Description
VCC
15
C OUT
In PAL
mode
2.1V 350mVp-p
150mVp-p
(burst)
PR
Output pin of the playback
PAL signal (TH, DL and EX
burst)∗2, SECAM signal and
PAL-M signal.
(×4)
15
2.5k
VCC
16
DL APC
LPF
Connecting pin of the time
constant of the LPF for the
TH/DL APC loop.
The TH/DL lock phase can
be varied by applying an
external DC current.
PR
2.4V
16
—
PR
17
SQ ID
4.0V
(H)
0V
(L)
8k
VCC
—
PR
(Sub)
17
20k
10k
Output pin of the SQ detector.
The TH or DL output signal at
Pin 15 can be selected by
applying an external DC
voltage.
DL: 0 to 2.0V
TH: 3.0 to 5.0V
VCC
PR 10.4p
18
fsc IN
—
350mVp-p
Input pin of the fsc.
(chrominance subcarrier)
18
30k
4k
–6–
CXA1203M/N
Pin
No.
Symbol
Voltage
DC
Equivalent circuit
AC
Description
VCC
15k
PR
19
DL GAIN
ADJ
19
5.0V
(typ.)
13.4k
13.4k
2670
Control pin of the DL signal
gain.
The gain can be varied by
applying an external DC
voltage. The internally fixed
gain is obtained at 5.0V.
Output pin of the S/H circuit
in TEST mode.
VCC
PR
20
SECAM
IN
—
150mVp-p
(burst)
15.2p
40k
20
10k
Input pin of the SECAM
detector in REC mode.
20k
8k
VCC
(Sub)
21
22
MODE
BELL
IN
—
PR
—
21
—
83mVp-p
(SECAM
burst)
VCC
Mode selection∗1 is possible
by applying an external DC
voltage.
REC: 0 to 1.3V
PB: 1.7 to 2.8V
JOG: 3.2 to 5.0V
15.2p 4k
PR
15.2p
13.5k
22
15k
117mVp-p
(PAL
burst)
100k
38k
–7–
Input pin of the SECAM
signal.
Input pin of the SECAM
detector in playback mode.
CXA1203M/N
Pin
No.
Symbol
Voltage
DC
Equivalent circuit
AC
Description
VCC
30k
PR
(Sub)
23
23
φADJ
5.0V
(typ.)
—
38k 38k
(×2)
10k
EX burst phase adjustment
pin.
The phase can be varied by
applying an external DC
voltage. The internally fixed
phase is obtained at 5.0V.
VCO output pin in TEST
mode.
2k
200
24
BELL
FILTER
3.0V
(×2)
—
24
4k
70
(×5)
1k
Connecting pin of the time
constant of the BELL and
C-BELL filters.
(×3)
Notes)
∗1 Refer to Mode Description.
∗2 PAL playback signal (TH, DL and EX burst)
The DL signal is symmetrical to the TH signal (PAL playback signal) about the B-Y axis.
The burst signal produced from the fsc (chrominance subcarrier) in the IC is known as the EX burst.
The EX burst is inserted into the playback chrominance signal in JOG mode.
–8–
CXA1203M/N
Mode Description
Mode
Control pin
PAL
—
Voltage
0 to 1.0V
Pin 3
High impedance
SECAM
3.0 to 5.0V
PAL-M
0 to 0.5V
Fixed PAL mode
Automatic selection of PAL or SECAM
Fixed SECAM mode
The PAL-M signal is output from Pin 15 by inputting
an NTSC signal to Pin 2.
(For details, see "Notes on Use".)
3.6 to 4.1V
The logic block (AFC ID, 150% masking and 1/2
division) in the AFC (fH-PLL) is turned off.
TEST
4.3 to 5.0V
The operation of the AFC ID, VCO and S/H blocks in
the AFC (fH-PLL) is checked.
DL
0 to 2.0V
RESET
—
Pin 7
Description
Pin 17
High impedance
TH
3.0 to 5.0V
REC
0 to 1.3V
PB
JOG
Pin 21
The DL signal is output from Pin 15.
The TH or DL signal selected by the SQ detector
decision is output.
The TH signal is output from Pin 15.
REC mode
1.7 to 2.8V
Playback mode
3.2 to 5.0V
The EX burst is inserted into the original burst signal
portion in PAL playback mode.
–9–
– 10 –
15
↓
↓
↓
↓
↓
θTH-EXB
14
O
↓
TH-EX burst phase
difference
TH/EXB level ratio
13
O
↓
↓
17
θTH-DL
TH/DL phase
difference
12
O
∆θEXB
DA-G
TH/DL Amp gain
ratio
11
↓
↓
EX burst phase
difference
THA-G
TH Amp gain
10
↓
↓
16
CBF-G
C-BELL FILTER
gain
9
↓
↓
↓
↓
↓
BF-G
BELL FILTER gain
8
O
↓
I-CT (SP)
Input SW crosstalk
(SECAM PB)
7
↓
↓
↓
↓
↓
↓
1.0V
↓
↓
↓
3.0V
↓
↓
5.0V
∆VEXB
I-CT (SR)
Input SW crosstalk
(SECAM REC)
6
↓
↓
5.5V
EX burst level ratio
V (IREF)
V (IREF)
5
↓
↓
4.5V
↓
VREG (5.5)
VREG (5.5V)
4
1.0V
↓
↓
3.0V
↓
↓
VREG (4.5)
VREG (4.5V)
3
V3
↓
∆VTH-EXB
VREG (5.0)
VREG (5.0V)
2
↓
ICC (SR)
Circuit current
(SECAM REC)
V2
V7
1.7V
1.3V
1.7V
1.3V
↓
↓
↓
1.7V
1.3V
1.7V
V21
↓
2.0V
↓
↓
↓
3.2V
↓
↓
3.0V 2.8V
V17
↓
G
↓
H
G
↓
H
↓
↓
↓
G
F
↓
↓
E
A
A
Test
point
PAL JOG
PAL PB
SECAM
PB
C OUT
Phase
test
Output
level
test
C OUT phase
test
C OUT output
level test
(4.43MHz)
C OUT output
level test
40
90
–1.0
1.1
50
–0.6
–2.5
–3.0
48
96
0
2.6
90
0.4
–0.3
0
14.0
–38.0
2.12
4.24
4.24
4.24
27.0
SECAM
REC
11.0
2.05
4.10
4.10
4.10
20.0
25.5
Typ.
–53.0
C OUT output
level test
DC voltage test
DC current test
17.5
Min.
SECAM
PB
SECAM
REC
PAL PB
SECAM
REC
PAL PB
Mode
Output waveform and test
content
56
102
1.0
4.1
120
1.4
2.0
3.0
16.0
–45.0
–35.0
2.20
4.40
4.40
4.40
34.0
32.5
Max.
deg
deg
dB
dB
deg
dB
dB
dB
dB
dB
dB
V
V
V
V
mA
mA
Unit
(Ta = 25°C, VCC = 5.0V, See Fig. 1. Electrical Characteristics Test Circuit.)
Bias condition
5.0V 2.5V 1.0V
SW1 SW2 SW3 SW4 SW5 VCC
Switch condition
ON : O, OFF: blank
↓
ICC (PP)
Symbol
Circuit current
(PAL PB)
Item
1
No.
Electrical Characteristics
CXA1203M/N
O
O
O
∆θEXB
(PAL M)
PAL-M DL-EX burst θTH-EXB
phase difference
(PAL M)
SQ (+)
SQ (–)
MSW-CT
(TH)
PAL-M EX burst
phase difference
SQ DET +V
detection
SQ DET –V
detection
Main SW crosstalk
(TH)
AFC HD timing
AFC HD width
AFC lock range (1)
20
21
22
23
24
25
26
27
28
V17
V21
↓
↓
↓
↓
↓
– 11 –
EXB-W
1/2FH-D
1/2FH-DU
TIMING EX burst
width
TIMING 1/2FHMP
delay
TIMING 1/2FHMP
duty
30
31
32
O
EXB-D
TIMING EX burst
delay
29
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
1.7V
↓
3.2V
↓
↓
C
↓
G
↓
↓
AFC-LR
(2)
↓
AFC lock range (2)
↓
↓
AFC-LR
(1)
↓
↓
↓
↓
↓
↓
HD-D
HD-W
G
↓
I
↓
↓
↓
D
3.0V 1.7V
↓
↓
↓
↓
↓
3.8V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
G
↓
O
V7
↓
O
V3
Test
point
↓
O
O
∆VEXB
(PAL M)
PAL-M EX burst
level ratio
19
V2
Bias condition
5.0V 2.5V 1.0V 5.0V 0V 2.8V
SW1 SW2 SW3 SW4 SW5 VCC
O
Symbol
PAL-M DL APC
DL-APC
loop characteristics (PAL M)
Item
18
No.
Switch condition
ON : O, OFF: blank
PAL PB
PAL JOG
PAL PB
PAL
RESET
PAL-M
PB
Mode
Time test
Frequency test
at Pin 10
Time test at
Pin 10
C OUT output
level test
DC voltage test
at Pin 17
C OUT phase
test
C OUT output
level test
C OUT phase
test
Output waveform and test
content
44
32.0
3.9
4.5
–55
–55
4.4
–3.0
–35
–122
–20
–104
–1.5
–100
Min.
50
36.0
4.4
5.2
5.3
–1.2
–49
–10
–96
0
–90
Typ.
56
40.0
5.1
5.8
55
55
6.2
0.3
–44
–59
–98
0
–88
1.5
–80
Max.
%
µs
µs
µs
Hz
Hz
µs
µs
dB
deg
deg
deg
deg
dB
deg
Unit
CXA1203M/N
SQ (PB)
SECAM DETECTOR
DEMOD (PB)
ACK check
33
34
ACK
Symbol
Item
No.
O
O
V2
↓
0.5V 1.0V
V3
V7
V17
5.0V
Bias condition
5.0V 2.5V
SW1 SW2 SW3 SW4 SW5 VCC
Switch condition
ON : O, OFF: blank
↓
2.8V
V21
G
B
Test
point
PAL PB
PB
Mode
C OUT output
level test
DC voltage test
at Pin 3
Output waveform and test
content
3.60
Min.
–58
3.80
Typ.
–49
4.00
Max.
dB
V
Unit
CXA1203M/N
– 12 –
– 13 –
4.286MHz CW
83mVp-p
C-BELL FILTER
gain
TH Amp gain
TH/DL Amp gain
ratio
TH/DL phase
difference
10
11
12
13
↓
↓
CW delayed by
135° from Vfsc
150mVp-p
↓
↓
↓
↓
↓
CW delayed by
135° from Vfsc
350mVp-p
4.286MHz CW
32mVp-p
BELL FILTER gain
9
4.286MHz CW
350mVp-p
Input SW crosstalk
(SECAM PB)
8
64µs
↓
↓
4.43MHz CW
350mVp-p
{
{
{
{
Output level of T11
C OUT (4.43MHz)
C OUT (4.43MHz)
VPAL
}
}
C OUT (4.286MHz component)
VSE
C OUT (4.286MHz component)
VPAL
C OUT (4.286MHz component)
VSE
θDL – θTH
20 log
20 log
20 log
20 log
{
Input SW crosstalk
(SECAM REC)
7
20 log
Test the DC voltage at Pin 14.
V (IREF)
6
5µs
Test the DC voltage at Pin 13.
VREG (5.5V)
5
4.286MHz CW
350mVp-p
Test the DC voltage at Pin 13.
VREG (4.5V)
4
15.625kHz,
4.0Vo-p
Test the DC voltage at Pin 13.
Test content
VREG (5.0V)
Vfsc
3
Vsync
Circuit current
(SECAM REC)
VSE
2
VPAL
Input signal
Circuit current
(PAL PB)
Item
1
No.
Test Methods of Electrical Characteristics
}
}
}
CXA1203M/N
↓
↓
↓
↓
↓
EX burst phase
difference
TH-EX burst phase
difference
PAL-M DL APC
loop characteristics
PAL-M EX burst
level ratio
PAL-M EX burst
phase difference
PAL-M DL-EX burst
phase difference
16
17
18
19
20
21
CW delayed by
90° from Vfsc
150mVp-p
↓
EX burst level ratio
– 14 –
63.6µs
5µs
15.734kHz,
4.0Vo-p
64µs
5µs
15.625kHz,
4.0Vo-p
15
Vsync
TH/EXB level ratio
VSE
14
VPAL
Input signal
Item
No.
↓
↓
↓
3.58MHz CW
350mVp-p
↓
↓
↓
4.43MHz CW
350mVp-p
Vfsc
20 log
5µs
5µs
{
EB1
EB1
5µs
EB2
EB2
EB1
Vfsc
θ2
θ1
– 7.4dB
130mVp-p
EB1
EB2
EB1
Vfsc
θ2
θ1
Phase difference between the center
θ1 + θ2
– T18
of EX burst and DL signal.
2
∆θ(EB) = |θ1 – θ2|
∆V(EB) = 20 log {V(EB1)/V(EB2)}
YC MIX
C Sync
}
Phase difference between the center
of EX burst and TH signal.
Test θ (DL) on the basis of Vfsc.
θ1 + θ2
– θTH
2
∆θ (EB) = θ2 – θ1
64µs
EB2
T11 (p-p)
(EB1 + EB2)/2
∆V (EB) = 20 log {V(EB1)/V(EB2)}
C Sync
YC MIX
EB2
130mVp-p
EB1
EB2
EB1
Test content
CXA1203M/N
tw
↓
↓
↓
Main SW crosstalk
(TH)
AFC HD timing
23
24
25
– 15 –
↓ 19.0kHz
15.625kHz,
4.0Vo-p
↓
AFC lock range (1)
AFC lock range (2)
TIMING EX burst
delay
TIMING EX burst
width
27
28
29
30
11.0kHz
5.0µs
AFC HD width
26
4.0V
td
↓
Signal with the
phase delayed
from Vfsc
150mVp-p
↓
4.43MHz CW
350mVp-p
↓
↓
Test content
(
tw
td
)
td
C OUT
C Sync
Test the time at C OUT.
1
Input frequency –
T
T
Test the frequency at Pin 10.
HD 2.0V
C Sync
Test the time at Pin 10.
Test by TH signal timing.
td
tw
0V
3.5V
3.5V
tw
0V
Test the phase of VPAL (on the basis of Vfsc) when DC
is changed from H to L (0V) at Pin 17.
Test the phase of VPAL (on the basis of Vfsc) when DC
is changed from L to H (4.0V) at Pin 17.
SQ DET –V
detection
4.43MHz CW
350mVp-p
15.625kHz,
4.0Vo-p
Vfsc
22
Vsync
Signal with the
phase delayed
from Vfsc
150mVp-p
VSE
SQ DET +V
detection
VPAL
Input signal
Item
No.
CXA1203M/N
ACK check
33
34
4.43MHz CW
350mVp-p
SECAM DETECTOR
DEMOD (PB)
32
↓
↓
↓
TIMING 1/2FHMP
duty
SECAM signal
(Burst level
83mVp-p)
15.625kHz,
4.0Vo-p
Vsync
TIMING 1/2FHMP
delay
VSE
31
VPAL
Input signal
Item
No.
Vfsc
1/2FHMP
C Sync
t1
td
Test the time at Pin 4.
C OUT (4.43MHz) → V,
20 log (V/350mV)
Test the DC voltage at Pin 3.
t1
(t1 + t2)
td
Test content
t2
CXA1203M/N
– 16 –
CXA1203M/N
Fig. 1. Electrical Characteristics Test Circuit
5V
100k
VSE
5V
4.43MHz
BPF
SW5
H
0.1µ
1.2k
SW4
G
1k
V17
0.01µ
33p
0.1µ
Vfsc
5V
SW3
5V
820
10µ
1500p
V21
39
20k
20k
50k
2k
50k
1µ
F
23
22
19
18
17
16
LIM
BELL
C-BELL
15
14
REC
AMP
CONV1
TH/DL
(1/2FHTA)
LIM2
13
TH
REC (Se)
PB (Se)
SWD
1/2FHM
TH/DL
PB (PAL)
PAL-M
DL MAIN
SW
CW
SW
PAL
×2
–90°
LIM1
VREG
IREF
C OUT
DL APC
LPF
SQ ID
fsc IN
DL GAIN
ADJ
SECAM
IN
20
Dummy
PB
PB
XPB
MODE
21
E
V-I2
BF Xch
LPF2
TH/DL
(1/2FHTA)
PAL-M
V-I1
LPF1
PAL-M
BF
TH/DL
1/2FHM
XSHP
D
S/H
AFC
ID
CLG PLS
BELL IN
CONT
SECAM IN
FM
LPF1
DEMOD
Normal
Peak
Hold
Secam
P. D.
Clamp
6
75% C
1/2FHMP
5
EDGE
TRIG
1/2
FHT
7
DLDP
4
SECAM
ACK
PB C IN
VCC
BF
Gen
75%
MASK1
TEST
RST
Normal
8
9
3.3µ
110p
10k
0.047µ
10k
SECAM
LPF2
S/H
Jump
P. D.
3
EDGE
TRIG
SWD SECAM
1/2FHT DETPLS
CLP PLS
H ID
2
75%
MASK2
MASK
75 – 2
LPF
1/2FHM
1
D 75%
→ 150%
SW1
10
11
12
C Sync
SA CONT
MASK 75 – 1
D
HD
VCO
U ERRI
D ERRI
AFC
LPF
1/2
HD
SECAM
LPF
XFHM
BF
LPF3
SECAM
JUMP
1/2FHM
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
SQ
P.D.
50k
5k
4.7k
1000p
4.7µ
SW2
A
0.01µ
V2
V3
Vsync
V7
VCC
VPAL
B
C
D
– 17 –
GND
24
MODE
BELL IN
φADJ
BELL
FILTER
100k
CXA1203M/N
Description of Functions
1. Gain Adjustment Amplifier (DL Signal)
This amplifier adjusts the gain of the DL signal in PAL or PAL-M mode. The amplifier gain varies according
to the DC voltage applied to Pin 19. When 5V is applied to Pin 19, the internally fixed gain is obtained and
the levels of the TH signal and the DL signal (4.43MHz component in PAL mode, 3.58MHz component in
PAL-M mode) become the same.
2. fsc –90° PLL, × 2 and EX Burst Block
cos ωt
fsc
18
cos ωt
cos (ωt – 90°)
LIM
–90°
V→I
2fsc
cos (2ωt – 90°)
LPF1
φADJ 23
cos (ωt – 180°)
EX Burst
√2 cos (ωt – 45°)
√2 cos (ωt – 135°)
cos ωt
1/2fH
Fig. 2
The fsc –90° PLL consists of the –90° phase shifter, multiplier, LPF (low pass filter) 1 and V/I converter.
A signal delayed by 90° to the fsc is obtained in this PLL. By changing the DC voltage at Pin 23, the
amount of phase shift is varied. allowing adjustment of the phase of the EX burst and the duty (DC offset)
of the 2fsc. By applying 5V at Pin 23, the internally fixed phase shift is obtained. The 2fsc is produced
from the multiplier output (×2 output).
The EX burst is produced by adding the fsc (or inverted fsc) to the fsc with 90° delay produced in the –90°
PLL.
The fsc and the inverted fsc are switched in a period of 1/2fH, so the phase of the EX burst changes every
1H.
– 18 –
CXA1203M/N
3. SQ DET (Sequence Detector)
Chrominance signal
SQ
P.D.
fsc
17 SQ
LPF3
1/2fH
Burst Flag Gate
Fig. 3
The SQ DET detects the color alignment of the chrominance signal. The SQ PD is the phase detector which
operates for a burst period only. This detects the color alignment by comparing the phase of the fsc signal
inverted every 1H with the phase of the burst of the chrominance signal.
Output at Pin 17
4V
0V
–180°
–135°
–90°
–48°
0
+48°
+90°
–112°
+135°
+180°
+112°
Phase of the burst signal
(on the bias of fsc and fsc)
Fig. 4
The above figure shows the relation between the phase of the burst signal, the phase of the fsc (fsc) and
the output at Pin 17 (SQ). As shown in the figure, the hysteresis angle is about 64°. If the relation is as
shown in the figure below, the detector judges it as the correct sequence and set the output at Pin 17 to
HIGH.
fsc
Burst
+135°
B-Y
B-Y
–135°
Burst
fsc
Fig. 5
Therefore, the center phase of the burst signal (about the B-Y axis) should be –90° to the fsc.
– 19 –
CXA1203M/N
4. V-Invert (V Axis Inversion Circuit)
For color alignment, the DL signal which is produced by inverting the chrominance signal (TH signal) about
the B-Y axis is necessary.
The V-Invert block produces the DL signal from the TH signal. Fig. 6 shows the principle of the V-Invert
block.
TH: cos (ωt ± θ)
To
Y/C MIX BLOCK
BPF
Playback chrominance
signal
cos (ωt ± θ)
cos 2ωt
θ
θ
DL: cos (ωt ± θ)
cos (3ωt ± θ)
×2
Rejected by the BPF.
fsc (cos ωt)
Fig. 6
Define the B-Y axis of the playback chrominance signal as cos ωt and input the playback chrominance
signal and the 2fsc (cos 2ωt) to the multiplier. By means of the frequency conversion of the 2fsc, the input
chrominance signal is inverted about the B-Y axis. The three fold frequency component (cos 3ωt) is also
output, but this component is rejected by the BPF in a later stage.
Fig. 7 shows the actual V-Invert block.
TH/DL
BF Xch
Dummy
Playback chrominance
signal
TH
DL
CONV1
15
Main
SW
PAL
φ
V-I
LPF2
C OUT
SWD
1/2fH
PAL-M
2fsc
BF Gate
fsc
EX Burst
Fig. 7
The V-Invert circuit constructs the TH/DL APC loop that keep the phase difference between the burst of the
TH signal and the burst of the DL signal to be 90°. This circuit detects the phase of the bursts of the TH and
DL signals and varies the delay time of the phase shifter φ with reference to the error current of APC loop.
In PAL-M mode, the APC is applied to the fsc and the DL signal. Therefore, the input burst signal has a
phase of 90° to the fsc. The CONV1 is a multiplier to obtain the DL signal.
The Dummy supplies the same gain loss and the same phase delay as produced in CONV1 to the TH
signal so that there is no gain and phase difference between the TH signal and the DL signal.
The main SW outputs the TH or DL signal according to the TH/DL select signal (output at Pin 17). When a
BF Xch pulse is supplied (in JOG mode only), the EX burst is output.
– 20 –
CXA1203M/N
5. fH PLL
AFC
ID
HD 10
11 C Sync
HD
VCO
S/H
XSHP
1/2fH
1/2
LPF
SWD 1/2fH
Fig. 8
The AFC ID compares the C Sync frequency with the VCO frequency. When a frequency difference is
present, the AFC ID outputs an up or down error and roughly compensates the VCO frequency. In this
case, the AFC ID detects if the frequency difference continues for a period of 15H × 6 (5760µs), and AFC
ID error is available only when the frequency difference continues for that period.
The AFC ID also detects the existence of C Sync. When the C Sync is missing in various speed mode, the
AFC ID cuts off its output and maintains the state immediately before the output cutout.
The phase lock of the C Sync and VCO frequencies is carried out in the PLL loop composed of the S/H and
LPF circuits.
6. BELL and C-BELL Filters
The Bell Filter is applied to the SECAM color TV signal to suppress the level near the chrominance subcarrier
(FOR, FOB). In REC mode, the CXA1203 employs the BELL filter (having the inverted characteristics from the
Bell Filter) to obtain the chrominance subcarrier of the same amplitude at every hue. The output signal from
the BELL filter is sent to the record signal processing block of chrominance signal in the CXA1200.
In playback mode, the chrominance signal processed in the CXA1200 is input to the C-BELL (having the
same characteristics as the Bell Filter) filter of the CXA1203 to equalize the input signal with the SECAM
color TV signal. The output from the C-BELL Filter is mixed with the Y signal in the CXA1200 and sent to
the CXA1201. The typical input level of the BELL Filter is 32mVp-p, and that of the C-BELL Filter is 83mVp-p.
7. SECAM Detector Circuit
The SECAM detector circuit employed in the CXA1203 converts the chrominance subcarrier frequency∗1 to
a voltage, and detects the color system by the voltage variation: PAL system if no voltage variation is
present, or SECAM system if the voltage varies every 1H. When the color alignment is carried out in
SECAM mode, the SECAM ACK output (Pin 3) is always set to HIGH by inputting the SECAM JUMP output
(Pin 7) to the DLDP (Pin 6).
∗1 PAL system:
color burst signal (4.43361875MHz)
SECAM system: line ID signal FOR: 4.40625MHz
FOB: 4.25000MHz
– 21 –
CXA1203M/N
Fig. 9. Application Circuit 1 (for PAL/SECAM mode)
5V
5V
20k
1k
0.01µ
100p
fsc IN
20k
BELL IN
1k
10p
SECAM IN
1k
20k
5V
5V
33k
5V
2.2k
0.01µ
PB
CHROMA
OUT
BPF
1µ
0.1µ
820
22k
23
22
0.01µ
20k
20
19
18
17
16
IREF
15
14
BELL
C-BELL
LIM
AMP
PB (Se)
DL MAIN
SW
CW
CONV1
SWD
1/2FHM
TH/DL
PB (PAL)
TH/DL
(1/2FHTA)
13
TH
Dummy
REC (Se)
REC
LIM2
PAL-M
SW
PAL
×2
–90°
LIM1
V-I2
BF Xch
LPF2
TH/DL
(1/2FHTA)
PAL-M
V-I1
LPF1
PAL-M
BF
TH/DL
1/2FHM
XSHP
D
VCO
S/H
Secam
P. D.
Clamp
5V
6
BF
Gen
SECAM
LPF2
S/H
1/2
FHT
7
DLDP
75% C
5
1/2FHMP
4
SECAM
ACK
3
PB C IN
75%
MASK1
EDGE
TRIG
TEST
RST
Normal
8
9
10k
0.01µ
EDGE
TRIG
10
11
C Sync
Peak
Hold
Jump
P. D.
2
75%
MASK2
MASK
75 – 2
SWD SECAM
1/2FHT DETPLS
CLP PLS
H ID
VCC
D 75%
→ 150%
HD
CLG PLS
BELL IN
CONT
SECAM IN
FM
LPF1
DEMOD
Normal
Vcc
AFC
ID
LPF
SA CONT
1/2FHM
1
MASK 75 – 1
D
AFC
LPF
1/2
U ERRI
D ERRI
HD
SECAM
LPF
XFHM
BF
LPF3
SECAM
JUMP
1/2FHM
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
SQ
P.D.
10µ
100k
C OUT
DL APC
LPF
SQ ID
fsc IN
DL GAIN
ADJ
SECAM
IN
100k
21
PB
PB
XPB
MODE
MODE
BELL IN
φADJ
BELL
FILTER
24
1.5k
100k
100k
1500p
39
1k
12
GND
33p
1k
1k
VREG
JOG
REC/PB
1.2k
5V
4.7k
10µ
110p
0.022µ
3.3µ
15k
1000p
4.7µ
10k
0.01µ
1k
390k
PB CHROMA IN
27k
C Sync
SECAM ACK
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXA1203M/N
Fig. 10. Application Circuit 2 (for PAL mode only)
5V
5V
20k
1k
0.01µ
100p
fsc IN
20k
1k
10p
1k
20k
5V
5V
33k
5V
2.2k
0.01µ
PB
CHROMA
OUT
1µ
20k
1k
1k
22k
100k
0.01µ
20k
21
20
19
18
17
16
IREF
15
14
LIM
BELL
C-BELL
REC
REC (Se)
AMP
PB (Se)
DL MAIN
SW
CW
CONV1
SWD
1/2FHM
TH/DL
PB (PAL)
TH/DL
(1/2FHTA)
13
TH
Dummy
PB
LIM2
PAL-M
SW
PAL
×2
–90°
LIM1
V-I2
BF Xch
LPF2
TH/DL
(1/2FHTA)
PAL-M
V-I1
LPF1
PAL-M
BF
TH/DL
1/2FHM
XSHP
D
CLG PLS
BELL IN
CONT
SECAM IN
FM
LPF1
DEMOD
Normal
SWD SECAM
1/2FHT DETPLS
CLP PLS
Peak
Hold
Secam
P. D.
Clamp
Jump
P. D.
H ID
7
DLDP
6
75% C
5
1/2FHMP
VCC
Vcc
4
SECAM
ACK
3
PB C IN
2
75%
MASK1
EDGE
TRIG
BF
Gen
SECAM
LPF2
S/H
1/2
FHT
TEST
RST
Normal
8
9
10k
0.01µ
EDGE
TRIG
LPF
1/2FHM
1
75%
MASK2
MASK
75 – 2
10
11
C Sync
SA CONT
S/H
D 75%
→ 150%
HD
VCO
AFC
ID
AFC
LPF
1/2
MASK 75 – 1
D
U ERRI
D ERRI
HD
SECAM
LPF
XFHM
BF
LPF3
SECAM
JUMP
1/2FHM
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
SQ
P.D.
10µ
100k
C OUT
DL APC
LPF
SQ ID
fsc IN
DL GAIN
ADJ
SECAM
IN
100k
12
GND
22
PB
XPB
MODE
MODE
BELL IN
φADJ
BELL
FILTER
23
1.5k
100k
1500p
24
1k
VREG
JOG
REC/PB
BPF
4.7k
10µ
1000p
110p
4.7µ
10k
0.01µ
C Sync
PB CHROMA IN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 23 –
CXA1203M/N
Notes on Use
1. Phase Adjustment in PAL Playback Mode
The phase of the EX burst signal can be adjusted with the phase of the input fsc (chrominance subcarrier).
The phase of the DL signal can be adjusted by applying a current to Pin 16.
Adjust the phase of the fsc so that the phase of the EX burst signal in JOG playback mode matches the
phase of the color burst signal in normal playback mode at the PB CHROMA output (Pin 15).
Then, adjust the current to be applied to Pin 16 so that the DL signal becomes symmetrical to the TH signal
about the B-Y axis.
2. PAL-M Mode
R-Y
R-Y
EX burst
B-Y
B-Y
TH and DL
signals
Input signal
fsc
fsc
Input
Output
Fig. 11
Input an NTSC signal to Pin 2, the fsc signal (3.58MHz) to Pin 18 and the C Sync signal (15.75MHz) to Pin 11.
Then the PAL-M playback signal is obtained at PB CHROMA output (Pin 15).
To adjust the phase, first input a burst signal with the same phase as the B-Y axis, and adjust the phase of
the fsc to be input so that the phase of the TH signal matches the center phase of the EX burst at Pin 15.
Then adjust the current to be applied to Pin 16 so that the phase of the DL signal matches the center phase
of the EX burst. In PAL-M mode, Pin 17 (SQ ID) should be fixed to "L".
3. PAL Only Mode
In PAL only mode, a part of the SECAM detector block is turned off by fixing Pin 22 (BELL IN) to "H". This
reduces the current consumption to 1.2mA. The connections for other pins are the same as shown in "Fig. 10
Application Circuit 2 (for PAL mode only)".
– 24 –
CXA1203M/N
Example of Representative Characteristics
VREG supply voltage characteristic
BELL Filter characteristic
4.25
16.0
14.0
12.0
10.0
Gain [dB]
VREG (Pin 13) [V]
4.24
4.23
8.0
6.0
4.0
4.22
2.0
4.21
4.50
4.75
5.00
5.25
0
3.786
5.50
4.286
Vcc (Pin 1) [V]
4.786
f – Frequency [MHz]
Vcc = 5.0V
SECAM/REC mode
Input level: 32mVp-p (BELL IN)
Output: C OUT (Pin 15)
C-BELL Filter characteristic
TH/DL/EX burst output level vs. Ambient temperature
160
16.0
14.0
TH
Output level [mVp-p]
12.0
Gain [dB]
10.0
8.0
6.0
140
DL
120
4.0
EX burst
2.0
0
3.786
4.286
100
–10
4.786
f – Frequency [MHz]
0
25
50
75
Ta – Ambient temperature [°C]
Vcc = 5.0V
SECAM/PB mode
Input level: 83mVp-p (BELL IN)
Output: C OUT (Pin 15)
Vcc = 5.0V
PAL/PB mode
Input level: 150mVp-p (PB C IN)
fsc: 350mVp-p
Output: 4.43MHz BPF OUT
(The output level is the average during 2H.)
– 25 –
CXA1203M/N
TH/DL/EX burst phases vs. Ambient temperature
SQ DET input/output vs. Ambient temperature
112
120
110
Phase of the input signal [deg]
108
104
102
EX burst
100
98
TH
96
80
Output at Pin 17
H→L
60
DL
94
92
–10
40
0
25
50
75
0
25
Ta – Ambient temperature [°C]
Vcc = 5.0V
PAL/PB mode
Input level: 150mVp-p
(PB C IN)
fsc: 350mVp-p
Output: C OUT (Pin 15)
Vcc = 5.0V
PAL/RESET mode
Input level: 150mVp-p
(PB C IN)
fsc: 350mVp-p
Output: SQ ID (Pin 17)
Relation of the phase of each pulse to the C Sync signal
C Sync
(Pin 11)
A
B
HD
(Pin 10)
C
D
EX burst
(Pin 15)
Phases of the HD and EX burst vs. Ambient temperature
C
5.0
D
B
4.0
3.0
2.0
A
1.0
0
0
50
75
Ta – Ambient temperature [°C]
The phase is the absolute value
determined by measuring the
center angle of the TL, DL or EX
burst during 2H with reference to
the fsc (at Pin 18).
Time [µs]
Phase [deg]
106
Output at Pin 17
L→H
100
25
50
Ta – Ambient temperature [°C]
– 26 –
75
The phase of the input
signal is the absolute value
of the phase delay to the
fsc. This is determined by
delaying the phase of the
input signal to the fsc and
measuring the phase delay
when the output changes.
CXA1203M/N
Package Outline
Unit: mm
CXA1203M
24PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
15.0 – 0.1
0.15
24
0.24
6.9
+ 0.1
0.2 – 0.05
1.27
0.5 ± 0.2
12
1
0.45 ± 0.1
+ 0.2
0.1 – 0.05
7.9 ± 0.4
+ 0.3
5.3 – 0.1
13
M
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SONY CODE
SOP-24P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP024-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
Kokubu Ass'y
24PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
15.0 – 0.1
0.15
24
0.24
6.9
+ 0.2
0.1 – 0.05
1.27
+ 0.1
0.2 – 0.05
0.5 ± 0.2
12
1
0.45 ± 0.1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
13
M
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SONY CODE
SOP-24P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP024-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 27 –
CXA1203M/N
Unit: mm
CXA1203N
24PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗7.8 ± 0.1
0.1
24
13
∗5.6 ± 0.1
7.6 ± 0.2
A
1
12
b
0.13 M
0.65
B
b=0.22 ± 0.03
0.5 ± 0.2
0.1 ± 0.1
+ 0.03
0.15 – 0.01
Package Outline
DETAIL B : PALLADIUM
0° to 10°
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-24P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-SSOP24-7.8x5.6-0.65
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
– 28 –
Sony Corporation