NJU26126 Digital Signal Processor ■ General Description The NJU26126 is a high performance 24-bit digital signal processor. The NJU26126 provides L/R channel independent 10bands PEQ, Low/High bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio Delay, eala & eala Rebirth of NJRC Original Sound Enhancement, Dynamic Bass Boost, two systems Limiter, and 5.1 channel output function. These kinds of sound functions are suitable for TV, mini-component, CD radio-cassette, Sound bar and speakers system. ■Package NJU26126VC2 ■ FEATURES - Software • NJRC Original Sound Enhancement (eala, eala Rebirth, Dynamic Bass Boost) • HPF, LPF, Center/Sub woofer and Surround output function • 10bands PEQ (Parametrical Equalizer) : L/R channel independent operation • DRC (Dynamic Range Compression) : 2-bands independent operation (FIR filter adoption) • Tone Control (Bass / Treble) • Limiter (SDO0 / SDO1) • Lip sync Audio Delay (fs=48kHz : Max. 22msec) • Signal level detector • Watchdog Clock Output - Hardware • 24bit Fixed-point Digital Signal Processing • Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit • Digital Audio Interface : 3 Input ports / 3 Output ports • Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs • Master / Slave Mode - Master Mode, MCK : 384fs @32kHz, 256fs @48kHz • Host Interface : I2C bus (Fast-mode/400kbps) • Power Supply : 3.3V • Input terminal : 5V Input tolerant • Package : SSOP24-C2 (Pb-Free) Ver.2010-08-19 -1- NJU26126 ■ Function Block Diagram 24Bit Fixed-point DSP Core SCL SDI0-2 2 I C INTERFACE SDA SDO0-2 PROGRAM CONTROL BCK 24Bit x 24Bit MULTIPLIER RESETb MCK SERIAL AUDIO INTERFACE ALU LR TIMING GENERATOR / PLL CLKOUT CLK ADDRESS GENERATION UNIT SLAVEb Internal Pow er (1.8V) WDC Built-in LDO DATA RAM VREGO External Low -ESR Capacitors Required GPIO INTERFACE FIRMWARE ROM PROC AD1 1.8V level terminal Fig. 1 NJU26126 Block Diagram ■ DSP Block Diagram NJU26126 Block Diagram SDI0 SDI1 SDI2 Signal Level Detector (No Signal Counter) Delay (22ms) Input Trimmer PEQ eala / eala Rebirth Tone Control (10band/9band+HPF) SW1 (0.5dB step) SW2 Dynamic Bass Boost Exec Volume (0~-96dB,mute, 0.25dB step) SW3 L/R trimmer (0~-96dB,mute, 0.5dB step) Delay処理位置は、Input/SDO0/SDO1/SDO2の The Delay processing position can be exclusively Selected from either of Input/SDO0/SDO1/SDO2. いずれかから排他的に選択可能です。 EXEC Output SW5(DRC enable/disable) HPF SW DRC(HPF) SW SW LPF DRC(LPF) SW SW DRC Mixer HPF Output SW SW eala / eala Rebirth PROC Output SW2 Surround Signal Generator LPF Output Surround Output SW4 (DRC Xover enable/disable) C/SW Output C/SW Mixer HPF/LPF executing even if DRC is disabled. ・DRCがOFFでもHPF/LPFは動作します。 When and XOVER option are only enabled, DRC Mixer can be used. ・DRCDRC MixerおよびDRC(LPF)は、DRCがEnableで、 If なおかつXOVER optionがEnableの場合のみ使用可能です。 you send Filter coefficient, you can use the XOVER frequencies other than the preset frequency. (However, it is limited to 2000Hz or less.) PROC Output HPF Output LPF Output EXEC Output C/SW Output Surround Output SDO0/1/2 Source Select Delay (22ms) SDO0 Delay (22ms) SDO1 Delay (22ms) SDO2 SDO0 Master Volume (+24dB~-96dB,mute, 0.25dB step) & Channel Trimmer SDO1 Limiter Limiter SDO0 SW6 SDO1 SW7 (0dB~-96dB,mute, 0.5dB step) SDO2 SDO2 Delay処理位置は、 The Delay processing position can be exclusively Input/SDO0/SDO1/SDO2のいずれかから排他的に選択可能です。 Selected from either of Input/SDO0/SDO1/SDO2. Fig. 2 NJU26126 Function Diagram -2- Ver.2010-08-19 NJU26126 ■ Pin Configuration RESETb 1 24 TEST LR 2 23 SCL BCK 3 22 SDA SDI2 4 21 SDO2 SDI1 5 20 SDO1 19 SDO0 18 WDC NJU26126 SDI0 6 MCK 7 VDD 8 17 PROC VSS 9 16 AD1 STBYb 10 15 SLAVEb VSS 11 14 CLK VREGO 12 13 CLKOUT SSOP24-C2 Fig. 3 NJU26126 Pin Configuration ■ Pin Description Table 1 Pin Description No. Symbol I/O Description No. Symbol I/O Description 1 RESETb I RESET (active Low) 13 CLKOUT O OSC Output 2 LR I/O LR Clock 14 CLK I OSC Clock Input 3 BCK I/O Bit Clock 15 SLAVEb I Slave select 4 SDI2 I Audio Data Input 2 L/R 16 AD1 I I2C Address 5 SDI1 I Audio Data Input 1 L/R 17 PROC I Status select after Reset DSP 6 SDI0 I Audio Data Input 0 L/R 18 WDC OD Clock for Watch Dog Timer 7 MCK I/O Master Clock 19 SDO0 O Audio Data Output 0 8 VDD Power Supply +3.3V 20 SDO1 O Audio Data Output 1 9 VSS GND 21 SDO2 O Audio Data Output 2 10 STBYb I For TEST (Connected to VDD) 22 SDA OD I2C I/O 11 VSS GND 23 SCL I I2C Clock 12 VREGO PI Built-in Power Supply Bypass 24 TEST I For TEST(Connected to VSS) * I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass AD1 (No.16) pin and PROC (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance. However, these pins operate as bi-directional pins. No.16pin and No.17pin connect with VDD or VSS through 3.3kΩ resistance. No.18pin do not connect or connect with VDD through 3.3kΩ resistance when unused. VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin. A built-in power supply is used only for NJU26126 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies. Ver.2010-08-19 -3- NJU26126 ■ Absolute Maximum Ratings ( VSS=0V=GND, Ta=25°°C ) Rating Units Table 2 Absolute Maximum Ratings Parameter Symbol Supply Voltage * Supply Voltage Bypass * VDD VREGO -0.3 to 4.2 -0.3 to 2.3 In Vx(IN) I/O, OD Vx(I/O) ,Vx(OD) -0.3 to 5.5 (VDD ≥ 3.0V) -0.3 to 4.2 (VDD < 3.0V) Out Vx(OUT) CLK Vx(CLK) CLKOUT Vx(CLKOUT) Pin Voltage * V V V -0.3 to 4.2 Power Dissipation Operating Voltage Storage Temperature 565 mW PD -40 to 85 TOPR °C TSTR -40 to 125 °C * The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. * VDD : 8 pin * VREGO : 12 pin * Vx(IN) : 1, 4, 5, 6, 10, 15, 23, 24 pin * Vx(OD) : 22 pin * Vx(I/O) : 2, 3, 7, 16, 17, 18 pin * Vx(OUT) : 19, 20, 21 pin * Vx(CLK) : 14 pin * Vx(CLKOUT) : 13 pin ■ Terminal equivalent circuit diagram VDD VDD(1.8V) CLK CLKOUT VDD VDD(1.8V) PAD RPD VSS V SS Input, I/O (Input part) (1 to 7, 22, 23pin) (with RPU : 18pin , With RPD: 15, 16, 17, 24pin) CLK/CLKOUT (13, 14pin) VDD RPU VDD PAD PAD Output Disable VSS Output, I/O (Output part) (2, 3, 7, 16, 17, 19, 20, 21pin ) ( Open Drain Output with RPU : 18pin) ( Open Drain Output: 22pin ) VSS STBYb (10pin) Fig.4 NJU26126 Terminal equivalent circuit diagram -4- Ver.2010-08-19 NJU26126 ■ Electric Characteristics ( VDD=3.3V, fOSC=12.288MHz, Ta=25°°C ) Table 3 Electric Characteristics Parameter Operating Voltage Symbol *1 Test Condition Min. Typ. Max. Units 3.0 3.3 3.6 V - 20 35 mA VDD VDD pin Operating Current IDD At no load High Level Input Voltage VIH VDD x 0.7 - VDD Low Level Input Voltage VIL 0 - VDD x 0.3 High Level Output Voltage Low Level Output Voltage *3 Clock Frequency Clock Jitter *5 Clock Duty Cycle *4 V VOH (IOH= -1mA) VDD x 0.8 - VDD VOL (IOL= 1mA) 0 - VDD x 0.2 -10 - 10 -120 - 10 IIN(PD) -10 - 120 fOSC 10 12.288 13 MHz 0 - ±3.0 ns 45 50 55 % IIN Leakage Current *2 IIN(PU) fJIT(CC) rEC VIN = VSS to VDD CLK, MCK *6 µA *1 VDD of The NJU26126 should be within electric characteristics. When turn on VDD, the voltage should be increase monotonously. After rise up the voltage to within electric characteristics, the voltage should be not under electric characteristics. When re-start the NJU26126 after cut the power, the voltage of VDD should be drop to GND level. *2 Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin. *3 Except No.18pin: WDC (Open-Drain output) and No.22: SDA (Open-Drain input/output). *4 I IN(PU) : 18pin, I IN(PD) : 15, 16, 17, 24 pin *5 Clock Jitter shows Cycle-to-cycle period jitter (JEDEC JESD65). *6 Provide clock frequency for fOSC spec. NJU26126 needs clock frequency 12.288MHz when sampling rate is 48kHz. Ver.2010-08-19 -5- NJU26126 1. Power Supply, Input/Output terminal, Clock, Reset 1.1 Power Supply The NJU26126 has a power supply VDD. To setup good power supply condition, the decoupling capacitors should be implemented at the all power supply terminals. VDD of The NJU26126 should be within electric characteristics. When turn on VDD, the voltage should be increase monotonously. After rise up the voltage to within electric characteristics, the voltage should be not under electric characteristics. When re-start the NJU26126 after cut the power, the voltage of VDD should be drop to GND level. The NJU26126 include a built-in power supply (LDO) for internal logic. A built-in power supply generates 1.8V (-10% to +10%). VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin. A built-in power supply is used only for NJU26126 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies. 1.2 Input/Output terminal It restricts, when the input terminals (AD1, PROC, RESETb, SDI0, SDI1, SDI2, STBYb, SLAVEb, SCL, TEST pins), the input/output terminals (LR, BCK, MCK pins) and the bi-directional Open-drain terminal (SDA pin) of NJU26126, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input tolerant. 1.3 Clock The NJU26126 CLK pin requires the system clock that should be related to the sample frequency 256 Fs. (For example : Fs=48kHz CLK=12.288MHz ) It is possible to be generated the system clock by connecting a crystal oscillator between CLK and CLKOUT. CLK/CLKOUT pins are not 5V tolerant, so check the voltage level of these pins. When SLAVEb pin is fixed on Low level, NJU26126 supplies the system clock from MCK pin. Fix the clock input pin not used to Low level because either the CLK pin or the MCK pin is supplied in NJU26126. The frequency divider for Master mode matched to the clock 256 times of Fs is installed in NJU26126. When clock except 256 times of Fs is used by Master mode, be careful to use because a dividing frequency of Master mode changes. Please check enough and decide parameter. -6- Ver.2010-08-19 NJU26126 1.4 Reset To initialize the NJU26126, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26126. After the power supply and the oscillation of the NJU26126 becomes stable, RESETb pin must be kept Low-level more than tRESETb period. (Fig.5) After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial Host Interface completes NJU26126 within 10msec. Then, it will be in the state which can communicate. VDD tVREGO VREGO CLK OSC unstable OSC stable tRESETb RESETb Fig.5 Reset Timing Table 4 Reset Time Symbol Time tVREGO ≥ 10msec tRESETb ≥ 1.0msec Note : All the I/O terminals and the Open-Drain I/O terminals compulsorily enter the state of the high-impedance when it is made RESETb=Low. However, the pull-up/pull-down of the terminal that has adhered the pull-up/pull-down is effective. Don’t stop the supply of a clock while operating. NJU26126 installs PLL circuit internally. If the supply of a clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26126 does not operate normally. If supply of a clock is stopped or the NJU26126 is reset again, putting a normal clock into CLK terminal, the period RESETb terminal of tRESETb is kept “Low” level.(Table 4) Next, the NJU26126 is reset. Then redo from initial setting. Ver.2010-08-19 -7- NJU26126 2. Digital Audio Clock Digital audio data needs to synchronize and transmit between digital audio systems. Thus, a device in the system generates the transmitted clock become a standard. The other devices are set according to the transmitted clock. The device generating transmitted clock is called Master Device. The device according to the transmitted clock is called Slave Device. NJU26126 usually operates Slave Device (In this specifications, called Slave mode). However, NJU26126 becomes Master Device in case of SLAVEb set the High level and NJU26126 is set Master mode by firmware command. In Slave mode, clock inputted to the BCK pin and the LR pin is used to digital audio signal transmission. In Master mode, clock outputted to the BCK pin and the LR pin is used to digital audio signal transmission. 2.1 Audio Clock Three kinds of clocks are needed for digital audio data transfer. (1) LR clock (LR) is needed by serial-data transmission. It is the same as the sampling frequency of a digital audio signal. (2) Bit clock (BCK) is needed by serial-data transmission. It becomes the multiple of LR clock. (3) Master clock (MCK) is needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is not related to serial audio data transmission. In SLAVEb is High level, the MCK pin becomes buffer output pin for input clock to the CLK pin after NJU26126 resets. The MCK output is able to be stopped by firmware command. In SLAVEb is Low level, MCK pin becomes system clock input pin. It is not insure to change the logical switch of SLAVEb pin during operating. If it is necessary to change SLAVEb pin setting, reset NJU26126 every time. Table 5 SLAVEb, BCK, LR, MCK SLAVEb and firmware LR pin setting SLAVEb=”Low” LR clock input Firmware: each DSP slave operating SLAVEb=”H” Firmware: Slave SLAVEb=”H” Firmware: Master LR clock output DSP Master operating BCK pin Bit clock input DSP slave operating Bit clock output DSP Master operating MCK pin NJU26126 operating clock input (MCK or CLK) Master clock output (Buffer of CLK) In NJU26126 is used by 256 times of Maximum sampling frequency, NJU26126 is able to output LR clock of same sampling rate and two-third times of sampling rate, and output BCK clock of 32 times sampling rate and 64 times sampling rate in Master mode. -8- Ver.2010-08-19 NJU26126 Table 6 Input clock (In Slave mode) Mode Clock Signal Multiple Frequency 32kHz 44.1kHz 48kHz LR 1fs 32kHz 44.1kHz 48kHz BCK (32fs) 32fs 1.024MHz 1.4112MHz 1.536MHz BCK (64fs) 64fs 2.048MHz 2.822MHz 3.072MHz DSP MCK Input terminal: used for a clock for NJU26126 is generated by Slave (SLAVEb=”L”) MCK or CLK terminal MCK Buffer output of CLK 12.288MHz (SLAVEb=”H”) Table 7 Output clock (In Master mode) Mode Clock Signal Multiple Frequency DSP Master LR BCK (32fs) BCK (64fs) MCK 1fs 32fs 64fs Buffer output of CLK Ver.2010-08-19 32kHz 32kHz 1.024MHz 2.048MHz CLK pin frequency 44.1kHz 48kHz 48kHz 1.536MHz 3.072MHz 12.288MHz -9- NJU26126 3. Digital Audio Interface 3.1 Digital Audio Data Format The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format. : MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing) (1) I2S (2) Left-justified : LR clock -- MSB is placed for changing. (3) Right-justified : LSB is placed just before LR clock change rate. The main differences among three kinds of formats are in the position relation between LR clock (LR) and an audio data (SDI, SDO). - In every format: : a left channel is transmitted previously. - In Right/Left-justified : LR clock ='High' shows a left channel. - I2S : LR clock=”Low” shows a left channel. - The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than the number of sum total transmission bits of a L/R channel is needed at least. - One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes equal to a sample rate (Fs). - The NJU26126 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode. 3.2 Serial Audio Data Input/output The NJU26126 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output lines: SDO0, SDO1 and SDO2. (Table 9). Table 8 Serial Audio Input Pin Description Pin No. Symbol Description 6 SDI0 Audio Data Input 0 L/R 5 SDI1 Audio Data Input 1 L/R 4 SDI2 Audio Data Input 2 L/R Table 9 Serial Audio Output Pin Description Pin No. Symbol Description 19 SDO0 Audio Data Output 0 20 SDO1 Audio Data Output 1 21 SDO2 Audio Data Output 2 - 10 - Ver.2010-08-19 NJU26126 The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format; (1) I2S (2) Left-Justified (3) Right-justified and 16 / 18 / 20 / 24bits data length. (Fig.6-1 to Fig6-12) An audio interface input and output data format become the same data format. Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig.6-1 I2S Data Format 64fs, 24bit Data LRI, LRO Left Channel Right Channel BCKI, BCKO MSB LSB MSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 23 32 Clocks Fig.6-2 Left-Justified Data Format 64fs, 24bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig.6-3 Right-Justified Data Format 64fs, 24bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig.6-4 I2S Data Format 64fs, 20bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 19 32 Clocks Fig.6-5 Left-Justified Data Format 64fs, 20bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks MSB LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks Fig.6-6 Right-Justified Data Format 64fs, 20bit Data Ver.2010-08-19 - 11 - NJU26126 Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig.6-7 I2S Data Format 64fs, 18bit Data LRI, LRO Left Channel Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 17 32 Clocks Fig.6-8 Left-Justified Data Format 64fs, 18bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB MSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig.6-9 Right-Justified Data Format 64fs, 18bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig.6-10 I2S Data Format 32fs, 16bit Data LRI, LRO Left Channel Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig.6-11 Left-Justified Data Format 32fs, 16bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig.6-12 Right-Justified Data Format 32fs, 16bit Data - 12 - Ver.2010-08-19 NJU26126 3.3 Serial Audio Input Timing Table 10 Serial Audio Input Timing Parameters Parameter Symbol Test Condition Min ( VDD=3.3V, Ta=25°°C ) Typ. Max Units BCK Frequency * BCK Period * Low Pulse Width High Pulse Width BCK to LR Time ** fBCKI - - 6.5 MHz tSIL tSIH tSLI 75 75 40 - - ns - - ns LR to BCK Time ** tLSI 40 - - ns Data Setup Time tDS 15 - - ns Data Hold Time tDH 15 - - ns * It is the regulation of absolute maximum ratings. Maximum frequency of BCK is limited. ** It is the regulation in slave mode. LR tSIH tSIL tSLI tDS tDH tLSI BCK SDI Fig.7 Serial Audio Input Timing Table 11 Serial Audio Output Timing Parameters Parameter Symbol Test Condition BCK to LR Time * tSLO Data Output Delay tDOD CL=25pF Min ( VDD=3.3V, Ta=25°°C ) Typ. Max Units -15 - 15 ns - - 15 ns * It is the regulation in Master mode. LR tSLO BCK tDOD SDO Fig.8 Serial Audio Input Timing Ver.2010-08-19 - 13 - NJU26126 ■ Host Interface The NJU26126 can be controlled via Serial Host Interface (SHI) using I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. Refer to serial Host Interface Pin Description.(Table 12) Table 12 Serial Host Interface Pin Description Symbol Pin No. I2C bus Format (I2C bus) 16 AD1 I2C bus address Bit Serial Data Input/Output 22 SDA (Open Drain Input/Output) 23 SCL Serial Clock Note : SDA pin (No.22) is a bi-directional open drain terminal. This pin requires a pull-up resister. AD1 (No.16) pin is input pin with pull-down. AD1 (No.16) pin is connected with VDD or VSS through 3.3kΩ resistance. When NJU26126 is stopped by power supply VDD, SDA pin and SCL pin become Hi-Z. But these pins are not 5V tolerant when VDD stops. ■ I2C bus I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. SDA pin is a bi-directional open drain and requires a pull-up resister. AD1 pin (pin#16) is used to configure LSB of the seven-bit SLAVE address of the serial host interface. Two addresses are supported by fixed value (Table 13) and connection of AD1 pin. Table 13 I2C bus SLAVE Address bit7 0 0 bit6 0 0 Start bit Fixed value bit5 bit4 1 1 1 1 bit3 1 1 Slave Address ( 7bit ) bit2 0 0 AD1 bit1 0 1 R/W bit R/W bit0 R/W ACK * SLAVE address is 0 when AD1 is “Low”. SLAVE address is 1 when AD1 is “High”. * SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”. Note : The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I2C bus data transfer. - 14 - Ver.2010-08-19 NJU26126 ( VDD=3.3V, fOSC=12.288MHz, Ta=25°°C ) Table 14 I2C bus Interface Timing Parameters Parameter Symbol Min Max Units fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF 0 0.6 1.3 0.6 0.6 0 250 0.6 1.3 400 0.9 1000 300 - KHz µs µs µs µs µs Ns Ns Ns µs µs SCL Clock Frequency Start Condition Hold Time SCL “Low” Duration SCL “High” Duration Start Condition Setup Time Data Hole Time *1 Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time *2 SDA tR tBUF tF tHD:STA SCL tHD:STA t LOW P tHD:DAT tHIGH tSU:STA tSU:DAT tSU:STO Sr S P 2 Fig.9 I C bus Timing Note : *1 tHD:DAT: Keep data 100ns hold time to avoid indefinite state by SCL falling edge. *2 This item shows the interface specification. The interval of a continuous command is specified separately. Ver.2010-08-19 - 15 - NJU26126 ■ Pin setting The NJU26126 operates default command setting after resetting the NJU26126. In addition, the NJU26126 restricts operation at power on by setting PROC pin (No.17) (Table 15). This pin is input pin. However, this pin operates as bi-directional pin. Connect with VDD or VSS through 3.3kΩ resistance. Table 15 Pin setting Pin No. Symbol Setting “High” 17 PROC “Low” Function The NJU26126 does not operate after reset. Sending start command is required for starting operation. The NJU26126 operates default setting after reset. The default value of Master Volume is Mute. ■ WatchDog Clock The NJU26126 outputs clock pulse through WDC (No.18) pin during normal operation. In the audio processing, WDC terminal notify NJU26126 operate correctly to other device by toggled (Low/High) output constantly. The unusual condition can be detected, to monitor WDC terminal by a microcomputer or a WDT IC. Watchdog clock output cycle is about 170msec. Note: If input and output of an audio signal stop and an audio interface stops, WDC can’t output. That is because it has controlled based on the signal of an audio interface. - 16 - Ver.2010-08-19 NJU26126 ■ NJU26126 Command Table Table 16 NJU26126 Command No. Command No. Command 1 Set Task 21 DRC (HPF) threshold level setup 2 Fs Select 22 DRC (LPF) threshold level setup 3 Smooth Control setup 23 PEQ Setup 4 Input Select 24 eala / eala Rebirth setup 5 SDO0 output source select 25 User define Xover filter coefficient setup 6 SDO1 output source select 26 User define Xover filter Freq. select 7 SDO2 output source select 27 D.B.B ratio & time constant setup 8 DRC mode select 28 D.B.B threshold level setup 9 DRC Xover frequency select 29 D.B.B filter setup 10 Delay setup 30 Signal detection setup 11 System Status Configuration 31 Firmware Version Number 12 Tone Control (Bass@100Hz) 32 Firm ware Revision Number 13 Tone Control (Treble@10kHz) 33 Software Reset 14 Limiter (SDO0) time constant setup 34 No signal counter read 15 Limiter (SDO0) ratio / limit &boost level setup 35 No signal counter reset 16 Limiter (SDO1) time constant setup 36 No signal detection output enable 17 Clipper (SDO1) ratio / limit &boost level setup 37 No signal detection output disable 18 Trimmer Setup 38 Boot with Mute 19 DRC (HPF) ratio & time constant setup 39 Boot with Un-mute 20 DRC (LPF) ratio & time constant setup 40 No Operation (Nop) . Please demand details of the command separately. Ver.2010-08-19 - 17 - NJU26126 ■ Package SSOP24-C2, Pb-Free [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 18 - Ver.2010-08-19