NJU26501 Preliminary Multi-Function Digital Audio Decoder ■ General Description The NJU26501 is a multi-function digital audio signal decoder. The NJU26501 processes the stereo matrix-encoded or compressed signal into spacious sound of up to 7.1(max) channels by Dolby Digital, Dolby Digital EX or DTS with Bass Management System. Also non matrix-encoded audio signal can be processed into effective spacious sound by Dolby ProLogic II. The decoded multi-channel signal can be downmixed into 2-channel virtual surround output by the Dolby Virtual technology. The applications of the NJU26501 are suitable for multi-channel products such as DVD Player, AV AMP, Home Theater and Car Audio, or any kinds of multi-channel audio products. ■Package TQFP- 52 ■ FEATURES · Dolby Digital / Dolby Digital EX (7.1ch) · DTS (5.1ch) · Dolby Pro Logic II · Virtual Dolby Digital · Bass Management ■ Digital Signal Processor Specification · 24bit Fixed-point Digital Signal Processing · Maximum Clock Frequency : 24.576MHz(Standard), built-in PLL Circuit · Digital Audio Interface : 2 Input ports / 4 Output ports · Microcomputer Interface : I2C Bus (Standard-mode/100Kbps, Fast-mode/400kbps) : 4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data) · Power Supply : DSP Core : 1.8V : I/O interface: 3.3V(+5.0V tolerant) · Package : TQFP 52pins * Note1: “Dolby,” “Pro Logic II,” “Dolby Digital,” “Dolby Digital EX,” and the double-D symbol are trademarks of Dolby Laboratories. The NJU26501 may only be supplied to licensees of or companies authorized by Dolby Laboratories. Please refer all licensing inquiries to Dolby Laboratories. * * Note2: “DTS” is a registered trademark of DTS, Inc. Note3: Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard specification as defined by Philips. Ver.2003-08-29 -1- NJU26501 ■ DSP Block Diagram AD1/SDIN NJU26501 AD2/SSX 24bit Fixed-point DSP Core SCL/SCK BCKO SERIAL HOST INTERFACE SDA/SDOUT PROGRAM CONTROL SEL1 ALU RESETX MCK/ MCK2 TIMING GENERATOR / PLL CLK CLKOUT SERIAL AUDIO INTERFACE LRO 24-BIT x 24-BIT MULTIPLIER BL/BR SDO0 SDI0 /1 BITSTREAM PROCESSOR L/R SDO1 CRC C/SW SDO2 BCKI ADDRESS GENERATION UNIT SL/SR SDO3 LRI PLLDIS MCK2ENX DISOUTX Bitstream / DATA RAM Coef. ROM FIRMWARE ROM TEST INTERFACE All I/O and Output Drivers(except CLKOUT) TEST [0:3] TEST 4,6 TEST 5,[7:11] Fig.1-1 NJU26501 Block Diagram ■ Multi-function Digital Audio Decoder BCKI LRI Serial Audio Interface SDO0 SDO1 SDO2 SDO3 Dolby Digital Decoder Dolby ProLogicII Decoder Clock Generator SDI0 SDI1 CLK CLKOUT DTS Dolby Digital EX PCM BCKO LRO Noise Genarator Bass Management Surround & Center Delay Virtual Dolby Digital Serial Host Interface SCL/SCK AD1/SDIN SDA/ AD2/SSX SDOUT RESETX Fig.1-2 NJU26501 Function Diagram -2- Ver.2003-08-29 NJU26501 LRO BCKO MCK MCK2 VSSIO VDDIO VDD VSS AD2/SSX AD1/SDIN SDA/SDOUT SCL/SCK SEL1 39 38 37 36 35 34 33 32 31 30 29 28 27 ■ Pin Configuration TEST9 40 26 TEST8 SDO3 41 25 TEST7 SDO2 42 24 TEST6 SDO1 43 23 VSSIO SDO0 44 22 CLK VSS 45 VDD 46 TEST10 47 TEST11 21 CLKOUT 20 VDDIO 19 VSS 48 18 VDD SDI1 49 17 VDDPLL SDI0 50 16 VSSPLL VSSIO 51 15 TEST5 VDDIO 52 14 DISOUTX 6 7 8 9 10 11 12 13 TEST2 TEST3 TEST4 VSSIO VDDIO MCK2ENX RESETX 4 VDD TEST1 3 VSS 5 2 BCKI TEST0 1 LRI NJU26501 TQFP 52pin (10mmx10mm) Fig.1-3 Pin Configuration Ver.2003-08-29 -3- NJU26501 ■ Pin Description Table1-1 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Symbol LRI BCKI VSS VDD TEST0 TEST1 TEST2 TEST3 TEST4 VSSIO VDDIO MCK2ENX RESETX DISOUTX TEST5 VSSPLL VDDPLL VDD VSS VDDIO CLKOUT CLK VSSIO TEST6 TEST7 TEST8 SEL1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSX VSS VDD VDDIO VSSIO MCK2 MCK BCKO LRO TEST9 SDO3 SDO2 SDO1 SDO0 VSS VDD TEST10 TEST11 SDI1 SDI0 VSSIO VDDIO I/O I I G P I/O I/O I/O I/O O G P Ipd I Ipu Ipd G P P G P I/O I G O Ipd Ipd Ipu I I/O I I G P P G O O O O Ipu O O O O G P I I I I G P Function LR Clock Input Bit Clock Input DSP Core Power Supply GND DSP Core Power Supply +1.8V for test (connect with VSSIO through 3.3-ohm resistance.) for test (connect with VDDIO or VSSIO through 3.3-ohm resistance.) for test (connect with VDDIO or VSSIO through 3.3-ohm resistance.) for test (connect with VDDIO or VSSIO through 3.3-ohm resistance.) for test (Open) I/O Power Supply GND I/O Power Supply +3.3V MCK2 Enable (’0’ : MCK2 enable / ‘1’ : MCK2 turns Hi-Z ) Reset (RESX=’0’ : DSP Reset) Disable Output (’0’:All outputs (except CLKOUT) turn Hi-Z) for test (connect to VSSIO) PLL Power Supply GND PLL Power Supply +1.8V DSP Core Power Supply +1.8V DSP Core Power Supply GND I/O Power Supply +3.3V OSC Clock Output OSC Clock Input (24.576MHz) I/O Power Supply GND for test (Open) for test (connect to VSSIO) for test (connect to VSSIO) 2 Select Host Interface (‘1’ : 4-wire serial mode / ‘0’ : I C mode) 2 2 I C SCL (I C mode) / Serial clock (4-wire serial mode) 2 2 I C SDA (I C mode) / Serial Out (4-wire serial mode) 2 2 I C Address (I C mode) / Serial In (4-wire serial mode) 2 2 I C Address (I C mode) / Serial enable (4-wire serial mode) DSP Core Power Supply GND DSP Core Power Supply +1.8V I/O Power Supply +3.3V I/O Power Supply GND A/D,D/A Clock Output (Buffered output of CLK input) A/D,D/A Clock Output (2-Divided output of CLK input) Bit Clock Output LR Clock Output for test (connect to VDDIO) Audio Data Output ch.3 (Surround channel (LS/RS) output) Audio Data Output ch.2 (Center/Sub Woofer channel (C/SW) output) Audio Data Output ch.1 (Front channel (L/R) output) Audio Data Output ch.0 (Back Surround channel (BL/BR) output) DSP Core Power Supply GND DSP Core Power Supply +1.8V for test (connect to VSSIO) for test (connect to VSSIO) Audio Data Input ch.1 Audio Data Input ch.0 I/O Power Supply GND I/O Power Supply +3.3V Note I:In, Ipd:Input Pull-down, Ipu:Input Pull-Up, O:Out, I/O:Bidir, P:+Power, G:GND -4- Ver.2003-08-29 NJU26501 ■ Absolute Maximum Ratings Table1-2 Absolute Maximum Ratings Parameter Supply Voltage Symbol Rating Units Logic PLL I/O VDD VDDPLL VDDIO -0.3 - 2.1 -0.3 - 2.1 VDD - 3.8 V In, I/O Vx -0.3 - 5.5 Out Vx(OUT) -0.3 - VDDIO +0.3 Pin Voltage V CLK Vx(Xi) -0.3 - VDDIO +0.3 CLK Vx(Xo) -0.3 - VDD +0.3 OUT Power Dissipation PD 0.3 W Storage Temperature TSTR -40～+125 ℃ * Vx : Pin No. 1,2,5,6,7,8,12,13,14,15,25,26,27,28,29,30,31,40,47,48,49,50 : Pin No. 9,24,36,37,38,39,41,42,43,44 * Vx(OUT) : Pin No. 22 * Vx(Xi) * Vx(Xo) : Pin No. 21 ■ Terminal equivalent circuit diagram VDDIO VDD RPU CLK PAD RPD CLK VDDIO VDD OUT VSS VSS Input, I/O (Input part) CLK/CLKOUT (No.1,2,5,6,7,8,13,28,29,30,31,47,48,49,50 pin) (No.21, 22 pin) (With RPU: No. 14, 27, 40 pin) (With RPD: No. 12,15,25,26 pin) VDDIO PAD Output Disable VSSIO Output, I/O (Output part) (No. 5,6,7,8,9,29,36,37,38,39,41,42,43,44 pin) Fig.1-4 NJU26501 Terminal equivalent circuit diagram Ver.2003-08-29 -5- NJU26501 ■ Electric Characteristics Table1-3 Electric Characteristics (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Operating Voltage Symbol Logic PLL I/O Operating Current VDD VDDPLL VDDIO Leakage Current (at output high impedance) High Level Output Voltage (for OSC Output Pad) Low Level Output Voltage -6- V - 4.0 - IDDIO VDDIO =3.3V - 3.0 - -40 25 85 2.0 VDD * 0.7 -0.3 - -0.3 - - - 5.25 VDDIO + 0.3 0.5 VDD * 0.3 10 -10 - - －150 - 10 100 - 400 -10 －100 - 400 - - 10 －200 - －50 －300 - 10 －10 - 10 - - 10 -10 - - -150 - 10 -30 - 10 2.7 - - VDDIO * 0.9 - - 1.5 - - - - 0.4 VIH(OSC) VIL VIL(OSC) IIN(PD) IIN(PU) IIN(OSC) IOZ(IO) (for I/O Pad) (for Output Pad) 1.9 1.9 3.6 VDD=VDDPLL=1.8V VDDIO=3.0 - 3.6V VDDIO=3.0 - 3.6V VDD=1.7 - 1.95V VDDIO=3.0 - 3.6V VDDO=3.0 - 3.6V VDD=1.7 - 1.95V VIN = VDDIO – 5.25V VIN = VSSIO VIN = VSSIO - VDDIO VIN = VSSIO VIN = VSSIO - VDDIO VIN = VDDIO – 5.25V (for OSC Input pad) 1.8 1.8 3.3 IDDPLL VIN = VDDIO – 5.25V (for Pull-Up pads) 1.7 1.7 3.0 - IIN (for Pull-Down pads) Units 40 VIH Input Current Max. - High Level Input Voltage (for OSC Input pad) Typ. VDD=VDDPLL=1.8V TOPR Low Level Input Voltage VDD pins VDDPLL pins VDDIO pins Min. IDD Operating Temperature (for OSC Input pad) Test Condition IOZ(OUT) VOH VOH(OSC) VOL VIN = VSSIO VIN = VSSIO - VDDIO VIN = VSSIO - VDDIO VIN= VDDIO – 5.25V DISOUTX=VIL VIN= VSSIO DISOUTX=VIL VIN= VSSIO – VDDIO DISOUTX=VIL VIN= VSSIO – VDDIO DISOUTX=VIL IOH= -2mA VDDIO=3.0V IOH= -300uA VDDIO=3.0 – 3.6V IOH=-100uA VDDIO=3.0V, VDD=1.7V IOL=2mA, VDDIO=3.0V - mA ℃ V V μA μA V V Ver.2003-08-29 NJU26501 (for OSC Output Pad) VOL(OSC) Input Capacitance CIN Input Transition Time tr / tf Clock Frequency Clock Duty Cycle IOL=300uA VDDIO=3.0 – 3.6V - - VDDIO * 0.1 IOL=100uA VDDIO=3.0V, VDD=1.7V - - 0.2 - 6 - pF - - 100 ns fOSC except for No.28, 29, 30, 31pin * No.22pin(CLK) 24 24.576 25 MHz rEC No.22pin(CLK) 45 50 55 % * The tr / tf of these terminals are specified separately. * All input / input-and-output terminals serve as the Schmidt trigger inputs except for No.22pin(Xi). * To fix a terminal level, the fixed level should be lower than VDDIO. * Do not carry out the pull-up of the output terminals on the voltage more than VDDIO. Ver.2003-08-29 -7- NJU26501 1. Power Supply, Clock and Reset 1.1 Power Supply The NJU26501 has three power supplies VDD/VSS, VDDPLL/VSSPLL and VDDIO/VSSIO. VDD/VSS is used as an internal core power supply, VDDPLL/VSSPLL is used as an internal PLL power supply and VDDIO/VSSIO is used as I/O terminal power supply. NOTICE: The power supply is turned on or turned off in order of the follow. The power supply is turned on: VDD -> VDDPLL -> VDDIO The power supply is turned off: VSS -> VSSPLL -> VSSIO There is a procedure to turn on the NJU26501. A power supply should surely start VDDIO first. Then, please start VDD and, finally supply VDDPLL. If the procedure to turn on is not kept right, there is possibility that excessive current makes fatal damage to the NJU26501 and the external circuit parts. Moreover, turn off of a power supply by the reverse sequence of turning on a power supply. To setup good power supply condition, the decoupling capacitors should be implemented at the all power supply terminals. Although there is no time parameter about the injection of a power supply, potential should not be crossed during an injection between power supplies The VDDPLL/VSSPLL supplies the power for internal PLL circuit. The VDDPLL/VSSPLL is sensitive to power-line noise. The VDDPLL/VSSPLL line should be separate from internal core power supply VDD or provide noise filters to prevent from power supply noise. Without these countermeasures, there is possibility of PLL oscillation-stop and so on. VDD VDDPLL 10Ω + 10uF 0.1uF Fig. 1-5 The example of a simple power supply filter -8- Ver.2003-08-29 NJU26501 1.2 Clock The NJU26501 CLK pin requires the system clock that should be related to the sample frequency fs. The CLK/CLKOUT pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator. Refer to the application circuit diagram about the circuit parameters. When the external oscillator is connected to CLK/CLKOUT pins, check the voltage level of the pins. Because the maximum input voltage level of CLK pin is deferent from the other input or bi-directional pins. The maximum voltage-level of CLK pin equals to VDD. Note: Contact with a manufacture maker about use of a crystal oscillator/ceramic vibrator. When a crystal oscillator or a ceramic vibrator is used, it connects only required parts of an oscillator. Do not take out a signal from CLK/CLKOUT. It becomes the cause of an unusual oscillation and oscillation stop. When an external clock is used, do not connect other parts to CLKOUT. When the clock inputted into a CLK terminal is required to be used further externally, fix MCK2ENX terminal to a Low level, and use the signal outputted from MCK terminal. When a crystal oscillator is used, choose a crystal oscillator of a basic wave. 10pF 1KΩ CLKOUT 24.576 MHz 1MΩ CLK 10pF Fig.1-6 The example of the oscillator circuit. Ver.2003-08-29 -9- NJU26501 1.3 Reset To initialize the NJU26501, RESETX pin should be set low level during some period. After some period of Low level, RESETX pin should be High level. This procedure starts the initialization of the NJU26501. After the power supply and the oscillation of the NJU26501 becomes stable, RESETX pin should be kept Low-level at least tRESETX period. To finalize the initialization procedure takes 1 m sec. After 1 m sec, the NJU26501 can accept a command from Host controller. The detail status of the initialized NJU26501 is referred to the each command that describes the initial status. To select I2C bus or 4-Wire serial bus, some level should be supplied to SEL1 pin. When SEL1=”L”, I2C bus is selected. When SEL1=”H”, 4-Wire serial bus is selected. The level of SEL1 is checked by the NJU26501 in 1 m sec after RESETX pin level goes to “H”. VDD CLK Oscillation instability Internal PLL Oscillation stability Lock-up Trigger operation DISOUTX* RESETX tRESETX Fig. 1-7 Reset Timing Table 1-4 Reset Time Symbol tRESETX Time >= 300us Note: It is better to connect a RESETX terminal and a DISOUTX terminal so that it avoids to compete bi-direction terminals in instability state after a power supply injection. If DISOUTX terminal is fixed “L” level, output driver of output terminal except CLKOUT terminal and bi-direction terminal becomes invalid. A clock should continue supplying during operation. The NJU26501 has the PLL circuit. When supply of a clock is stopped, the NJU26501 is impossible for PLL to send a normal clock to an inside. If supply of a clock is stopped or the NJU26501 is reset again, it requires locking PLL again. Putting a normal clock into CLK terminal, the period RESETX terminal of tRESETX is kept “L” level. Next, the NJU26501 is reset. Then redo from initial setting. - 10 - Ver.2003-08-29 NJU26501 2 System Clock Audio data samples must be transferred in synchronism between all components of the digital audio system. That is, for each audio sample originated by an audio source there must be one and only one audio sample processed by the NJU26501 and delivered to the D/A converters. To accomplish this, one device in the system is selected to generate the audio sample rate; the other devices are designated to follow this sample rate. The device that generates the audio sample rate is called the MASTER device; all devices following this sample rate are called SLAVE(s) Although the NJU26501 is usually used as a slave device, it can also be used as MASTER device. The clock frequency supplied to the NJU26501 is 24.576MHz. When the NJU26501 is in MASTER mode, the NJU26501 can generate a required system clock to 48MHz of sampling frequency. NOTICE The clock frequency of 24.576MHz(48KHz x 512) should be supplied to the NJU26501. The NJU26501 employs PLL circuit and divider circuit for Master mode inside. These circuits are designed for 24.576MHz clock frequency. If the clock frequency does not meet the clock frequency specification, this causes possibility of the next troubles. For example, PLL is out of lock. The NJU26501 cannot process the decoding correctly. 2.1 Audio Clock Three types of clock signals are included in the serial audio interface. Two of the clock signals LR (LRI and LRO) and BCK (BCKI and BCKO) establish data transfer on the serial data lines. The third clock, MCK and MCK2 , is not associated with serial data transfer but is required by delta-sigma A/D and D/A converters. In the NJU26501, it has two kinds of output terminals of MCK and MCK2 so that it may be properly used by apprications. The frequency of the LR clock is, by definition, equal to the digital audio sample rate, Fs. BCK and MCK operate at multiples of the LR clock rate. Therefore the signals LR, BCK and MCK/MCK2 must be locked, that is, they must be generated or derived from a single frequency reference. When RESETX is “L”, the NJU26501 dose not generate MCK clock. In “H”, the clock signal divided CLK in half is generated to MCK. In case of MCKENX=”L”, buffered CLK is generated to MCK2. In case of MCKENX=“H”, CLK does not generate MCK2 by changing a terminal into a high impedance state. Table2-1 Sampling Frequency and BCK, MCK, CLK Mode Slave Master Clock Signal LR BCK(32Fs) BCK(64Fs) LR BCK(32Fs) BCK(64Fs) MCK(256Fs) from DSP MCK2(512Fs) from DSP* CLK Multiple Frequency 1Fs 32Fs 64Fs 1Fs @Fs=48KHz 32Fs @Fs=48KHz 64Fs @Fs=48KHz 32Khz 32kHz 1.024MHz 2.048MHz 44.1kHz 44.1kHz 1.4112MHz 2.822MHz 48kHz 1.536MHz 3.072MHz 256Fs @Fs=48KHz 12.288MHz 512Fs @Fs=48KHz 24.576MHz 512Fs @Fs=48KHz 24.576MHz 48kHz 48kHz 1.536MHz 3.072MHz * Set MCK2ENX=Low Ver.2003-08-29 - 11 - NJU26501 SDO0 SDO1 SDO2 SDO3 SDI0 SDI1 BCKI BCKO LRI LRO MCK CLOCK DIVIDER MCK2 MASTER SLAVE CLK CLKOUT BOTH Oscillator Fig. 2-1 MASTER / SLAVE Mode - 12 - Ver.2003-08-29 NJU26501 3. Audio Interface The serial audio interface carries audio data to and from the NJU26501. Industry standard serial data formats of I S, MSB-first left-justified or MSB-first right-justified are supported. These serial audio formats define a pair of digital audio signals (stereo audio) on each data line. Two clock lines, BCK (bit clock) and LR (left/right word clock) establish timing for serial data transfers. Serial audio data which synchronized with two kinds of clocks spreads on a system by SDI/SDO. 2 The NJU26501 serial audio interface includes 2 data input lines: SDI0/SDI1 and 4 data output lines: SDO0 to SDO3 as shown in the figure below. The input serial data is selected by the firmaware command. Table 3-1 Serial Audio Output Pin Description Symbol Pin No. Description SDO0 44 Back Surround (BL/BR) Output SDO1 43 Front (L/R) Output(*) SDO2 42 Center/Sub Woofer (C/SW) Output SDO3 41 Surround (LS/RS) Output (*) In Virtual Dolby Surround mode, only front Lch/Rch outputs are active. The other channels are muted. The NJU26501 has a pair of bit clock lines (BCKI and BCKO) and a pair of left/right clock lines (LRI and LRO). The clock inputs BCKI and LRI are used to accept timing signals from an external device when the NJU26501 operates in SLAVE mode. The clock outputs BCKO and LRO are provided for delta-sigma A/D and D/A converters when the NJU26501 operates in MASTER mode. In SLAVE mode, the output of BCKO and LRO are the buffered output of BCKI and LRI, In SLAVE mode, the NJU26501 does not generate MCK clock and fixes MCK to “L”. The MCK always generates half of the system clock supplied to the NJU26501 expect RESET sequence. In MCK2ENX=”L”, the MCK2 is always buffered output of system clock supplied to the NJU26501. In MCK2ENX=”H”, the MCK2 is high impedance output. In MASTER mode, the MCK/MCK2 and BCKO/LRO synchronize. Serial Data Inputs SDI0 SDI1 SDO0 SDO1 SDO2 SDO3 Serial Data Outputs NJU26501 Serial Clock Inputs BCKI LRI BCKO LRO MCK / MCK2 Serial Clock Outputs System clock for A/D, D/A converters (DSP MASTER mode only) Fig. 3-1 Serial Audio Interface Ver.2003-08-29 - 13 - NJU26501 3.1 Audio Data Format The NJU26501 can exchange data using any of three industry-standard digital audio data formats: I2S, MSB-first Left-justified, or MSB-first Right-justified. The three serial formats differ primarily in the placement of the audio data word relative to the LR clock. Left-justified format places the most-significant data bit (MSB) as the first bit after an LR transition. I2S format places the most-significant data bit (MSB) as the second bit after an LR transition (one bit delay relative to left-justified format). Right-justified format places the least-significant data bit (LSB) as the last bit before an LR transition. All formats transmit the stereo sample left channel first. Note that polarity of LR is opposite in I2S format (LR:LOW = Left channel data) compared to Left-Justified or Right-Justified formats. Clock LR (LRI, LRO) marks data word boundaries and clock BCK (BCKI, BCKO) clocks the transfer of serial data bits. One period of LR defines a complete stereo audio sample and thus the rate of LR equals the audio sample rate (Fs). The number of BCK clock must follow the serial data format. If the BCK clock is not enough , the right sound are not produced. The serial data format should be the same as A/Ds ,D/As or Codecs which are used. The NJU26501 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode. 3.2 Serial Audio Data Transmitting Diagram Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 23 32 Clocks Fig. 3-2 Left-Justified Data Format 64Fs, 24bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB MSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig. 3-3 Right-Justified Data Format 64Fs, 24bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks MSB LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks Fig. 3-4 I2S Data Format 64Fs, 24bit Data - 14 - Ver.2003-08-29 NJU26501 Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 19 32 Clocks Fig. 3-5 Left-Justified Data Format 64Fs, 20bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig. 3-6 Right-Justified Data Format 64Fs, 20bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig. 3-7 I2S Data Format 64Fs, 20bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB LSB MSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI, SDO LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 17 32 Clocks Fig. 3-8 Left-Justified Data Format 64Fs, 18bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO 2 1 0 LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks MSB LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks Fig. 3-9 Right-Justified Data Format 64Fs, 18bit Data Ver.2003-08-29 - 15 - NJU26501 Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Clocks 32 Clocks Fig. 3-10 I2S Data Format 64Fs, 18bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig. 3-11 Left-Justified Data Format 32Fs, 16bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig. 3-12 Right-Justified Data Format 32Fs, 16bit Data Left Channel LRI, LRO Right Channel BCKI, BCKO MSB SDI, SDO LSB MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Clocks 16 Clocks Fig. 3-13 I2S Data Format 32Fs, 16bit Data - 16 - Ver.2003-08-29 NJU26501 3.3 Serial Audio Timing Table 3-2 Serial Audio Input Timing Parameters (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Symbol Test Condition Min Typ. Max Units - - 4.0 MHz BCKI Frequency BCKI Period L Pulse Width tSIL 85 H Pulse Width tSIH 85 - - ns BDKI to LRI Time tSLI 40 - - ns LRI to BCKI Time tLSI 40 - - ns Data Setup Time tDS 40 - - ns Data Hold Time tDH 40 - - ns LRI tSIH tSIL tSLI tLSI BCKI tDS tDH SDI0,1 Fig. 3-14 Serial Audio Input Timing Ver.2003-08-29 - 17 - NJU26501 Table 3-3 Serial Audio Output Timing Parameters (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Symbol Test Condition CL:LRO, BCKO, SDO=25pF Min Typ. Max Units 20 - - ns BCKO to LRO Time tSLO LRO to BCKO Time tLSO 20 - - ns Data Output Delay tDOD - - 20 ns LRO tSLO tLSO BCKO tDOD SDO0,1,2,3 Fig. 3-15 Serial Audio Output Timing - 18 - Ver.2003-08-29 NJU26501 Table 3-4 Serial Audio Clock Parameters (SLAVE mode) (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Symbol LRI to LRO Delay tPDL BCKI to BCKO Delay tPDB Test Condition CL:LRO, BCKO, SDO=25pF DSP Slave mode Min Typ. Max Units - - 20 ns - - 20 ns LRI LRO tPDL BCKI BCKO tPDB Fig. 3-16 Serial Audio Clock Timing (SLAVE mode) Ver.2003-08-29 - 19 - NJU26501 Table 3-5 Serial Audio Clock Parameters (MASTER mode) (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Symbol CLK to MCK2 Delay MCK2 to MCK, BCKO, LRO Delay Output Clock Duty Cycle tPDM2 tPDM rEM Test Condition CL:LRO, BCKO, MCK, MCK2=25pF DSP Master mode MCK2ENX=”L” CLK:rEC=50% Min Typ. Max Units - - 20 ns -20 - 20 ns 45 50 55 % CLK MCK2 tPDM2 MCK BCKO* * DSP MASTER mode tPDM rEM Fig. 3-17 Serial Audio Clock Timing (MASTER mode) - 20 - Ver.2003-08-29 NJU26501 4. Host Interface The NJU26501 can be controlled via Serial Host Interface (SHI) using either of two serial bus format : 4-Wire serial bus or I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The SEL1 pin controls the serial bus mode. When the SEL1 is low during the NJU26501 initialization, 4-Wire serial bus is available. When the SEL1 is high during the NJU26501 initialization, I2C bus is available. Table 4-1 Serial Host Interface Pin Description Symbol Pin No. 4-Wire Serial bus Format I2C bus Format SCK/SCL 28 Serial Clock Serial Clock SDOUT/SDA 29 Serial Data Output SDIN/AD1 30 Serial Data Input I C bus address Bit1 SSX/AD2 31 SLAVE Select I2C bus address Bit2 (Serial/I2C) Serial Data 2 Note : When 4-Wire Serial bus is selected, SDA /SDOUT pin is CMOS output. When I2C is selected, this pin is a bi-directional open drain. This pin, which is assigned for I2C, requires a pull-up resister. Ver.2003-08-29 - 21 - NJU26501 4.1 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”H” during the Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting SSX = “L”. Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is latched on the falling transitions of SSX. SDOUT is always CMOS output. SDOUT does not require a pull-up resistor. Table 4-2 4-Wire Serial Interface Timing Parameters (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter Input Data Rising Time Input Data Falling Time Serial Clock Rising Time Serial Clock Falling Time Serial Strobe Rising Time Serial Strobe Falling Time Serial Clock H Duration Serial Clock L Duration Serial Clock Period Serial Strobe Setup Time Serial Strobe Hold Time Serial Strobe L Duration Serial Strobe H Duration Input Data Setup Time Input Data Hold Time Output Data Hold Time (from SCK) Output Data Hold Time (from SSX) - 22 - Symbol tMSDr tMSDf tMSCr tMSCf tMSSr tMSSf tMSCa tMSCn tMSCc tMSSs tMSSh tMSSa tMSSn tMSDis tMSDih tMSDoh tMSDov Timelines a-b a-b d-e f-g p-q m-n e-f g-h e-i n-e j-q n-p q-r b-e e-c g-k n-o, q-l Min. 0.5 0.5 1.0 0.5 0.5 0.1 0.1 0 0 Typ. 8.5 1.0 - Max. 100 100 100 100 100 100 0.25 0.25 Units ns ns ns ns ns ns ms ms ms ms ms ms ms ms ms ms ms Ver.2003-08-29 NJU26501 a b c 7 SDIN d 6 e f g h 1 5 0 i j SCK X SDOUT m 6 7 n o 5 1 X 0 k p q l r SSX MSB LSB Fig. 4-1 4-Wire Serial Interface Timing Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSX=”H”. When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSX becomes “H”. Ver.2003-08-29 - 23 - NJU26501 4.2 I2C Bus When the NJU26501 is configured for I2C bus communication in SEL1=”L”, the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. SDA is an open drain pin requiring a pull-up resistor. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. This offers additional flexibility in a system design by offering two different possible SLAVE addresses for which the NJU26501 will respond to. An address can be arbitrarily set up with an internal setup and this AD1 terminal. In the NJU26501, AD2 pin should be connected to “H”. Any I2C address could be chosen for AD1. The I2C address of AD1 is decided by connection of AD1-pin. The I2C address should be the same level of AD1-pin . Table 4-3 I2C Bus SLAVE Address bit7 0 *1 *2 bit6 bit5 bit4 Bit3 bit2 bit1 bit0 0 1 1 1 AD2*1 AD1*2 R/W 2 AD2 pin should be connected to “H”. The I C address of AD2 should be 1. SLAVE address is 0 when AD1 is “L”. SLAVE address is 1 when AD1 is “H”. The figure on the following shows the basic timing relationships for transfers. A transfer is initiated with a START condition, followed by the SLAVE address byte. The SLAVE address consists of the seven-bit SLAVE address followed by a read/write (R/W) bit. When an address with an effective serial host interface is detected, the acknowledgement bit which sets a SDA line to “L” in the ninth bit clock cycle is returned. The R/W bit in the SLAVE address byte sets the direction of data transmission until a STOP condition terminates the transfer. R/W = 0 indicates the host will send to the NJU26501 while R/W = 1 indicates the host will receive data from the NJU26501. SDA 1-7 8 9 1-7 8 9 SCL S Start P Address R/W ACK Data ACK Stop Fig. 4-2 I2C Bus Format In case of the NJU26501, only single-byte transmission is available. The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I2C bus data transfer. However, the NJU26501 is not completely based on I2C bus specification from the characteristic of a SDA I/O terminal and a SCL input terminal. - 24 - Ver.2003-08-29 NJU26501 Table 4-4 I2C Bus Interface Timing Parameters (VDD=VDDPLL=1.8V, VDDIO=VDDO=3.3V, fOSC=24.576MHz, Ta=25°C) Parameter SCL Clock Frequency Start Condition Hold Time SCL “L” Duration SCL “H” Duration Start Condition Setup Time Data Hole Time Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF Standard Mode Min Max 0 400 0.6 1.3 0.6 0.6 0.1 0.9 250 1000 300 0.6 1.3 - Units kHz ms ms ms ms ms ns ns ns ms ms SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P S tHD:DAT tHIGH tSU:STA tSU:DAT Sr t SU:STO P Fig. 4-3 I2C Bus Timing Note : The NJU26501 has similar protocol as I2C bus specification from the characteristic of a SDA I/O terminal and a SCL input terminal. Check the bus driver of other devices intermingled into the same bus has bus drive capability. tHD:DAT: Keep Data Hold Time to avoid indefinite state by SCL falling edge. This item shows the interface specification. Ver.2003-08-29 - 25 - NJU26501 5. Firmware Command Table The NJU26501 allows for user configuration of the decoder with micro controller commands entered via Host interface (serial interface or I2C bus). The following table summarizes the available user commands. Table5-1 NJU26501 Command No. 1 Command System Set Task Command 2 AC3 Decode Command 3 4 PCM Scale Command Maximum Frame Repeat Command 5 Pro Logic II Command 6 Bass Management Command 7 8 9 Delay Command Pink Noise Generator Command Play Command 10 11 12 13 Stop Command Mute Command Unmute Command AC3 Status Read Command 14 15 Version Number Command Audio Interface Configuration Command 16 17 18 19 20 21 22 23 24 25 - 26 - NOP Command READ Command Read Task Command Input Select Command Bass Management Trimmer Command Karaoke Command Virtual Command DTS Status Read Command Bypass Mode Configuration Command Dolby Digital EX Mode Configuration Command Command Description Select Decode Mode : Dolby Digital, DTS, PCM, Noise Generator, etc. Select Dolby Digital Decode Mode : Dynamic Range Control, Compression Mode, Dual Mode. Set PCM Scale Factor. Set repeat times of valid data in case of error. Set Pro Logic II parameters : Decode mode, Panorama mode, Sample Rate, Center Width, Dimension, etc. Set Bass Management parameters : Speaker Size, Speakers Cutoff Frequencies. Set Delay parameters for Center and Surround. Select Noise Generator : L, R, C, LS ,RS, BL, BR. PLAY the setup environment after “STOP” command is issued. Stop the operation and mute outputs until PLAY is issued. Mute function Unmute function Read Command to receive Dolby Digital Decode status information. Check Firmware Version Number. Set Serial Audio Interface parameters. This command is used to check DSP status. READ Command Read DSP status information. Select Serial Input port: SDI0 or SDI1. Set Bass Management trimmer parameters : L, R, C, LS, RS, SW. Set Karaoke parameters : Aware mode, Capable mode, etc. Select Speaker Degree: 15 or 20 degree. Read DTS status information. Select bypass output port: SDO0, SDO1, SDO2, SDO3. Set Dolby Digital EX mode configuration. Ver.2003-08-29 NJU26501 Package Dimensions [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver. 0.90 Ver.2003-08-29 - 27 -