NJU6355 ■TREMINAL DESCRIPTION No. SYMBOL FUNCTION I/O Input/Output Select Terminal for DATA Terminal 1 "H" : Input, "L" : Output During the CE terminal is "L", the DATA terminal is high impedance. Quartz Crystal Connecting Terminal (f=32.768kHz) 2 XT Refer to the line-up table for internal Cg, Cd value. XT 3 Chip Enable Input Terminal (with Pull-down Resistance) "H" : DATA input/output is available. 5 CE "L" : DATA terminal is high impedance. When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to "L". Clock Input Terminal 6 CLK The DATA input/output is synchronized this clock. When the CE terminal is "L" the DATA terminal is high impedance. Serial Timer Data Input/Output Terminal I/O CE DATA H H Input 7 DATA L H Output H L High Impedance L L High Impedance 8 4 VDD VSS Power Supply GND ■FUNCTIONAL DESCRIPTION 1. Timer Data Structure The NJU6355 using BCD code which consisting of 4 bits per 1 digit. The calender function including the last date of each month and the leap year calculation is executed automatically. The unused bit for the timer data is “0”. Timer Data Bit Map Second MSB 0 S6 Minute 0 Hour 0 LSB S0 Range 0 to 59 m6 m5 m4 m3 m2 m1 m0 0 to 59 0 S5 S4 -2- S2 S1 H5 H4 H3 H2 H1 H0 Days of Week 0 0 to 23 W2 W1 W0 1 to 7 D5 D4 D3 D2 D1 D0 1 to 31 Day 0 0 Month 0 0 0 Y7 Y6 Y5 Year S3 M4 M3 M2 M1 M0 1 to 12 Y4 0 to 99 Y3 Y2 Y1 Y0 NJU6355 2. Timer Data Reading When the I/O termianl is "L" and the CE tarminal is "H", timer data can read out. The output is LSB first and the output data strings is shown below. The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the DATA terminal. Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on the CLK terminal and output from the DATA terminal. If the timer data is updated in the data output, there are one second difference between timer data and output data. Type E Days of Hour Minute Second Week The data is read out from LSB of Year, and first 52-bit is effective. Year Month Day If the low voltage detector detect the low battery, (EE)H is written into each digit of timer data and read out. code of (EE)H is a warning for the broken. The < Read Out Timing > CLK CE I/O Data Output 0 1 2 3 4 5 6 7 3 Year Shift Register 0 (1) (2) 1 2 3 4 4 5 6 7 6 7 Second 5 6 7 3 4 5 The timer data is transferred to the shift register at rising edge of the CE (1) and LSB of the timer data is output to the DATA terminal. Afterward the timer data in the shift register shift by synchronized at falling edge of the CLK(2) then output to the DATA terminal time-to-time. Note) When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to “L”. And so, before the CE signal is raised, the I/O signal should be fixed to “L”. -3- NJU6355 3. Timer Data Writing When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared, and the timer data can be written to the NJU6355. The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator divider start the operation. The input data strings are LSB first of each digit as shown below. Type E Days of Hour Minute Second Week The data is read out from LSB of Year, and last 44-bit is effective. Year Month 0 2 Day < Write Down Timing > CLK CE I/O Data Input 1 3 4 5 6 7 3 Year Shift Register 0 1 2 3 4 5 6 7 6 7 Minute 4 5 6 The data is input into the shift register at rising edge of the CLK. 7 3 4 5 The data in the shift register is transferred to the timer counter at this falling edge of the CE, then the oscillator divider start the operation. Note) When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to "L". And so, before the CE signal is raised, the I/O signal should be fixed to "H". 4. Low Voltage Detector The NJU6355 series incorporate the low battery detector. If the supply voltage reduce to the detection level, (EE)H is written into each digit of the shift register as warning code for the CPU. 5. Data Access The NJU6355 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of 5V±10%. It may be broken the data unless 5V±10%. Thus, when the data access, the CE terminal should be "H" after the power supply rise to 5V±10%, then start the operation. -4- NJU6355 CLK CLK tCH tCS CE I/O tDS tCS CE I/O tDH (in) tCH tDH tDS (out) tWDS tr CLK 80% CLK 20% t CWH t CWL tf 50% 20% 50% 50% Vss t RDD tWDH 80% 80% 20% 20% 80% Output Data Input Data 20% Vss ■APPLICATION CIRCUIT Main Power Supply VDD NJU6355 VDD DATA I/O CPU CLK CE VSS XT XT [CAUTION] The specifications on this data book are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -6-