DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4990A
SERIAL I/O CALENDAR & CLOCK
CMOS LSI
The µPD4990A is a CMOS LSI developed to input/output calendar & clock data serially to/from the micro computer.
The crystal frequency is 32.768 kHz and the data items included are time, minute, second, year, month, day, and
week.
FEATURES
•
•
•
•
•
Built-in counters for time (hour, minute, and second) and date (year, month, day, and week)
Leap years are adjusted automatically.
Data is represented in BCD notation (except months in hexadecimal notation) and input/output serially.
Commands can be set by inputting serial data.
Selective timing pulses (TPs) are 64 Hz, 256 Hz, 2 048 Hz, and 4 096 Hz and selective output intervals are 1, 10,
30, and 60 seconds.
ORDERING INFORMATION
PART No.
PACKAGE
µPD4990AC
14-pin plastic DIP (300 mil)
µPD4990AG
16-pin plastic SOP (300 mil)
CONNECTION DIAGRAM (Top View)
C2
1
14
VDD (+)
C2
1
16
VDD (+)
C1
2
13
XTAL
C1
2
15
XTAL
C0
3
12
XTAL
C0
3
14
XTAL
STB
4
11
OUT ENBL
NC
4
13
NC
CS
5
10
TP
STB
5
12
OUT ENBL
DATA IN
6
9
DATA OUT
CS
6
11
TP
GND
(VSS)
7
8
CLK
DATA IN
7
10
DATA OUT
GND
(VSS)
8
9
CLK
µ PD4990AC
µ PD4990AG
NC: NO CONNECTION
Document No. IC-1755 (1st edition)
Date Published March 1997 P
Printed in Japan
©
1989
µPD4990A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD − VSS
−0.5 to 7.0
V
VIN
VSS −0.3 to VDD +0.3
V
Input Voltage
Operating Temperature Range
Topt
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +125
°C
Output Terminal Voltage
VOUT
−0.5 to 7.0
V
ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, CG = CD = 20 pF, CI = 20 kΩ, Ta = 25 °C)
CHARACTERISTIC
Operating Voltage
SYMBOL
MIN.
VDD − VSS
2.00
TYP.
8
Current Consumption
MAX.
UNIT
5.50
V
20
µA
VDD − VSS = 3.60 V
100
µA
VDD − VSS = 5.50 V
0.4*
V
500
kHz
VDD − VSS = 2.0 V, Duty 50 %
±1
µA
VDD − VSS = 5.50 V
IDD
Low Level Output Voltage
VOL
CLK Input Frequency
fCLK
Input Leakage Current
IIN
High Level Input Voltage
VIH
0.7 VDD
VDD
V
Low Level Input Voltage
VIL
VSS
0.3 VDD
V
DC
TEST CONDITIONS
VDD − VSS = 2.0 to 5.5 V
IOL = 500 µA
* TP and DATA OUT are N-channel open drain output.
A.C. ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, VDD − VSS = 2.0 V, Ta = 25 °C)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
C0 to 2, CS − STB Set-up Time
tSU
1
µs
STB Pulse Width
tSTB
1
µs
C0 to 2, CS − STB Hold Time
tHLD
1
µs
TEST CONDITIONS
td1
1**
µs
except Time Read mode
CLK-DATA OUT Delay time
td(c-o)
1
µs
RL = 33 kΩ, C L = 15 pF
DATA IN Set-up Time
tDSU
1
µs
DATA IN Hold Time
tDHLD
1
µs
STB LATCH Delay Time
** Note: When a function mode is Time Read mode (other than Test mode), STB LATCH delay time is 20 µs MAX.
(td2).
2
CLK
CLK
N-ch
OPEN DRAIN
48 Bit Shift Register
DATA
IN
DATA
OUT
COMMAND
Register
BLOCK DIAGRAM
OE
MPX
CLK RH
C3' C2' C1' C0'
1 Hz
YEAR
PS
MON
-TH
D/W
CS
DAY HOUR
MIN
SEC
Time counter
15 Stage Binary Divider
XTAL
XTAL
1/215
OSC
Select signal
generator circuit
64 Hz
STOP
C3'
C0'
C2
C1
C0
STB
1/26
SEC
RESET
TP
TEST
MPX
MPX
PS
D/W
CS
TP
:
:
:
:
:
Multiplexer
Preset
Day of the Week
Chip Select
Timing Pulse
RH
: Register Hold
3
µPD4990A
CS
DECODER
C1'
1 Hz
DATA SELECTOR
C2'
µPD4990A
FUNCTION SPECIFICATIONS
•
Crystal frequency (X tal osc.).
°
•
32.768 kHz
Data
Data types are: second, minute, day, week, month, and year.
Leap years, 31-day months, and months with 30 or less days are adjusted automatically.
A 24-hour system is used and last two digits of Gregorian year are indicated.
It is assumed that leap years are expressed by multiples of 4.
•
Data format
Data is represented in BCD notation. Only months are represented in hexadecimal notation.
•
Data input-output and Clock
Data is input/output synchronously with reference to the external clocks input from the CLK pin using the serial
input/output system. (See Fig. 1.)
•
Timing pulse output
Three frequencies, 64 Hz, 256 Hz, and 2 048 Hz, can be set with C0, C1 and C2 pins.
Using serial data input command, selective timing pulses (TPs) are 64 Hz, 256 Hz, 2 048 Hz, and 4 096 Hz
and selective output intervals are 1, 10, 30, and 60 seconds.
•
Function mode selection
A function mode can be selected by the inputs from C0, C 1, and C2. Also a function mode can be selected through
serial data input. (C0 = C1 = C2 = VDD)
Each command is latched with STB (strobe).
•
Chip select
Connecting the CS pin to the ground level inhibits CLK and STB inputs.
•
Data output inhibition
Connecting the OUT ENBL pin to the ground level sets the DATA OUT pin at high impedance.
Figure 1.
MSB
command
register
Ten's of Unit of
year
year
LSB
month
day of Ten's of Unit of Ten's of Unit of Ten's of Unit of Ten's of Unit of
the week days
days
hours hours minutes minutes seconds seconds
C3' C2' C1' C0'
D3 D2 D1 D0
52 Bit Shift Register
* DATA of 52 Bit Shift Register appears on DATA OUT terminal from LSB of second.
4
µPD4990A
TERMINALS
•
Input terminals
°
°
°
°
°
°
•
CLK
Shift clock input of 40-/52-bit shift register
C 0, C 1, C 2
Command input (3 bit)
STB
Strobe input
CS
Chip select input (Prohibits CLK & STB)
OUT ENBL
Output control input (Makes the DATA OUT high impedance by inputting low level).
DATA OUT
Data output of 40-/52-bit shift register
TP
Timing pulse output
Oscillation terminals
°
°
•
Data input of 40-/52-bit shift register
Output terminals (N-channel Open Drain)
°
°
•
DATA IN
XTAL
Oscillation inverter input (OSC IN)
XTAL
Oscillation inverter output (OSC OUT)
Power supply terminals
°
°
VDD
Plus power supply
GND (VSS)
Common line
5
µPD4990A
COMMAND SPECIFICATIONS
°
Commands input from C0, C1, and C2 pins (1 ...H, 0 ...L)
Shift register 40 bit (The year function is ineffective.)
(Operates as the existing µPD1990AC in other than test mode)
C2
C1
C0
FUNCTION
0
0
0
Register Hold
DATA OUT = 1 Hz
0
0
1
Register Shift
DATA OUT = [LSB] = 0 or 1
0
1
0
Time Set & Counter Hold
DATA OUT = [LSB] = 0 or 1
0
1
1
Time Read
DATA OUT = 1 Hz
1
0
0
TP = 64 Hz
1
0
1
TP = 256 Hz
1
1
0
TP = 2 048 Hz
1
1
1
Serial command transfer mode
* The test mode is cancelled by [C2, C1, C0] = [0, 0, 0] to [1, 1, 0].
°
Serial data commands
Set [C2, C1, C0] = [1, 1, 1] at all time.
Shift register 52 bit (The year function is effective.)
C 3'
C 2'
C1'
C0'
FUNCTION
0
0
0
0
Register Hold
DATA OUT = 1 Hz
0
0
0
1
Register Shift
DATA OUT = [LSB] = 0 or 1
0
0
1
0
Time Set & Counter Hold
DATA OUT = [LSB] = 0 or 1
0
0
1
1
Time Read
DATA OUT = 1 Hz
0
1
0
0
TP = 64 Hz
0
1
0
1
TP = 256 Hz
0
1
1
0
TP = 2 048 Hz
0
1
1
1
TP = 4 096 Hz
1
0
0
0
TP = 1 s interval set (counter reset & start)
1
0
0
1
TP = 10 s interval set (counter reset & start)
1
0
1
0
TP = 30 s interval set (counter reset & start)
1
0
1
1
TP = 60 s interval set (counter reset & start)
1
1
0
0
Interval Output Flag Reset
1
1
0
1
Interval Timer Clock Run
1
1
1
0
Interval Timer Clock Stop
1
1
1
1
TEST MODE SET
When serial data commands are used, C0, C1, and C2 pins should be connected V DD pin.
6
µPD4990A
•
Command input
(1) 3-bit binary code input: C2, C1, C0
(2) 4-bit serial transfer command input: C3', C2', C1', C0'
•
•
Number of commands
C2, C1, C0
C'3, C'2, C' 1, C' 0
Register control
4
4
TP select
3
8
TP control
0
3
Test mode set
1
1
Commands (C3', C2', C1', C0' commands are made effective only when [C2, C1, C0] = [1, 1, 1].)
(1) Register control
°
[C2, C1, C0] / [C3', C2', C1', C0']
Register Hold Mode
[0, 0, 0] / [0, 0, 0, 0]
[C2, C1, C0]
The 40-bit shift register is held. The year function is ineffective.
[C3', C2', C1', C0']
The 48-bit shift register is held.
The command register is not held.
* The DATA OUT output frequency is 1 Hz.
°
Register Shift Mode
[0, 0, 1] / [0, 0, 0, 1]
[C2, C1, C0]
The 40-bit shift register data can be shifted. The year function is ineffective.
[C3', C2', C1', C0']
Data in 52-bit shift registers (including command registers) can be shifted. For command register, data can
be always shifted using the serial command transfer mode.
* The DATA OUT output is LSB data from the shift register.
°
Time Set and Counter Hold Mode
[0, 1, 0] / [0, 0, 1, 0]
[C2, C1, C0]
Data is transferred from the 40-bit shift register to the time counter. The year function is ineffective.
[C3', C2', C1', C0']
Data is transferred from the 48-bit shift register to the time counter.
* This command is used to reset the last 10-15 of 15 Stage Binary Divider and holds the time counter.
15 Stage Binary Divider resetting and time counter release are executed by the following:
[C2, C1, C0] = [0, 0, 0] [0, 0, 1] [0, 1, 1] [C3', C2', C1', C0'] = [0, 0, 0, 0] [0, 0, 0, 1] [0, 0, 1, 1]
The time setting accuracy is ±15.625 ms.
The DATA OUT pin outputs LSB data (0 or 1) from the shift register.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
°
Time Read Mode
[0, 1, 1] / [0, 0, 1, 1]
[C2, C1, C0]
Data is transferred from the time-counter to the 40-bit shift register. The year function is ineffective.
[C3', C2', C1', C0']
Data is transferred from the time counter to the 48-bit shift register.
* The DATA OUT pin output is a 1 Hz frequency.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
7
µPD4990A
(2) TP selection and control
•
[C2, C1, C0] / [C3', C2', C1', C0']
TP = 64 Hz Set Mode [1, 0, 0] / [0, 1, 0, 0]
64 Hz (50 % duty) is output to the TP pin.
[C2, C1, C0]: The year function is ineffective and the interval timer stops.
•
TP = 256 Hz Set Mode [1, 0, 1] / [0, 1, 0, 1]
256 Hz (50 % duty) is output to the TP pin.
[C2, C1, C0]: The year function is ineffective and the interval timer stops.
•
TP = 2 048 Hz Set Mode [1, 1, 0] / [0, 1, 1, 0]
2 048 Hz (50 % duty) is output to the TP pin.
[C2, C1, C0]: The year function is ineffective and the interval timer stops.
Modes permitted only for serial commands
•
[C3', C2', C1', C0']
TP = 4 098 Hz Set Mode [0, 1, 1, 1]
4 098 Hz (50 % duty) is output to the TP pin. The interval timer stops.
•
TP = 1-second Interval Set Mode (counter reset & start) [1, 0, 0, 0]
A 1-second interval signal is output to the TP pin.
•
TP = 10-second Interval Set Mode (counter reset & start) [1, 0, 0, 1]
A 10-second interval signal is output to the TP pin.
•
TP = 30-second Interval Set Mode (counter reset & start) [1, 0, 1, 0]
A 30-second interval signal is output to the TP pin.
•
TP = 60-second Interval Set Mode (counter reset & start) [1, 0, 1, 1]
A 60-second interval signal is output to the TP pin.
•
Interval Output Flag Reset [1, 1, 0, 0]
The interval signal output to the TP pin is reset.
The interval timer counter continue the operation.
•
Interval Timer Clock Run [1, 1, 0, 1]
The timer for outputting interval signals is reset then started.
•
Interval Timer Clock Stop [1, 1, 1, 0]
The timer for outputting interval signals stops.
The output status does not change.
(3) Serial command transfer mode setting
Set [C2, C1, C0] = [1, 1, 1]
(4) Test mode setting
Set [C2, C1, C0] = [1, 1, 1] [C3', C2', C1', C0'] = [1, 1, 1, 1]
°
3-bit parallel command setting mode
[C2, C1, C0]
The year function is ineffective when commands are input through C2, C1, and C0 pins.
Generally, February involves 28 days. The 29th day can be set optionally. The next day of the February
29th can be set the March 1st automatically. The interval timer is in the halt state.
* The test mode is cancelled by [C2, C1, C0] = [0, 0, 0] to [1, 1, 0].
°
Serial command transfer mode
[C3', C2', C1', C0']
If a strobe signal is input with C 2, C1, and C0 pins set at the VDD level ([1, 1, 1]), the contents of the serial
command register ([C3', C2', C1', C0']) are received as a command; the year function is effective.
* The test mode is cancelled by [C3', C2', C1', C0']
= [0, 0, 0]
= [0, 1, 0, 0] to [1, 1, 1, 0]
In this mode, the serial command register is not held with the Register Hold command. Accordingly, the serial
command can be executed irrespective of the mode if the CS pin is active.
The year function is effective in the serial command transfer mode.
8
µPD4990A
°
Interval output function
An interrupt signal can be output by selecting an output from TP.
Interrupt signals are output repeatedly at specified intervals until their output is suppressed by a command.
Only output flags can be reset to operate the timer continuously.
0.5 s
1s
1s
1s
Interval Output
Flag Reset
Interval Timer
Clock Stop
Interval of 1 second
The interval signal waveform is rectangular (50 % duty) if not reset.
The interval timer is independent of the Timer Counter, so it is not affected by the resetting of the current
time timer.
30 s
60 s
Interval Output
Flag Reset
The interval timer accuracy is ±15.625 ms.
* The interval timer counter is reset by [1, 0, 0, 0] through [1, 0, 1, 1].
9
µPD4990A
°
Test mode
In the test mode, data is output to the DATA OUT pin regardless of whether data has been input to OUT
ENBL.
There are two different test modes depending on the OUT ENBL data.
(1) Test mode 1 (OUT ENBL = 0)
8 192 Hz signals are set parallel in the counters for year, month, week, day, time, minute, and second.
There is no carry from these counters.
Year
counter
Month
counter
Week
counter
Day
counter
Time
counter
Minute
counter
Second
counter
8 192 Hz
(2) Test mode 2 (OUT ENBL = 1)
A 8 192 Hz signal is input to the second counter instead of the 1 Hz signal. There is carry from counters.
Year
counter
Month
counter
Week
counter
Day
counter
Time
counter
Minute
counter
Second
counter
8 192 Hz
Outputs from DATA OUT and TP OUT pins in different function modes are listed below.
MODE
DATA OUT
TP
REGISTER HOLD
1 Hz
64 Hz
REGISTER SHIFT
LSB of shift register
32 Hz
TIME SET
LSB of shift register
L Level
1 Hz
32 Hz
TIME READ
Others
By this command, TEST MODE is released.
8 192 Hz input to time counter
Test mode
8 192 Hz input to time counter
When the REGISTER HOLD command cancels the test mode, 64 Hz is output to the TP pin.
10
µPD4990A
TIMING DIAGRAM FOR SETTING COMMANDS (C0', C1', C2', C3')
Figure 2.
DATA
IN
VIH
VIH
VIL
tDSU
CLK
C1'
C0'
C2'
C3'
VIL
tDHLD
VIH
VIH
VIL
VIL
tHLD
tSTB
VIH
STB
VIL
Other than time read mode
NEW COMMAND
VALID
td1
NEW MODE
OLD MODE
td2
Time read mode
OLD MODE
VDD − VSS = 2.0 V
NEW MODE
tDSU = 1 µs MIN.
tDHLD = 1 µs MIN.
tHLD = 1 µs MIN.
tSTB = 1 µs MIN.
td1
= 1 µs MAX. (Other than time read mode)
td2
= 20 µs MAX. (Time read mode)
Note: Command (C 2, C1, C0) is set to (1, 1, 1)
CS = "H"
A mode is latched by STB and held until another mode in the same group is set.
11
µPD4990A
TIMING DIAGRAM FOR SETTING COMMANDS (C0, C1, C2)
Figure 3.
C2,C1,C0
CAN CHANGE
VIH
STABLE
CAN CHANGE
VIH
VIL
VIL
tSU
tHLD
VIH
VIH
CS
tSU
tHLD
tSTB
VIH
STB
VIL
tS-C
CLK
tS-C
VIL
Other than time read mode
td1
NEW COMMAND
VALID
OLD MODE
NEW MODE
Time read mode
td2
OLD MODE
VDD − VSS = 2.0 V
tSU
NEW MODE
= 1 µs MIN.
tHLD = 1 µs MIN.
tSTB = 1 µs MIN.
td1
= 1 µs MAX. (Other than time read mode)
td2
= 20 µs MAX. (Time read mode)
tS-C
= 1 µs MIN.
Note: A mode is latched by STB and held until another mode in the same group is set.
12
µPD4990A
DATA INPUT/OUTPUT TIMING DIAGRAM
Figure 4.
Command (C2, C1, C0) is set to (1, 1, 1).
Command (C3', C2', C0') is set to [0001] (Register Shift Mode).
CS = "H"
CLK
"1" s.
"10" s.
"1" min.
"1" year "10" year
'70
July 16 (Sun.)
2 hours 24 minutes
35 seconds.
DATA
IN
OUT
ENBL
"1" s.
"10" s.
"1" min.
INPUT
TIMING
"1" year "10" year
OUTPUT
TIMING
'86
November 25 (Sat.)
2 hours 23 minutes
49 seconds.
DATA
OUT
0 1 2 3 4 5 6 7 8 9 1011
4041424344454647
Written-in data LSB ("H")
appears at output.
Note: Reading-in timing of CPU (Trailing edge of CLK).
TIMING DIAGRAM OF DATA INPUT AND OUTPUT
Figure 5.
VIH
CLK
VIL
tdC-O
VOH
DATA OUT
VOL
tDSU
tDHLD
VIH
DATA IN
VIL
tdC-O : 1 µ s MAX. (RL = 33 kΩ, CL = 25 pF)
tDSU : 1 µ s MIN.
tDHLD : 1 µ s MIN.
13
µPD4990A
POWER SUPPLY CIRCUIT
1SS53
µ PD4990A
2SA733
+5 V
VDD
Power
Fail
CS
C0
15 kΩ
1 kΩ
510 Ω
C1
1SS53
C2
10 kΩ
OE
DIN
2SC945
3.6 V
Ni−Cd
CLK
4.7 kΩ
GND
STB
32.768 kHz
CG = 20 pF
VSS
XTAL
XTAL
CD = 5 to 30 pF
+5 V
TP
DOUT
10 kΩ
14
µPD4990A
APPLICATION
+5 V
10 kΩ
DATA BUS
D7
D6
D5
D4
D3
D2
D1
D0
WR
Power Fail
4
5
12
D0
D1
Q1
D2
Q2
13 D3
9
Q0
2
7
10
1
DOUT
DIN
OE
CLK
Q3 15
CLK RESET
CS
RD
Address Decoder
+5 V
STB
RESET of
SYSTEM
µ PD4175BC
10 kΩ
VDD
C0
TP
32.768 kHz
CG = 20 pF
C1
Power Supply
Circuit
C2
INT
XTAL
XTAL
CD = 5 to 30 pF
µ PD4990A
15
µPD4990A
14PIN PLASTIC DIP (300 mil)
14
8
1
7
A
K
I
L
J
H
C
F
G
D
N
M
B
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
R
M
ITEM
MILLIMETERS
INCHES
A
20.32 MAX.
0.800 MAX.
B
2.54 MAX.
0.100 MAX.
C
2.54 (T.P.)
0.100 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
1.2 MIN.
0.047 MIN.
G
3.5±0.3
0.138±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
L
6.4
0.252
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.25
0.01
R
0~15°
0~15°
P14C-100-300A,C-1
16
µPD4990A
16 PIN PLASTIC SOP (300 mil)
16
9
P
detail of lead end
1
8
A
H
J
E
K
F
G
I
C
N
D
M
B
L
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
10.46 MAX.
0.412 MAX.
B
0.78 MAX.
0.031 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40 +0.10
–0.05
0.016 +0.004
–0.003
E
0.1±0.1
0.004±0.004
F
1.8 MAX.
0.071 MAX.
G
1.55
0.061
H
7.7±0.3
0.303±0.012
I
5.6
0.220
J
1.1
0.043
K
0.20 +0.10
–0.05
0.008 +0.004
–0.002
L
0.6±0.2
M
0.12
0.005
N
0.10
0.004
P
3 ° +7°
–3°
3° +7°
–3°
0.024 +0.008
–0.009
P16GM-50-300B-4
17
µPD4990A
[MEMO]
18
µPD4990A
[MEMO]
19
µPD4990A
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5