Preliminary R2J20653ANP Integrated Driver – MOS FET (DrMOS) REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Description The R2J20653ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Features • • • • • • • • • • • • • • • Compliant with Intel 6 × 6 DrMOS specification Built-in power MOS FET suitable for Notebook, Desktop, Server application Low-side MOS FET with built-in SBD for lower loss and reduced ringing Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers High-frequency operation (above 1 MHz) possible VIN operating-voltage range: 27 V max Large average output current (Max. 35 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Double thermal protection: Thermal warning & Thermal shutdown Built-in bootstrapping switch Small package: QFN40 (6 mm × 6 mm × 0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 1 10 40 11 THWN Driver Pad High-side MOS Pad DISBL# VSWH MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND VDRV GL PGND 20 30 21 (Bottom view) REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 1 of 12 R2J20653ANP Preliminary Block Diagram Driver Chip VCIN THWN THWN VDRV BOOT GH Boot SW THDN VIN DISBL# High Side MOS FET 2 μA UVL CGND VCIN Level Shifter 25 k CGND 150 k LSDBL# VCIN VSWH PWM Overlap Protection. & Logic Input Logic (TTL Level) (3 state in) Low Side MOS FET VDRV 20 μA PGND CGND GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" 2. Truth table for the LSDBL# pin. Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 3. Output signal from the UVL block UVL output Logic Level For shutdown "L" VCIN VL VH 5. Truth table for the THDN block Driver IC Temp. < 150°C (< 135°C on cancellation) > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 2 of 12 "L" "Open" "H" GL Status "L" "Active" "Active" 4. Output signal from the THWN block For active "H" LSDBL# Input "H" Thermal Warning Logic Level "L" Normal operating Thermal Warning TIC(°C) TwarnL TwarnH R2J20653ANP Preliminary VIN 11 VIN 12 VIN 13 VIN VIN VIN VSWH GH CGND BOOT VDRV VCIN LSDBL# Pin Arrangement 10 9 8 7 6 5 4 3 2 1 40 PWM 39 DISBL# 38 THWN VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH VIN CGND VSWH VSWH PGND VSWH PGND PGND PGND PGND PGND PGND PGND 21 22 23 24 25 26 27 28 29 30 (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# VCIN VDRV BOOT CGND GH VIN VSWH PGND GL THWN DISBL# Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 Description Low-side gate disable Control input voltage (+5 V input) Gate supply voltage (+5 V input) Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning Signal disable PWM 40 PWM drive logic input REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 3 of 12 Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input 5 V gate drive To be supplied +5 V through internal switch Should be connected to PGND externally Pin for monitor Pin for monitor Thermal warning when over 115°C Disabled when DISBL# is "L" This pin is pulled low when internal IC over the thermal shutdown level, 150°C. 5 V logic input R2J20653ANP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage THWN current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN & VDRV VSWH (DC) VSWH (AC) VBOOT (DC) VBOOT (AC) Rating 25 8 35 –0.3 to +27 30 –0.3 to +6 27 30 32 36 Units W Vpwm, Vdisble, Vlsdbl, Vthwn Ithwn Tj-opr Tstg –0.3 to VCIN + 0.3 V 0 to 1.0 –40 to +150 –55 to +150 mA °C °C A V V V V Note 1 2 2, 4 2 2 2, 4 2 2, 4 2, 5 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110°C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow. The specification values indicated "AC" are limited within 100 ns. VCIN + 0.3 V < 6 V Safe Operating Area Average Output Current (A) 45 40 35 30 25 Condition VOUT = 1.3 V VIN = 12 V VCIN = 5 V VDRV = 5 V L = 0.45 μH Fsw = 1 MHz 20 15 10 5 0 0 25 50 75 100 125 150 175 PCB Temperature (°C) Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN & VDRV REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 4 of 12 Rating 4.5 to 22 4.5 to 5.5 Units V V Note R2J20653ANP Preliminary Electrical Characteristics (Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified) Item Symbol Supply PWM input DISBL# input LSDBL# input Thermal warning Thermal shutdown Note: Min Typ Max Units Test Conditions VCIN start threshold VH 4.1 4.3 4.5 V VCIN shutdown threshold VL 3.6 3.8 4.0 V UVLO hysteresis dUVL — 0.5 — V VCIN operating current ICIN — 33 — mA fPWM = 1 MHz, Ton_pwm = 120 ns VCIN disable current ICIN-DISBL — — 2 mA DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM rising threshold VH-PWM 3.0 3.4 3.8 V PWM falling threshold VL-PWM 0.9 1.2 1.5 V PWM input resistance RIN-PWM 10 20 40 kΩ VH – VL PWM = 1 V Tri-state shutdown window VIN-SD VL-PWM — VH-PWM V Shutdown hold-off time tHOLD-OFF *1 — 100 — ns Disable threshold VDISBL 0.9 1.2 1.5 V Enable threshold VENBL 1.9 2.4 2.9 V Input current IDISBL — 2.0 5.0 μA DISBL# = 1 V THDN = 0.2 V 1 THDN on resistance RTHDN * 0.2 0.5 1.0 kΩ Low-side activation threshold VLSDBLH 1.9 2.4 2.9 V Low-side disable threshold VLSDBLL 0.9 1.2 1.5 V Input current ILSDBL –56 –27 –14 μA LSDBL# = 1 V Warning temperature TTHWN *1 95 115 135 °C Driver IC temperature Temperature hysteresis THYS *1 — 15 — °C THWN on resistance RTHWN *1 0.2 0.5 1.0 kΩ THWN = 0.2 V THWN leakage current ILEAK — 0.001 1.0 μA THWN = 5 V Shutdown temperature Tstdn *1 130 150 — °C Driver IC temperature Temperature hysteresis TDHYS *1 — 15 — °C 1. Reference values for design. Not 100% tested in production. REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 5 of 12 R2J20653ANP Preliminary Typical Application 4.5 to 22 V +5 V VCIN VDRV BOOT GH VIN THWN DISBL# R2J20653A NP VSWH LSDBL# PGND PWM CGND VCIN GL VDRV BOOT GH VIN THWN DISBL# R2J20653A NP VSWH LSDBL# PGND PWM CGND GL PWM1 +1.3 V PWM Control Circuit PWM2 PWM3 VCIN VDRV BOOT GH PWM4 VIN THWN DISBL# R2J20653A NP VSWH Power GND LSDBL# PGND PWM CGND VCIN GL VDRV BOOT GH VIN THWN DISBL# R2J20653A NP VSWH LSDBL# PGND PWM CGND REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 6 of 12 GL Signal GND R2J20653ANP Preliminary Pin Connection +5 V 0.1 μF 1.0 μF CGND 0~10 Ω VIN (4.5 V~22 V) Low Side Disable Signal INPUT 4 3 2 1 VDRV VCIN LSDBL# VIN PAD 13 CGND PAD 16 PGND 17 R2J20653ANP 20 THWN 10 kΩ +5 V VSWH 35 10 kΩ +5 V 34 33 PGND 19 PWM INPUT DISBL# GL 36 VSWH PAD 18 39 PWM CGND 37 14 VIN 15 VSWH 40 38 VSWH PGND 5 BOOT 12 6 CGND 10 μF × 4 7 GH 11 8 VSWH 9 VIN CGND 10 21 22 23 24 25 26 27 28 29 30 Thermal Shutdown 32 31 Thermal Warning 0.45 μH Vout PGND Power GND Signal GND REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 7 of 12 PGND R2J20653ANP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The signal on pin DISBL# also enables or disables the circuit. Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# ∗ L H Open Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is connected to the DISBL# pin. The detailed function is described in THDN section. PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal. This pin is internally pulled up to VCIN with 150 kΩ resistor. When low-side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 1.1 Typical Signals during CCM REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 8 of 12 R2J20653ANP Preliminary DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 1.2 Typical Signals during Low-Side Disable Operation The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.4 V or more is required to make the circuit return to normal operation. 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL Figure 2 REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 9 of 12 100 ns (tHOLD-OFF) R2J20653ANP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN DISBL# M1 20 k PWM Pin Tri-state detection signal Input Logic To internal control 20 k Figure 3 Equivalent Circuit for the PWM-pin Input THWN & THDN This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function. This thermal warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 kΩ) to THWN for systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 115°C, thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. "H" THWN output Logic Level "L" Thermal warning Normal operating 100 115 TIC (°C) Figure 4 THWN Trigger Temperature REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 10 of 12 R2J20653ANP Preliminary THDN is an internal thermal shutdown signal when driver IC becomes over 150°C. This function makes high-side MOS FET and low-side MOS FET turn off for the device protection from abnormal high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller. Figure 5 shows the example of two types of DISBL# connection with the system controller signal. Driver IC Temp. < 150°C (< 135°C on cancellation) > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") 5V To Internal Logic 10 k DISBL# 2 μA To shutdown signal To Internal Logic 10 k DISBL# 2 μA Thermal Shutdown Detection Figure 5.1 THDN Signal to the System Controller ON/OFF signal Thermal Shutdown Detection Figure 5.2 ON/OFF Signal from the System Controller MOS FETs The MOS FETs incorporated in R2J20653ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 11 of 12 R2J20653ANP Preliminary Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KC-A Previous Code — MASS[Typ.] — .1 39 ) B HE E B 1pin 40 40 2.2 C0.3 1.95 E /2 INDEX 1.95 4-C0.50 1pin 2.2 (0 D /2 2.2 4- HD/2 0.2 0.2 HD D A 0.7 0.2 Reference Symbol 2.05 X4 f S AB b x 20° S AB L1 S c2 y1 S A A2 0.69 20° 2.05 ZD e t S AB Lp A1 X4 ZE 1.95 2.2 HE/2 CAV No. Die No. 1.95 2-A section y S Dimension in Millimeters Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Ordering Information Part Name R2J20653ANP#G3 Quantity 2500 pcs REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 12 of 12 Shipping Container Taping Reel Sales Strategic Planning Div. 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