To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. Preliminary R2J20651ANP Integrated Driver – MOS FET (DrMOS) REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Description The R2J20651ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Features Compliant with Intel 6 6 DrMOS specification Built-in power MOS FET suitable for applications with 5 V/12 V input Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers VIN operating-voltage range: 16 V max High-frequency operation (above 1 MHz) possible Large average output current (Max. 35 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Built-in thermal warning Built-in Schottky diode for bootstrapping Small package: QFN40 (6 mm 6 mm 0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 1 10 11 40 THWN Driver Pad High-side MOS Pad DISBL# VSWH MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND VDRV GL PGND 20 30 21 (Bottom view) REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 1 of 17 R2J20651ANP Preliminary Block Diagram Driver chip BOOT GH VIN VCIN SBD UVL THWN THWN High-side MOS FET CGND Level shifter DISBL# 25 k 0.5 μA VCIN CGND 150 k LSDBL# PWM VSWH Overlap protection VCIN Input logic (TTL level) (3 state in) Low-side MOS FET 20 μA CGND PGND VDRV Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" 2. Truth table for the LSDBL# pin. Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 3. Output signal from the UVL block LSDBL# Input "L" "Open" "H" GL Status "L" "Active" "Active" 4. Output signal from the THWN block Thermal warning "H" "H" For active UVL Output Logic Level GL For shutdown "L" VL VH REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 2 of 17 VCIN THWN Output Logic Level "L" Normal operating TL TH TIC (°C) R2J20651ANP Preliminary VIN 11 VIN 12 VIN 13 VIN VIN VIN VSWH GH CGND BOOT VDRV VCIN LSDBL# Pin Arrangement 10 9 8 7 6 5 4 3 2 1 40 PWM 39 DISBL# 38 THWN VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH VIN CGND VSWH VSWH PGND VSWH PGND PGND PGND PGND PGND PGND PGND 21 22 23 24 25 26 27 28 29 30 (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# VCIN VDRV BOOT CGND GH VIN VSWH PGND GL THWN DISBL# PWM Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 40 Description Low-side gate disable Control input voltage (+5 V input) Gate supply voltage (+5 V input) Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning Signal disable PWM drive logic input REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 3 of 17 Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input 5 V gate drive To be supplied +5 V through internal SBD Should be connected to PGND externally Pin for Monitor Pin for Monitor Thermal warning when over 130°C Disabled when DISBL# is "L" 5 V logic input R2J20651ANP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN & VDRV VSWH (DC) VSWH (AC) VBOOT (DC) VBOOT (AC) Rating 25 8 35 –0.3 to +16 20 –0.3 to +6 16 25 22 25 Units W Vpwm, Vdisble, Vlsdbl, Vthwn Tj-opr Tstg –0.3 to VCIN + 0.3 V –40 to +150 –55 to +150 °C °C A V V V V Note 1 2 2, 3 2 2 2, 3 2 2, 3 2, 4 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. The specification values indicated "AC" are limited within 100 ns. VCIN + 0.3 V < 6 V Safe Operating Area Average Output Current (A) 45 40 35 30 25 Condition VOUT = 1.3 V VIN = 12 V VCIN = 5 V VDRV = 5 V L = 0.45 μH Fsw = 1 MHz 20 15 10 5 0 0 25 50 75 100 125 150 175 PCB Temperature (°C) Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN & VDRV REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 4 of 17 Rating Units 4.5 to 14 4.5 to 5.5 V V Note R2J20651ANP Preliminary Electrical Characteristics (Ta = 25C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified) Min 3.1 2.7 — — Typ 3.5 3.0 0.5 29 Max 3.9 3.3 — — Units V V V mA ICIN-DISBL — — 50 A PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window VH-PWM VL-PWM RIN-PWM VIN-SD 3.3 0.9 10 4.1 1.5 40 DISBL# input Shutdown hold-off time Disable threshold Enable threshold tHOLD-OFF * VDISBL VENBL LSDBL# input Input current Low-side activation threshold Low-side disable threshold IDISBL VLSDBLH VLSDBLL VL-PWM — 0.9 1.9 — 1.9 0.9 3.7 1.2 20 — 100 1.2 2.4 0.5 2.4 1.2 VH-PWM — 1.5 2.9 2.0 2.9 1.5 V V k V ns V V A V V Input current Warning temperature Temperature hysteresis THWN on resistance ILSDBL TTHWN *1 THYS *1 RTHWN *1 THWN leakage current ILEAK –54 110 — 1.0 — –27 130 15 2.5 0.001 –13.5 — — 4.0 1.0 A °C °C k A Supply PWM input Thermal warning Note: Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current Symbol VH VL dUVL ICIN VCIN disable current 1 1. Reference values for design. Not 100% tested in production. REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 5 of 17 Test Conditions VH – VL fPWM = 1 MHz, Ton_pwm = 120 ns DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM = 1 V DISBL# = 1 V LSDBL# = 1 V Driver IC temperature THWN = 1 V THWN = 5 V R2J20651ANP Preliminary Pin Connection +5 V 0.1 μF 1.0 μF CGND 0~10 Ω VIN (4.5 V~14 V) Low Side Disable Signal INPUT 4 3 2 1 VDRV VCIN LSDBL# VIN PAD 13 CGND PAD 14 VIN 15 VSWH 16 PGND 17 R2J20651ANP 20 PWM INPUT DISBL# THWN DISBL# INPUT GL 36 VSWH 35 51 kΩ +5 V 34 33 PGND 19 39 PWM CGND 37 VSWH PAD 18 40 38 VSWH PGND 5 BOOT 12 6 CGND 10 μF × 4 7 GH 11 8 VSWH 9 VIN CGND 10 21 22 23 24 25 26 27 28 29 30 32 31 0.45 μF Vout PGND Power GND Signal GND REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 6 of 17 PGND R2J20651ANP Preliminary Typical Application (1) 12 V Input Power +12 V +5 V VCIN VDRV BOOT THWN GH VIN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND VCIN GL VDRV BOOT THWN GH VIN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND GL PWM1 +1.3 V PWM Control Circuit PWM2 PWM3 VCIN VDRV BOOT GH PWM4 VIN THWN DISBL# R2J20651A NP VSWH Power GND LSDBL# PGND PWM CGND VCIN GL VDRV BOOT GH VIN THWN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 7 of 17 GL Signal GND R2J20651ANP Preliminary (2) 5 V Input Power +5 V VCIN VDRV BOOT THWN GH VIN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND VCIN GL VDRV BOOT THWN GH VIN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND GL PWM1 +1.5 V PWM Control Circuit PWM2 PWM3 VCIN VDRV BOOT GH PWM4 VIN THWN DISBL# R2J20651A NP VSWH Power GND LSDBL# PGND PWM CGND VCIN GL VDRV BOOT GH VIN THWN DISBL# R2J20651A NP VSWH LSDBL# PGND PWM CGND REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 8 of 17 GL Signal GND R2J20651ANP Preliminary Test Circuit Vinput A IIN V VIN Vcont A ICIN 6.2 Ω VCIN V VCIN VDRV BOOT 0.1 μF VIN DISBL# LSDBL# R2J20651A VSWH NP THWN 5V pulse fPWM Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 9 of 17 PWM CGND PGND GH Electric load IO GL Average Output Voltage Averaging V VO circuit R2J20651ANP Preliminary Typical Data Power Loss vs. Input Voltage Power Loss vs. Output Current 1.5 10 VCIN = 5 V VIN = 12 V 1.4 VOUT = 1.3 V Normalized Power Loss @ VIN = 12 V Power Loss (W) 9 VCIN = 5 V 8 VOUT = 1.3 V fPWM = 600 kHz 7 L = 0.45 μH 6 5 4 3 2 1.2 1.1 1.0 0.9 1 0 fPWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 0 5 10 15 20 25 30 0.8 35 4 6 8 Output Current (A) 12 14 16 Input Voltage (V) Power Loss vs. Output Voltage Power Loss vs. Switching Frequency 1.5 1.5 VIN = 12 V VIN = 12 V 1.4 VCIN = 5 V 1.4 VCIN = 5 V fPWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 1.2 1.1 1.0 Normalized Power Loss @ fPWM = 600 kHz Normalized Power Loss @ VOUT = 1.3 V 10 VOUT = 1.3 V L = 0.45 μH 1.3 IOUT = 25 A 1.2 1.1 1.0 0.9 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 0.8 250 Output Voltage (V) REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 10 of 17 500 750 1000 Switching Frequency (kHz) 1250 R2J20651ANP Preliminary Typical Data (cont.) Power Loss vs. VCIN Power Loss vs. Output Inductance 1.5 1.5 VIN = 12 V VOUT = 1.3 V fPWM = 600 kHz L = 0.45 μH IOUT = 25 A VIN = 12 V 1.4 VOUT = 1.3 V fPWM = 600 kHz 1.3 IOUT = 25 A Normalized Power Loss @ VCIN = 5 V Normalized Power Loss @ L = 0.45 μH 1.4 VCIN = 5 V 1.2 1.1 1.0 1.2 1.1 1.0 0.9 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.8 4.0 Output Inductance (μH) Average ICIN vs. Switching Frequency VIN = 12 V VCIN = 5 V 40 VOUT = 1.3 V L = 0.45 μH IOUT = 0 A 30 20 10 0 250 500 750 1000 Switching Frequency (kHz) REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 11 of 17 4.5 5.0 VCIN (V) 50 Average ICIN (mA) 1.3 1250 5.5 6.0 R2J20651ANP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 3.5 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.0 V or less. The signal on pin DISBL# also enables or disables the circuit. Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# L H Open Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal. This pin is internally pulled up to VCIN with 150 k resistor. When low-side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 1.1 Typical Signals During CCM REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 12 of 17 R2J20651ANP Preliminary DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 1.2 Typical Signals during Low-Side Disable Operation The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.7 V or more is required to make the circuit return to normal operation. 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.7 V PWM 1.2 V GH GL 100 ns (tHOLD-OFF) 3.7 V PWM 1.2 V GH GL Figure 2 REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 13 of 17 100 ns (tHOLD-OFF) R2J20651ANP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN DISBL# M1 20 k PWM Pin Tri-state detection signal Input Logic To internal control 20 k Figure 3 Equivalent Circuit for the PWM-pin Input THWN This thermal warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 k) to THWN for systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 130°C, thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. "H" THWN output Logic Level "L" Thermal warning Normal operating 115 130 TIC (°C) Figure 4 MOS FETs The MOS FETs incorporated in R2J20651ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 14 of 17 R2J20651ANP Preliminary PCB Layout Example Figure 5 shows an example of the PCB layout for the R2J20651ANP. Placing several ceramic capacitors (e.g. 10 F) between VIN and PGND can be expected to the decreasing switching noise and improvement of efficiency. In that case, it is necessary to connect each GND pattern with low impedance by using other PCB layers. Moreover, by taking the wide VSWH pattern, the effect of letting the heat from the low side MOS FET can be expected. When R2J20651ANP is mounted on a small substrate like POL module, the temperature rising of the device could be eased if the thermal via-hole is added under the pad of VIN and VSWH. 10 μF 10 μF Vin 10 μF 10 μF GND 0.1 μF GND GND Rboot 1 μF VCIN VSWH To Inductor GND PWM DISBL# Via Hole Figure 5 R2J20651ANP PCB Layout Example (Top View) REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 15 of 17 R2J20651ANP Preliminary Footprint Example (Unit: mm) 6.20 2.3 0.20 2.3 0.20 0.1 0.1 2.3 0.20 C0.4 6.20 0.6 0.3 C0.1 13–R0.2 2.3 2.15 0.20 2.15 0.50 0.6 40–0.30 Figure 6 Footprint Example REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 16 of 17 R2J20651ANP Preliminary Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KC-A Previous Code — MASS[Typ.] — .1 39 ) B HE E B 1pin 40 40 2.2 C0.3 1.95 E /2 INDEX 1.95 4-C0.50 1pin 2.2 (0 D /2 2.2 4- HD/2 0.2 0.2 HD D A 0.7 0.2 Reference Symbol 2.05 X4 f S AB b x 20° S AB L1 S c2 y1 S A A2 0.69 20° 2.05 ZD e t S AB Lp A1 X4 ZE 1.95 2.2 HE/2 CAV No. Die No. 1.95 2-A section y S Dimension in Millimeters Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Ordering Information Part Name R2J20651ANP#G3 Quantity 2500 pcs REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 17 of 17 Shipping Container Taping Reel Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. 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