PO74HSTL85331A

PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
DESCRIPTION:
FEATURES:
. Patented Technology
. Four HSTL differential outputs
. Selectable differential CLK, nCLK or crystal inputs
. CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
. Operating frequency up to 700MHz with 2pf load
. Operating frequency up to 550MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. Very low output pin to pin skew < 50ps
. 3.3-ns propagation delay (typical)
. 2.3V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
. 5000V Human-BodyModel (A114-A)
. 200V MachineModel (A115-A)
Pin Configuration
GND
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V CC
1
2
3
4
5
6
7
8
9
10
Potato Semiconductor Corporation
The PO74HSTL85331A is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V HSTL
fanout buffer of High Performance Clock Solutions from
PotatoSemi. The PO74HSTL85331A has selectable
differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the PO74HSTL85331A ideal for those applications
demanding well defined performance and repeatability.
Logic Block Diagram
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V CC
Q1
nQ1
Q2
nQ2
D
CLK_EN
CL K
nCLK
CLKIN / XTAL1
CLKOUT / XTAL2
CLK_SEL
V CC
Q3
LE
0
1
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
nQ3
1
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Pin Definitions
Nu m b e r
Na m e
Ty p e
De s c r ip t io n
1
VE E
P o we r
2
C LK_ EN
In p ut
3
C LK_ S EL
In p ut
4
C LK
In p ut
5
n C LK
In p ut
6
XTAL1
In p u t
7
XTAL2
In p u t
8, 9
nc
Un u s e d
10, 13, 18
VC C
P o we r
P o s itive s u p p ly p in s .
GND Pin
S yn c h ro n iz in g c lo c k e n a b le . Wh e n HIG H, c lo c k o u tp u ts fo llo ws c lo c k in p u t.
Wh e n LOW, Q o u tp u ts a re fo rc e d lo w, n Q o u tp u ts a re fo rc e d h ig h .
LVC MO S / LVTTL in te rfa c e le ve ls .
C lo c k s e le c t in p u t. Wh e n LOW, s e le c ts C LK, n C LK in p u t.
P u lld o w n
Wh e n HIG H, s e le c ts XTAL in p u t. LVC MO S / LVTTL in te rfa c e le ve ls .
P u lld o w n No n -in ve r tin g d iffe re n tia l c lo c k in p u t.
P u llu p
P u llu p
In ve r tin g d iffe re n tia l c lo c k in p u t.
P u lld o w n C r ys ta l o s c illa to r in p u t.
P u llu p
C r ys ta l o s c illa to r in p u t.
No c o n n e c t.
11, 12
n Q 3 , Q3
O u tp ut
Diffe re n tia l c lo c k o u tp u ts . HSTL in te rfa c e le ve ls .
14, 15
n Q 2 , Q2
O u tp ut
Diffe re n tia l c lo c k o u tp u ts . HSTL in te rfa c e le ve ls .
16, 17
n Q 1 , Q1
O u tp ut
Diffe re n tia l c lo c k o u tp u ts . HSTL in te rfa c e le ve ls .
19, 20
n Q 0 , Q0
O u tp ut
Diffe re n tia l c lo c k o u tp u ts . HSTL in te rfa c e le ve ls .
NOTE : P u llu p a n d P u lld o wn re fe r to in te rn a l in p u t re s is to rs . S e e Ta b le 2 , P in c h a ra c te ris tic s , fo r typ ic a l va lu e s .
Function Table
In p u t s
C LK_ E N
C LK_ S E L
Ou tp u ts
S e le c t e d S o u r c e
Q0:Q3
n Q0:n Q3
0
0
C LK, n C LK
Dis a b le d ; LOW
Dis a b le d ; HIG H
0
1
XTAL1 , XTAL2
Dis a b le d ; LOW
Dis a b le d ; HIG H
1
0
C LK, n C LK
E n a b le d
E n a b le d
1
1
XTAL1 , XTAL2
E n a b le d
E n a b le d
Afte r C LK_ E N s witc h e s , th e c lo c k o u tp u ts a re d is a b le d o r e n a b le d fo lo win g a ris in g a n d fa llin g in p u t c lo c k o r
c rys ta l o s c illa to r e d g e a s s h o wn in F ig u re 1 .
In th e a c tive m o d e , th e s ta te o f th e o u tp u ts a re a fu n c tio n o f th e C LK, n C LK a n d XTAL1 , XTAL2 in p u ts a s d e s c rib e d
in Ta b le 3 B.
Pin Characteristics
S ym b o l
P a r a m e t er
C IN
In p u t C a p a c ita n c e
Te s t C o n d it io n s
Min im u m
Ty p ic a l
Ma x im u m
Un it s
4
pF
R P ULLUP
In p u t P u llu p R e s is to r
88
K
R P ULLDOWN
In p u t P u lld o wn R e s is to r
88
K
Potato Semiconductor Corporation
2
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to +5.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
VIK
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Potato Semiconductor Corporation
3
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Power Supply Characteristics
Symbol
IccQ
Description
Quiescent Power Supply Current
Test Conditions (1)
Min
Typ
Max
Unit
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
Notes:
1.
2.
3.
4.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Crystal Oscillator Test Conditions
Te s t C o n d it io n s
Un its
Output Frequency
X1=3.579MHz, C4=100pf, C5=100pf
X1=14.318MHz, C4=50pf, C5=50pf
X1=28MHz, C4=50pf, C5=50pf, R1=5.1K
X1=50MHz, C4=50pf, C5=50pf, R1=3K
X1=250MHz, C4=0, C5=0, R1=1K
X1=400MHz, C4=0, C5=0, R1=1K
X1=462MHz, C4=0, C5=0, R1=1K
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.579
14.318
28
50
250
400
462
Notes:
See schematic example.
Switching Characteristics
Symbol
tPD
tr/tf
tsk(o)
tsk(pp)
Description
Test Conditions (1)
M ax
Unit
CL = 15pF
3.7
ns
0.8V – 2.0V
ns
ps
Propagation Delay CLK to Output pair
Rise/Fall Time
Output Pin to Pin Skew (Same Package)
CL = 15pF, 125MHz
0.8
50
Output Skew (Different Package)
CL = 15pF, 125MHz
300
ps
MHz
MHz
fmax
Input Frequency
CL =15pF
fmax
Input Frequency
CL = 5pF
400
250
570
300
fmax
Input Frequency
CL = 2pF
700
400
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Potato Semiconductor Corporation
4
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Test Waveforms
FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS
VCC
VCC= 3.3V
VIH
VPP
VPP RANGE
0V-VCC
VIL
VEE=0.0V
VEE
FIGURE 2. HSTL/HSTL OUTPUT
tr,tf,
20-80%
VO
FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew
for both CLKA or CLKB to output pair
INPUT
CLOCK
VPP
TPLH
TPD
TPHL
OUTPUT
CLOCK
VO
tSK(O)
ANOTHER
OUTPUT
CLOCK
FIGURE 4. CLK_EN Timing Diagram
nCLK
Enabled
Disabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Potato Semiconductor Corporation
5
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Test Circuit
50pF
to
2pF
50Ohm
50pF
to
2pF
50Ohm
Schematic Example
+
3.3V
-
R11
1K
R12
1K
+
U1
40p - 60pF
C4
X1
C5
SPARE
R1
3.3V
C1
0.1u
1
2
3
4
5
6
7
8
9
10
VEE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
NC
NC
VCC
20
19
18
17
16
15
14
13
12
11
3.3V
-
+
3.3V
3.3V
C2
0.1u
Potato Semiconductor Corporation
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
nQ3
-
+
-
C3
0.1u
6
01/01/10
PO74HSTL85331A
www.potatosemi.com
2.3V-3.6V 1:4 Crystal Oscillator/Differential Clock or Data Fanout Buffer
700MHz TTL/CMOS Potato Chip
Packaging Mechanical Drawing: 20 pin TSSOP
20
.169
.177
1
.252
.260
6.4
6.6
4.3
4.5
.047
1.20
Max
SEATING
PLANE
6.1
6.7
.004 0.09
.008 0.20
.002 0.05
.006 0.15
.007
.012
0.19
0.30
.0256
BSC
0.65
.238
.269
.018
.030
0.45
0.75
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
IC Ordering Information
Ordering Code
Package
Top-Marking
TA
20pin 173mil TSSOP
Pb-free & Green PO74HSTL85331AS -40°C to 85°C
PO74HSTL85331ASR for Tape & Reel 20pin 173mil TSSOP
Pb-free & Green PO74HSTL85331AS -40°C to 85°C
PO74HSTL85331ASU for Tube
IC Package Information
PACKAGE
CODE
T
PACKAGE
TYPE
20pin 173mil TSSOP
Potato Semiconductor Corporation
TAPE
WIDTH
(mm)
TAPE
PITCH
(mm)
TAPE & REEL
PIN 1 LOCATION
TAPE TRAILER
LENGTH
16
8
Top Left Corner
39 (12”)
7
QTY
PER TAPE
3000
TAPE LEADER
LENGTH
QTY
PER
TUBE
64 (20”)
74
01/01/10