LC05112CMT CMOS LSI 1-Cell Lithium-Ion Battery Protection IC with integrated Power MOS FET http://onsemi.com Overview The LC05112CMT is a protection IC for 1-cell lithium-ion secondary batteries with integrated power MOS FET. Also it integrates highly accurate detection circuits and detection delay circuits to prevent batteries from over-charging, over-discharging, over-current discharging and over-current charging. A battery protection system can be made by only LC05112CMT and few external parts.. WDFN6 2.6x4.0, 0.65P, Dual Flag Feature Charge-and-discharge power MOSFET are integrated at Ta = 25C, VCC = 4.5V ON resistance (total of charge and discharge) 11.2m (typ) Highly accurate detection voltage/current at Ta = 25C, VCC = 3.7V Over-charge detection ±25mV Over-discharge detection ±50mV Charge over-current detection ±0.7A Discharge over-current detection ±0.7A Delay time for detection and release (fixed internally) Discharge/Charge over-current detection is compensated for temperature dependency of power FET. 0V battery charging : “Unavailable” Over charge detection voltage : 4.0V to 4.5V (5mV steps) Over charge release hysteresis : 0V to 0.3V (100mV steps) Over discharge detection voltage : 2.2V to 2.8V (50mV steps) Over discharge release hysteresis : 0V to 0.075V (25mV steps) Discharge over current detection : 2.0A to 8.0A (0.5A steps) Charge over current detection : 8.0A to -2.0A (0.5A steps) Over-discharge detection delay time : 20ms or 128ms Typical Applications Smart phone Tablet Wearable device ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2014 September 2014 - Rev. 1 1 Publication Order Number : LC05112CMT/D LC05112CMT Specifications Absolute Maximum Ratings at Ta = 25C Symbol Ratings Unit Conditions Supply voltage VCC -0.3-12.0 V Between PAC+ and VCC : R1=680 S1 - S2 voltage VS1-S2 24.0 V CS VCC24.0 V BAT-, PAC- 10.0 A Parameter CS terminal Input voltage Charge or discharge current TST Input voltage TST -0.3-7 V Storage temperature Tstg 55 to +125 C ID 10.0 A VCC = 3.7V IDP 35 A Pulse Width<10s, duty cycle<1% Topr 40 to +85 C Allowable power dissipation Pd 350 mW Junction temperature Tj 125 C Current between S1 and S2(DC) Current between S1 and S2 (continuous pulse) Operating ambient temperature Glass epoxy four-layer board. Board size 27.4mm x 3.1mm x 0.8mm Caution 1) Absolute maximum ratings represent the values which cannot be exceeded even for a moment. Caution 2) If you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Example of Application Circuit Components R1 R2 C1 Recommended value 680 1k 2.2 MAX unit 1k 2k 4.7u F Description * We don’t guarantee the characteristics of the circuit shown above. * TST pin would be better to be connected to VSS pin, though it is connected to VSS with internal resistor (100k typ). http://www.onsemi.com 2 LC05112CMT Electrical Characteristics at Ta = 25C, unless otherwise specified. Parameter Detection voltage Over-charge detection voltage Over-charge release voltage Over-discharge detection voltage Symbol MIN. TYP. MAX. Unit Vov Vovr Vuv Vov_set -25 Vovr_set -40 Vuv_set -50 Vov_set Vovr_set Vuv_set Vov_set +25 Vovr_set +40 Vuv_set +50 mV mV mV R1=680ohm R1=680ohm R1=680ohm Over-discharge release voltage Discharge over-current detection current Discharge over-current release current Discharge over-current detection current (Short circuit) Charge over-current detection current Charge over-current release current Input voltage 0 V battery charge inhibition battery voltage Current consumption Operating current Shutt down current Resistance ON resistance 1 of integrated power MOS FET ON resistance 2 of integrated power MOS FET ON resistance 3 of integrated power MOS FET ON resistance 4 of integrated power MOS FET Internal resistance (VCC-CS) Internal resistance (VSS-CS) Detection and Release delay time Over-charge detection delay time Over-charge release delay time Over-discharge detection delay time Over-discharge release delay time Discharge over-current detection delay time 1 Discharge over-current release delay time 1 Discharge over-current detection delay time 2 (Short circuit) Charge Over-current detection delay time Charge Over-current release delay time Vuvr Vuvr_set -100 Vuvr_set Vuvr_set +100 mV R1=680ohm, CS=0V Ioc Ioc_set -0.7 Ioc_set Ioc_set +0.7 A R2=1k, VCC=3.7V,Pulse input Iocr Ioc_set-0.7 Ioc_set Ioc_set+0.7 A R2=1k, VCC=3.7V,Pulse input Ioc2 14.7 21.0 27.3 A R2=1k, VCC=3.7V,Pulse input Ioch Ioch_set -0.7 Ioch_set Ioch_set +0.7 A R2=1k, VCC=3.7V,Pulse input Iochr Ioch_set-0.7 Ioch_set Ioch_set+0.7 A R2=1k, VCC=3.7V,Pulse input Vinh 0.4 0.9 1.4 V 3.0 6.0 0.1 A A Icc Ishutt k k 10.4 13.0 18.2 m Ron2 9.6 12.0 15.6 m Ron3 9.2 11.6 15.0 m Ron4 8.8 11.2 14.0 m Tov Tovr 300 15 At normal state,VCC=3.7V At Shutt down state,VCC=2.0V VCC=3.1V I=±2.0A VCC=3.7V I=±2.0A VCC=4.0V I=±2.0A VCC=4.5V I=±2.0A VCC=2.0V, CS=0V VCC=3.7V, CS=1.0V Ron1 Rcsu Rcsd Conditions 0.8 12.8 102 16 1.0 16.0 128 20 1.2 19.2 154 24 sec ms VCC=3.7V VCC=3.7V ms VCC=3.7V Tuvr 0.9 1.1 1.3 ms VCC=3.7V Toc1 9.6 12.0 14.4 ms VCC=3.7V Tocr1 3.2 4.0 4.8 ms VCC=3.7V Toc2 80 200 320 us VCC=3.7V Toch 12.8 16.0 19.2 ms VCC=3.7V Tochr 3.2 4.0 4.8 ms VCC=3.7V Tuv Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://www.onsemi.com 3 LC05112CMT Electrical Characteristics2 at Ta = -30 to +70C , unless otherwise specified. Parameter Detection voltage Over-charge detection voltage Over-charge release voltage Over-discharge detection voltage Symbol MIN. TYP. MAX. Unit Vov Vovr Vuv Vov_set -30 Vovr_set -70 Vuv_set -80 Vov_set Vovr_set Vuv_set Vov_set +30 Vovr_set +70 Vuv_set +80 mV mV mV R1=680ohm R1=680ohm R1=680ohm Over-discharge release voltage Discharge over-current detection current Discharge over-current release current1 Discharge over-current detection current2 (Short circuit) Charge over-current detection current Charge over-current release current Resistance Internal resistance (VCC-CS) Internal resistance (S1-CS) Detection and Release delay time Over-charge detection delay time Over-charge release delay time Over-discharge detection delay time Over-discharge release delay time Discharge over-current detection delay time 1 Discharge over-current release delay time 1 Discharge over-current detection delay time 2 (Short circuit) Charge Over-current detection delay time Charge Over-current release delay time Vuvr Vuvr_set -120 Vuvr_set Vuvr_set +120 mV R1=680ohm,CS=0V Ioc Ioc_set -1.2 Ioc_set Ioc_set +1.2 A Iocr Ioc_set-1.2 Ioc_set Ioc_set+1.2 A Ioc2 10.5 21.0 31.5 A Ioch Ioch_set -1.2 Ioch_set Ioch_set +1.2 A Iochr Ioch_set-1.2 Ioch_set Ioch_set+1.2 A Rcsu Rcsd Tov Tovr 300 15 Conditions R2=1k, VCC=2.5-4.3V, Pulse input R2=1k, VCC=2.5-4.3V, Pulse input R2=1k, VCC=2.5-4.3V, Pulse input R2=1k, VCC=2.5-4.3V, Pulse input R2=1k, VCC=2.5-4.3V, Pulse input k k VCC=2.0V, CS=0V VCC=3.7V, CS=1.0V 0.6 9.6 77 12 1.0 16.0 128 20 1.5 24.0 192 30 sec ms VCC=3.7V VCC=3.7V ms VCC=3.7V Tuvr 0.6 1.1 1.5 ms VCC=3.7V Toc1 7.2 12.0 18.0 ms VCC=3.7V Tocr1 2.4 4.0 6.0 ms VCC=3.7V Toc2 50 200 350 us VCC=3.7V Toch 9.6 16.0 24 ms VCC=3.7V Tochr 2.4 4.0 6.0 ms VCC=3.7V Tuv Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://www.onsemi.com 4 LC05112CMT SELECTION GUIDE Device Vov(V) Vovr(V) Vuv(V) Vuvr(V) Ioc(A) Ioch(A) Ioc2(A) LC05112C01MTTTG 4.285 4.085 2.200 2.200 6.3 4.0 21 Pdmax-Ta graph http://www.onsemi.com 5 Tuv(ms) 128 0Vcharge unavailable LC05112CMT Recommended board layout Board schematic Board size L=27.4mm W=3.1 mm H=0.8mm glass-epoxy 4layers All layer 27.4mm 3.1mm Top layer 2nd layer 3rd layer 4th layer PACK+ PACK- http://www.onsemi.com 6 LC05112CMT Note Please connect the VSS line to a pin of S1 directly. Please connect the resistance of R2 to a pin of S2 directly. It can perform the detection of the overcurrent exactly by performing these. It can get rid of influence of the wiring impedance caused by a severe electric current flowing through S1 and S2. Red line of schematic is very important line. Zoom http://www.onsemi.com 7 LC05112CMT Package Demensions unit : mm WDFN6 2.6x4.0, 0.65P, Dual Flag CASE 511BZ ISSUE O 6 5 4 PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C DIM A A3 b D D2 D3 D4 E E2 E3 e L L2 E 1 2 3 TOP VIEW A 0.10 C 8X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. PROFILE TOLERANCE APPLIES TO THE EXPOSED PADS AS WELL AS THE LEADS. A B D 0.05 C A3 SIDE VIEW NOTE 3 C GENERIC MARKING DIAGRAM* SEATING PLANE XXXXX XXXXX AYWW D2 D4 L2 D3 1 4X 3 E3 MILLIMETERS MAX MIN 0.80 0.10 0.25 0.25 0.40 2.60 BSC 2.075 2.375 1.20 1.50 0.40 0.70 4.00 BSC 2.95 3.05 2.25 2.55 0.65 BSC 0.12 0.32 0.10 XXXXX A Y WW E2 = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) 6X 6 L 4 *This information is generic. Please refer to device data sheet for actual part marking. 10X b e BOTTOM VIEW 0.10 M C A B 0.05 M C RECOMMENDED SOLDERING FOOTPRINT* 2.29 0.53 0.27 6X 0.40 2.50 4.20 PACKAGE OUTLINE 1 6X 0.40 0.65 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://www.onsemi.com 8 LC05112CMT Pin Functions Pin No. Symbol Pin Function Description 1 S2 Charger minus voltage input pin 2 CS Charger minus voltage input pin 3 TST Package trimming Termainal 4 VSS Negative power input 5 VCC VCC terminal 6 S1 7 Drain Drain of FET Exposed pad 8 Sub IC Sub (VSS) Exposed pad Connected to VSS by internal 100k resistor Negative power input Block Diagram VCC Power Control OSC Control Circuit Over- discharge D etect or Discharge Over- current D etector Level Shifter 1.2V Short- circuit Detector 1.2V Over- charge D etect or C harge O ver- current D etect or DCHG_ SW S1 VSS http://www.onsemi.com 9 CHG _SW S2 CS （Pack minus） LC05112CMT Description of operation (1) Normal mode LC05112CMT controls charging and discharging by detecting cell voltage (VCC) and controls S2-S1 current. In case that cell voltage is between over-discharge detection voltage (Vuv) and over-charge detection voltage (Vov), and S2-S1 current is between charge over-current detection current (Ioch) and discharge over-current detection current (Ioc), internal power MOS FETs as CHG_SW, DCHG_SW are all turned ON. This is the normal mode, and it is possible to be charged and discharged. (2) Over-charging mode Internal power MOS FET as CHG_SW will be turned off if cell voltage will get equal to or higher than over-charge detection voltage (Vov) over the delay time of over-charging (Tov). This is the over-charging detection mode. The recovery from over-charging will be made after the following three conditions are all satisfied. a. Charger is removed from IC. b. CS pin voltage will get equal to or higher than discharge over-current detection current (Ioc) due to load connected c. Cell voltage will get lower than over-charge release voltage (Vovr) over the delay time of over-charging release (Tovr) due to discharging through load. Consequently, internal power MOS FET as CHG_SW will be turned on and normal mode will be resumed. In over-charging mode, discharging over-current detection is made only when CS pin will get higher than discharging over-current detection current 2(Ioc2), because discharge current flows through parasitic diode of CHG_SW FET. If CS pin voltage will get higher than discharging over-current detection current 2 (Ioc2) over the delay time of discharging over-current 2 (Toc2), discharging will be shut off, because internal power FETs as DCHG_SW is turned off.(short-circuit detection mode) After detecting short-circuit, CS pin will be pulled down to Vss by internal resistor Rcsd. The recovery from short circuit detection in over-charging mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than discharging over-current detection current 2 (Ioc2) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and over-charging detection mode will be resumed. (3) Over-discharging mode If cell voltage will get lower than over-discharge detection voltage (Vuv) over the delay time of over-discharging (Tuv), discharging will be shut off, because internal power FETs as DCHG_SW is turned off. This is the over-discharging mode. After detecting over-discharging, CS pin will be pulled up to Vcc by internal resistor Rcsu and the bias of internal circuits will be shut off. (Stand-by mode) In stand-by mode, operating current is suppressed under 0.95uA (max). The recovery from stand-by mode will be made by internal circuits biased after the following two conditions are satisfied. a. Charger is connected. By continuing to be charged, if cell voltage will get higher than over-discharge detection voltage (Vuvr) over the delay time of over-discharging (Tuvr), internal power MOS FETs as DCHG_SW is turned on and normal mode will be resumed. In over-discharge detection mode, charging over-current detection does not operate. By continuing to be charged, charging over-current detection starts to operate after cell voltage goes up more than over-discharge release voltage (Vuvr). http://www.onsemi.com 10 LC05112CMT (4) Discharging over-current detection mode 1 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage will get equal to or higher than discharging over-current detection current (Ioc) over the delay time of discharging over-current (Toc1). This is the discharging over-current detection mode 1. In discharging over-current detection mode 1, CS pin will be pulled down to Vss with internal resistor Rcsd. The recovery from discharging over-current detection mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than discharging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed. (5) Discharging over-current detection mode 2 (short circuit detection) Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage will get equal to or higher than discharging over-current detection current2 (Ioc2) over the delay time of discharging over-current 2 (Toc2). This is the short circuit detection mode. In short circuit detection mode, CS pin will be pulled down to Vss by internal resistor Rcsd. The recovery from short circuit detection mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than discharging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed. (6) Charging over-current detection mode Internal power MOS FET as CHG_SW will be turned off and charging current will be shut off if CS pin voltage will get equal to or lower than charging over-current detection current (Ioch) over the delay time of charging over-current (Toch). This is the charging over-current detection mode. The recovery from charging over-current detection mode will be made after the following two conditions is satisfied. a. Charger is removed from IC and CS pin will get higher by load connected. b. CS pin voltage will get equal to or higher than charging over-current release current (Iochr) over the delay time of charging over-current release (Tocrh). Consequently, internal power MOS FET as CHG_SW will be turned on, and normal mode will be resumed. *Internal current flows out through CS and S2 terminals. After charger is removed, it flows through parasitic diode of CHG_SW FET. Therefore, CS pin voltage will go up more than charging over-current release current (Iochr). So CS pin voltage is not an indispensable condition for recovery from charging over-current detection. (7) 0V battery charge inhibition function When the battery (0 V battery) of internal short-circuit is connected, it is the function to forbid charge. When battery voltage is below typ.0.9 V, the gate of FET for charge control is fixed to the PAC-terminal voltage, and charge is forbidden. It can charge, when battery voltage is more than 0 V battery charge prohibition battery voltage (Vinh). http://www.onsemi.com 11 LC05112CMT Timing Chart Over-charge detection/release, Over-discharge detection/release (connect charger) http://www.onsemi.com 12 LC05112CMT Discharge over-current detection1, Discharge over-current detection2 (Short circuit) http://www.onsemi.com 13 LC05112CMT Charge over-current detection http://www.onsemi.com 14 LC05112CMT ORDERING INFORMATION Device LC05112C01MTTTG Package WDFN6 (2.64.0) (Pb-Free / Halogen Free) Shipping (Qty / Packing) 4000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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