LC05111CMT - ON Semiconductor

LC05111CMT
CMOS LSI
1-Cell Lithium-Ion Battery
Protection IC with integrated
Power MOS FET
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Overview
The LC05111CMT is a protection IC for 1-cell lithium-ion secondary
batteries with integrated power MOS FET. Also it integrates highly
accurate detection circuits and detection delay circuits to prevent batteries
from over-charging, over-discharging, over-current discharging and
over-current charging.
A battery protection system can be made by only LC05111CMT and few
external parts.
WDFN6 2.6x4.0, 0.65P, Dual Flag
Feature
Charge-and-discharge power MOSFET are integrated at Ta = 25C, VCC = 4.5V
ON resistance (total of charge and discharge) 11.2m (typ)
 Highly accurate detection voltage/current at Ta = 25C, VCC = 3.7V
Over-charge detection ±25mV
Over-discharge detection
±50mV
Charge over-current detection
±0.7A
Discharge over-current detection ±0.7A
 Delay time for detection and release (fixed internally)
 Discharge/Charge over-current detection is compensated for temperature dependency of power FET
 0V battery charging
: “Permission”
 Auto wake-up function battery charging
: “Permission”
 Over charge detection voltage
: 4.0V to 4.5V (5mV steps)
 Over charge release hysteresis
: 0V to 0.3V (100mV steps)
 Over discharge detection voltage
: 2.2V to 2.7V (50mV steps)
 Over discharge release hysteresis at Auto wake-up : 0V to 0.6V (200mV steps)
 Over discharge release hysteresis
: 0V to 0.075V (25mV steps)
 Discharge over current detection
: 2.0A to 8.0A (0.5A steps)
 Charge over current detection
: 8.0A to -2.0A (0.5A steps)
Typical Applications
 Lithium ion battery protection
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January 2015 - Rev. 2
1
Publication Order Number :
LC05111CMT/D
LC05111CMT
Specifications
Absolute Maximum Ratings at Ta = 25C
Symbol
Conditions
Ratings
Supply voltage
Parameter
VCC
Between PAC+ and VCC : R1=680
0.3 to +12.0
Unit
V
S1 - S2 voltage
VS1-S2
24.0
V
CS
VCC24.0
V
BAT-, PAC-
10.0
A
TST Input voltage
TST
0.3 to +7.0
V
Storage temperature
Tstg
55 to +125
C
CS terminal Input voltage
Charge or discharge current
Current between S1 and
S2(DC)
ID
VCC = 3.7V
10.0
A
Current between S1 and S2
(continuous pulse)
IDP
Pulse Width<10s, duty cycle<1%
35
A
Operating ambient temperature
Topr
40 to +85
C
450
mW
125
C
Allowable power dissipation
Pd
Junction temperature
Tj
Glass epoxy four-layer board.
Board size 27.4mm x 3.1mm x 0.8mm
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded even for a moment.
Caution 2) If you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature
change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of
decrease reliability. Please contact us for a confirmation.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Example of Application Circuit
Components
R1
R2
C1
Recommended
value
680
1k
0.1
MAX
unit
1k
2k


F
1.0
Description
* We don’t guarantee the characteristics of the circuit shown above.
* TST pin would be better to be connected to VSS pin, though it is connected to VSS with internal resistor (100k typ).
* Battery voltage drop occurs, a current of about 60uA flow period of 1.5V-1.3V.
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2
LC05111CMT
Electrical Characteristics
Parameter
Detection voltage
Symbol
Conditions
Over-charge detection voltage
Vov
R1=680
Over-charge release voltage
Vovr
R1=680
Over-discharge detection
voltage
Vuv
R1=680
Over-discharge release voltage
Vuvr
R1=680
CS=0V
Over-discharge release
voltage2
Discharge over-current
detection current
Discharge over-current
release current
Discharge over-current
detection current(Short circuit)
Charge over-current
detection current
Charge over-current
release current
Vuvr2
Ioc
Iocr
Ioc2
Ioch
Iochr
R1=680
CS=open
R2=1k
R2=1k
R2=1k
R2=1k
R2=1k
MIN.
TYP.
MAX.
25C
30 to 70C
25C
30 to 70C
25C
30 to 70C
Vov_set -25
Vov_set -30
Vovr_set -40
Vovr_set -70
Vuv_set -50
Vuv_set -80
Vov_set
Vov_set
Vovr_set
Vovr_set
Vuv_set
Vuv_set
Vov_set +25
Vov_set +30
Vovr_set +40
Vovr_set +70
Vuv_set +50
Vuv_set +80
25C
Vuvr_set -100
Vuvr_set
Vuvr_set +100
30 to 70C
Vuvr_set -120
Vuvr_set
Vuvr_set +120
25C
Vuvr2_set -100
Vuvr2_set
Vuvr2_set +100
30 to 70C
Vuvr2_set -120
Vuvr2_set
Vuvr2_set +120
25C
VCC=3.7V
Ioc_set -0.7
Ioc_set
Ioc_set +0.7
30 to 70C
VCC=2.6 to 4.3V
Ioc_set -1.2
Ioc_set
Ioc_set +1.2
25C
VCC=3.7V
(Ioc_set-0.7)
(Ioc_set)
(Ioc_set+0.7)
30 to 70C
VCC=2.6 to 4.3V
(Ioc_set-1.2)
(Ioc_set)
oc_set+1.2)
25C
VCC=3.7V
Ioc2_set*0.8
Ioc2_set
Ioc2_set*1.2
25C
VCC=3.7V
Ioch_set -0.7
Ioch_set
Ioch_set +0.7
30 to 70C
VCC=2.6 to 4.3V
Ioch_set -1.2
Ioch_set
Ioch_set +1.2
25C
VCC=3.7V
Ioch_set -0.7
Ioch_set
Ioch_set +0.7
30 to 70C
VCC=2.6 to 4.3V
Ioch_set -1.2
Ioch_set
Ioch_set +1.2
Unit
mV
mV
mV
mV
mV
A
A
A
A
A
Input voltage
Operating Voltage for 0V
charging
Vchg
VCC-CS
VCC-GND
=0V
25C
1.4
V
6
A
0.95
A
Current consumption
Operating current
Icc
Stand-by current
Istb
At normal
state
At
Stand-by
state
Auto
wake-up
=enable
25C
VCC=3.7V
25C
VCC=2.0V
3
Continued on next page.
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3
LC05111CMT
Continued from preceding page.
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
25C
10.4
13
18.2
m
25C
9.6
12
15.6
m
25C
9.2
11.6
15
m
25C
8.8
11.2
14
m
Resistance
ON resistance 1 of
integrated power MOS FET
ON resistance 2 of
integrated power MOS FET
ON resistance 3 of
integrated power MOS FET
ON resistance 4 of
integrated power MOS FET
Ron1
Ron2
Ron3
Ron4
Internal resistance (VCC-CS)
Rcsu
Internal resistance (VSS-CS)
Rcsd
VCC=3.1V
I=±2.0A
VCC=3.7V
I=±2.0A
VCC=4.0V
I=±2.0A
VCC=4.5V
I=±2.0A
VCC=Vuv
_set
CS=0V
VCC=3.7V
CS=0.1V
25C
300
k
25C
15
k
Detection and Release delay time
Over-charge detection delay
time
Tov
Over-charge release delay time
Tovr
Over-discharge detection delay
time
Tuv
Over-discharge release delay
time
Tuvr
Discharge over-current
detection delay time 1
Discharge over-current
release delay time 1
Discharge over-current
detection delay time 2 (Short
circuit)
Charge Over-current
detection delay time
Charge Over-current
release delay time
Toc1
Tocr1
Toc2
Toch
Tochr
25C
0.8
1
1.2
30 to 70C
0.6
1
1.5
25C
12.8
16
19.2
30 to 70C
9.6
16
24
25C
16
20
24
30 to 70C
12
20
30
25C
0.9
1.1
1.3
30 to 70C
0.6
1.1
1.5
25C
9.6
12
14.4
30 to 70C
7.2
12
18
25C
3.2
4
4.8
VCC=3.7V
sec
ms
ms
ms
ms
VCC=3.7V
ms
30 to 70C
2.4
4
6
25C
280
400
560
30 to 70C
180
400
800
25C
12.8
16
19.2
30 to 70C
9.6
16
24
25C
3.2
4
4.8
30 to 70C
2.4
4
6
VCC=3.7V
s
VCC=3.7V
ms
VCC=3.7V
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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4
LC05111CMT
SELECTION GUIDE
Device
Vov(V)
Vovr(V)
Vuv(V)
Vuvr(V)
Vuvr2(V)
AWUP
Ioc(A)
Ioch(A)
Ioc2(A)
0Vcharge
LC05111C01MTTTG
4.425
4.225
2.500
2.500
2.900
enable
6.00
4.00
17.5
enable
LC05111C02MTTTG
4.280
4.180
2.700
2.700
2.900
enable
6.00
3.50
21.5
enable
LC05111C03MTTTG
4.425
4.225
2.600
2.600
3.000
enable
6.00
4.00
17.5
enable
LC05111C04MTTTG
4.375
4.175
2.400
2.400
2.800
enable
6.15
6.25
17.5
enable
LC05111C05MTTTG
4.425
4.225
2.300
2.300
2.700
enable
4.00
4.00
17.5
enable
LC05111C06MTTTG
4.425
4.225
2.400
2.400
2.800
enable
6.00
4.00
17.5
enable
LC05111C07MTTTG
4.425
4.225
2.500
2.520
2.900
enable
5.00
5.00
17.5
enable
LC05111C08MTTTG
4.430
4.430
2.400
2.450
2.800
enable
5.00
5.00
17.5
enable
LC05111C09MTTTG
4.400
4.200
2.400
2.400
3.000
enable
6.00
4.00
17.5
enable
LC05111C10MTTTG
4.280
4.080
2.600
2.600
3.000
enable
6.00
4.00
17.5
enable
LC05111C11MTTTG
4.310
4.110
2.500
2.500
2.900
enable
2.00
2.00
17.5
enable
LC05111C12MTTTG
4.450
4.450
2.600
2.600
3.000
enable
4.0
3.0
15.0
enable
Pdmax-Ta graph
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5
LC05111CMT
Recommended board layout
Board schematic
Board size L=27.4mm W=3.1 mm H=0.8mm glass-epoxy 4layers
All layer
27.4mm
3.1mm
Top layer
2nd layer
3rd layer
4th layer
PACK+
PACK-
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6
LC05111CMT
Note
 Please connect the VSS line to a pin of S1 directly.
 Please connect the resistance of R2 to a pin of S2 directly.
It can perform the detection of the overcurrent exactly by performing these.
It can get rid of influence of the wiring impedance caused by a severe electric current flowing through S1 and S2.
Red line of schematic is very important line.
Zoom


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7
LC05111CMT
Package Dimensions
unit : mm
WDFN6 2.6x4.0, 0.65P, Dual Flag
CASE 511BZ
ISSUE A
6
5 4
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
DIM
A
A3
b
b2
D
D2
D3
D4
E
E1
E2
E3
e
L
L2
L3
E1 E
1
2 3
TOP VIEW
A
0.10 C
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. PROFILE TOLERANCE APPLIES TO THE
EXPOSED PADS AS WELL AS THE LEADS.
A B
D
0.05 C
A3
SIDE VIEW
NOTE 3
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
D2
4X
4X
L3
1
3
L2
b2
4X
E3
6X
XXXXX
XXXXX
AYWW
D4
D3
XXXXX
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
E2
6
L
4
6X
e
BOTTOM VIEW
MILLIMETERS
MIN
MAX
−−−
0.80
0.10
0.25
0.25
0.40
0.15
0.30
2.60 BSC
2.075
2.375
1.20
1.50
0.40
0.70
4.00 BSC
3.80 REF
2.95
3.05
2.55
2.25
0.65 BSC
0.32
0.12
−−−
0.10
−−−
0.55
b
0.10
M
C A B
0.05
M
C
RECOMMENDED
SOLDERING FOOTPRINT*
2.29
0.53
0.27
6X
0.40
2.50
4.20
PACKAGE
OUTLINE
1
0.65
PITCH
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8
6X
0.40
DIMENSION: MILLIMETERS
LC05111CMT
Pin Functions
Pin No.
Symbol
Pin Function
Description
1
S2
Charger minus voltage input pin
2
CS
Charger minus voltage input pin
3
TST
Package trimming Termainal
4
VSS
Negative power input
5
VCC
VCC terminal
6
S1
7
Drain
Drain of FET
Exposed pad
8
Sub
IC Sub (VSS)
Exposed pad
Connected to GND by internal 100k resistor
Negative power input
Block Diagram
VCC
Power
Control
OSC
Control Circuit
Over- discharge
D etect or
Discharge
Over- current
D etector
Level
Shifter
1.2V
Short- circuit
Detector
1.2V
Over- charge
D etect or
C harge
O ver- current
D etect or
DCHG_ SW
S1
VSS
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9
CHG _SW
S2 CS
（Pack minus）
LC05111CMT
(1) Normal mode
 LC05111CMT controls charging and discharging by detecting cell voltage (VCC) and controls S2-S1
current. In case that cell voltage is between over-discharge detection voltage (Vuv) and over-charge
detection voltage (Vov), and S2-S1 current is between charge over-current detection current (Ioch) and
discharge over-current detection current (Ioc), internal power MOS FETs as CHG_SW, DCHG_SW are all
turned ON.
This is the normal mode, and it is possible to be charged and discharged.
(2) Over-charging mode
 Internal power MOS FET as CHG_SW will be turned off if cell voltage will get equal to or higher than
over-charge detection voltage (Vov) over the delay time of over-charging (Tov).
This is the over-charging detection mode.
 The recovery from over-charging will be made after the following three conditions are all satisfied.
a. Charger is removed from IC.
b. Cell voltage will get lower than over-charge release voltage (Vovr) over the delay time of over-charging
release (Tovr) due to discharging through load.
Consequently, internal power MOS FET as CHG_SW will be turned on and normal mode will be resumed.
 In over-charging mode, discharging over-current detection is made only when CS pin will get higher than
discharging over-current detection current 2(Ioc2), because discharge current flows through parasitic diode
of CHG_SW FET.
If CS pin voltage will get higher than discharging over-current detection current 2 (Ioc2) over the delay time
of discharging over-current 2 (Toc2), discharging will be shut off, because internal power FETs as
DCHG_SW is turned off.(short-circuit detection mode)
After detecting short-circuit, CS pin will be pulled down to Vss by internal resistor Rcsd.
The recovery from short circuit detection in over-charging mode will be made after the following two
conditions are satisfied.
a. Load is removed from IC.
b. CS pin voltage will get equal to or lower than discharging over-current detection current 2 (Ioc2) due to CS
pin pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and over-charging detection mode
will be resumed.
(3) Over-discharging mode
 If cell voltage will get lower than over-discharge detection voltage (Vuv) over the delay time of
over-discharging (Tuv), discharging will be shut off, because internal power FETs as DCHG_SW is turned
off.
This is the over-discharging mode.
After detecting over-discharging, CS pin will be pulled up to Vcc by internal resistor Rcsu and the bias of
internal circuits will be shut off. (Stand-by mode)
In stand-by mode, operating current is suppressed under 0.95uA (max).
 The recovery from stand-by mode will be made by internal circuits biased after the following two conditions
are satisfied.
a. Charger is connected.
b. VCC level rise more than Over-discharge release voltage2(Vuvr2) without charger.(Auto wake-up function)
 If CS pin voltage will get lower than charger detecting voltage (Vchg) by connecting charger under the
condition that cell voltage is lower than over-discharge detection voltage, internal power MOS FET as
DCHG_SW is turned on and power dissipation in power MOS FETs is suppressed.
*In case that charging current is low enough, ripple current will be appeared at S2 terminal when CS pin
voltage is near by the threshold of charger detecting voltage (Vchg).
It is caused that the two modes, charger detected and charger not detected (charging through parasitic
diodes of DCHG_SW, is alternately appeared.
Continue into next page
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10
LC05111CMT
Continued from previous page
By continuing to be charged, if cell voltage will get higher than over-discharge detection voltage (Vuvr) over
the delay time of over-discharging (Tuvr), internal power MOS FETs as DCHG_SW is turned on and normal
mode will be resumed.
In over-discharge detection mode, charging over-current detection does not operate.
By continuing to be charged, charging over-current detection starts to operate after cell voltage goes up
more than over-discharge release voltage (Vuvr).
(4) Discharging over-current detection mode 1
 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin
voltage will get equal to or higher than discharging over-current detection current (Ioc) over the delay time
of discharging over-current (Toc1).
This is the discharging over-current detection mode 1.
In discharging over-current detection mode 1, CS pin will be pulled down to Vss with internal resistor Rcsd.
 The recovery from discharging over-current detection mode will be made after the following two conditions
are satisfied.
a. Load is removed from IC.
b. CS pin voltage will get equal to or lower than discharging over-current release current (Iocr) over the
delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be
resumed.
(5) Discharging over-current detection mode 2 (short circuit detection)
 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin
voltage will get equal to or higher than discharging over-current detection current2 (Ioc2) over the delay
time of discharging over-current 2 (Toc2).
This is the short circuit detection mode.
 In short circuit detection mode, CS pin will be pulled down to Vss by internal resistor Rcsd.
The recovery from short circuit detection mode will be made after the following two conditions are satisfied.
a. Load is removed from IC.
b. CS pin voltage will get equal to or lower than discharging over-current release current (Iocr) over the
delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be
resumed.
(6) Charging over-current detection mode
 Internal power MOS FET as CHG_SW will be turned off and charging current will be shut off if CS pin
voltage will get equal to or lower than charging over-current detection current (Ioch) over the delay time of
charging over-current (Toch).
This is the charging over-current detection mode.
 The recovery from charging over-current detection mode will be made after the following two conditions is
satisfied.
a. Charger is removed from IC and CS pin will get higher by load connected.
b. CS pin voltage will get equal to or higher than charging over-current release current (Iochr) over the
delay time of charging over-current release (Tocrh).
Consequently, internal power MOS FET as CHG_SW will be turned on, and normal mode will be resumed.
*Internal current flows out through CS and S2 terminals.
After charger is removed, it flows through parasitic diode of CHG_SW FET.
Therefore, CS pin voltage will go up more than charging over-current release current (Iochr).
So CS pin voltage is not an indispensable condition for recovery from charging over-current detection.
Continue into next page
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11
LC05111CMT
Continued from previous page
(7) Available Voltage for 0V charging
It is the function that the voltage of a connected battery can charge from the state that became 0V by
self-discharge. The 0V battery charge start battery charger voltage (Vchg), it fix a gate of the charge
system order FET to the VDD terminal voltage when it connect a battery charger of the above-mentioned
voltage to PAC+ terminal between PAC- terminals.
Gate-source voltage of the charge control FET becomes equal to the turn-on voltage or more due to the
charger voltage, the charging control FET.
To start charging row is turned on.
Discharge control FET is off at this time, the charge current flows through the internal parasitic diode in the
discharging control FET. It is the normal state battery voltage becomes the overdischarge release voltage
(Vuvr) or more.
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12
LC05111CMT
Timing Chart
Over-charge detection/release, Over-discharge detection/release (connect charger)
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13
LC05111CMT
Over-charge detection/release, Over-discharge detection/release (non connect charger)
Charger connection
Load
connection
Load connection
VCC
Vov
Vovr
Vuvr2
Vuv
DCHG_SW
VCC
S1
CHG_SW
VCC
S2
CS
VCC
S1
Tov
Tovr
Tuv
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14
Tuvr
LC05111CMT
Discharge over-current detection1, Discharge over-current detection2
(Short circuit)
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15
LC05111CMT
Charge over-current detection
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16
LC05111CMT
ORDERING INFORMATION
Device
LC05111C01MTTTG
Package
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
LC05111C02MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C03MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C04MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C05MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C06MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C07MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C08MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C09MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C10MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
4000 / Tape & Reel
LC05111C11MTTTG
LC05111C12MTTTG
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
WDFN6 2.6x4.0, 0.65P, Dual Flag
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
4000 / Tape & Reel
4000 / Tape & Reel
4000 / Tape & Reel
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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applicable copyright laws and is not for resale in any manner.
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