LC05132C01MT - ON Semiconductor

LC05132C01MT
CMOS LSI
1-Cell Lithium-Ion Battery
Protection IC with integrated
Power MOS FET
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Overview
The LC05132C01MT is a protection IC for 1-cell lithium-ion secondary
batteries with integrated power MOS FET. Also it integrates highly
accurate detection circuits and detection delay circuits to prevent batteries
from over-charging, over-discharging, over-current discharging and
over-current charging.
In addition, main system can execute the power-on reset of itself by turning
off the charge FET and discharge FET of LC05132C01MT for a certain
time period, with a reset signal.
A battery protection system can be made by only LC05132C01MT and few
external parts.
WDFN6 2.6x4.0, 0.65P, Dual Flag
Feature
 Charge-and-discharge power MOSFET are integrated at Ta = 25°C, VCC = 4.5V
ON resistance (total of charge and discharge ) 11.2m (typ)
 Highly accurate detection voltage/current at Ta = 25°C, VCC = 3.7V
Over-charge detection
±25mV
Over-discharge detection
±50mV
Charge over-current detection
±0.63A
Discharge over-current detection
±0.63A
 Delay time for detection and release (fixed internally)
 Discharge/Charge over-current detection is compensated for temperature dependency of power FET
 0V battery charging
: “Inhibit”
 Auto wake-up function battery charging
: “Inhibit”
 Over charge detection voltage
: 4.0V to 4.525V (5mV steps)
 Over charge release hysteresis
: 0V to 0.3V (100mV steps)
 Over discharge detection voltage
: 2.2V to 2.8V (50mV steps)
 Over discharge release hysteresis
: 0V to 0.075V (25mV steps)
 Forcible charge-FET and discharge-FET OFF mode
RSTB>VDD*0.8: Charge-FET and Discharge-FET=ON
RSTB<VDD*0.2: Charge-FET and Discharge-FET=OFF
Typical Applications
 Smart phone
 Tablet
 Wearable device
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
February 2015 - Rev. 2
1
Publication Order Number :
LC05132C01MT/D
LC05132C01MT
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VCC
Between PAC+ and VCC : R1=680
0.3 to 12.0
V
S1 - S2 voltage
VS1-S2
24.0
V
CS terminal Input voltage
CS
VCC24.0 to VCC+0.3
V
Charge or discharge current
BAT, PAC
10.0
A
RSTB Input voltage
RSTB
0.3 to 7
V
Storage temperature
Tstg
55 to +125
C
Current between S1 and S2(DC)
ID
VCC = 3.7V
10.0
A
IDP
Pulse Width<10us, duty cycle<1%
35
A
Current between S1 and S2
(continuous pulse)
Operating ambient temperature
Topr
Allowable power dissipation
Pd
Junction temperature
Tj
40 to +100
C
450
mW
125
C
Glass epoxy four-layer board
Board size L=38.7mm W=4.4mm H=1.6mm
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded at any given time.
Caution 2) If you intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within
the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for confirmation.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Example of Application Circuit
PAC+
R1
VCC
VCC
RSTB
R3
RSTB
Controller IC
Battery
C1
VSS
S1
S2
CS
R2
PAC-
Components
Recommended value
MAX
unit
R1
680
1k

R2
1k
2k

R3
1k
2k

C1
1.0µ
-
F
Description
* We don’t guarantee the characteristics of the circuit shown above.
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LC05132C01MT
Electrical Characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Detection voltage
Over-charge detection voltage
Vov
R1=680
Over-charge release voltage
Vovr
R1=680
Over-discharge detection voltage
Vuv
R1=680
Over-discharge release voltage
Vuvr
R1=680
CS=0V
Discharge over-current
detection current
Discharge over-current
release current
Discharge over-current
detection currnt2 (Short circuit)
Charge over-current
detection current
Charge over-current
release current
Reset terminal
High−Level
Input Voltage
Low−Level
Input Voltage
High−Level Input
Leakage Current
Ta=25°C
4.45
4.475
4.5
Ta=30 to 70°C
Ta=25°C
4.445
4.435
4.475
4.475
4.505
4.5
Ta=30 to 70°C
4.405
4.475
4.505
V
V
Ta=25°C
2.150
2.200
2.250
Ta=30 to 70°C
Ta=25°C
Ta=30 to 70°C
2.120
2.150
2.120
2.200
2.200
2.200
2.280
2.300
2.320
Ta=25°C
VCC=3.7V
5.67
6.3
6.93
Ta=20 to 60°C
VCC=2.6 to 4.3V
5.29
6.3
7.31
Ta=30 to 70°C
VCC=2.6 to 4.3V
5.22
6.3
7.38
Ta=25°C
VCC=3.7V
5.66
6.3
6.92
Ta=20 to 60°C
VCC=2.6 to 4.3V
5.28
6.3
7.30
Ta=30 to 70°C
VCC=2.6 to 4.3V
5.21
6.3
7.37
Ta=25°C
VCC=3.7V
14.8
17.5
21
Ta=30 to 70°C
VCC=2.6 to 4.3V
10.4
17.5
30
Ta=25°C
VCC=3.7V
4.57
5.2
5.83
Ta=20 to 60°C
VCC=2.6 to 4.3V
4.35
5.2
6.21
Ta=30 to 90°C
VCC=2.6 to 4.3V
4.2
5.2
6.28
Ta=25°C
VCC=3.7V
4.56
5.2
5.82
Ta=20 to 60°C
VCC=2.6 to 4.3V
4.34
5.2
6.20
Ta=30 to 90°C
VCC=2.6 to 4.3V
4.19
5.2
6.27
VIH
Ta=30 to 90°C
0.9*VCC
VIL
Ta=30 to 90°C
0.1*VCC
V
1
µA
Ioc
Iocr1
Ioc2
Ioch
Iochr
R2=1k
R2=1k
R2=1k
R2=1k
R2=1k
V
V
A
A
A
A
A
V
IIH
VCC=RSTB
Ta=30 to 90°C
Low−Level Input
Leakage Current
IIL
VCC=3.7V
RSTB=0V
Ta=30 to 90°C
20
34
48
µA
Reset pulse width
Tw_res
VCC=2.2 to 4.3V
Ta=30 to 90°C
10
20
30
ms
Input voltage
0V battery charging inhibition battery
voltage
Current consumption
Vinh
Ta=25°C
0.4
0.9
1.4
V
Operating current
Icc
At normal
state
Ta=25°C
VCC=3.7V
3
6
µA
Shut down current
Ishut
At shut down
state
Ta=25°C
VCC=2.0V
0.1
µA
Continued on next page.
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3
LC05132C01MT
Continued from preceding page.
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Ta=25°C
10.4
13
18.2
m
Ta=25°C
9.6
12
15.6
m
Ta=25°C
9.2
11.6
15
m
Ta=25°C
8.8
11.2
14
m
Resistance
ON resistance 1 of
VCC=3.1V
Ron1
integrated power MOS FET
I=±2.0A
ON resistance 2 of
VCC=3.7V
Ron2
integrated power MOS FET
I=±2.0A
ON resistance 3 of
VCC=4.0V
Ron3
integrated power MOS FET
I=±2.0A
ON resistance 4 of
VCC=4.5V
Ron4
integrated power MOS FET
I=±2.0A
Internal resistance (VCC-CS)
Rcsu
VCC=Vuv_set
CS=0V
Ta=25°C
300
k
Internal resistance (VSS-CS)
Rcsd
VCC=3.7V
CS=0.1V
Ta=25°C
15
k
Detection and Release delay time
Over-charge detection delay time
Tov
Over-charge release delay time
Tovr
Over-discharge detection delay time
Tuv
Over-discharge release delay time
Tuvr
Discharge over-current
detection delay time 1
Toc1
Discharge over-current
release delay time 1
Tocr1
Discharge over-current
detection delay time 2 (Short circuit)
Toc2
Charge Over-current
detection delay time
Toch
Charge Over-current
release delay time
Tochr
Reset release time
Tres
Ta=25°C
0.8
1
1.2
Ta=30 to 70°C
0.6
1
1.5
Ta=25°C
12.8
16
19.2
Ta=30 to 70°C
9.6
16
24
Ta=25°C
14
20
26
Ta=30 to 70°C
12
20
30
Ta=25°C
0.9
1.1
1.3
Ta=30 to 70°C
0.6
1.1
1.5
Ta=25°C
9.6
12
14.4
Ta=30 to 70°C
7.2
12
18
Ta=25°C
3.2
4
4.8
Ta=30 to 70°C
2.4
4
6
Ta=25°C
130
200
320
Ta=30 to 70°C
100
200
350
Ta=25°C
12.8
16
19.2
Ta=30 to 90°C
9.6
16
24
Ta=25°C
3.2
4
4.8
Ta=-30 to 90°C
2.4
4
6
Ta=25°C
4
5
6
Ta=30 to 70°C
3
5
7.5
VCC=3.7V
sec
ms
ms
ms
ms
VCC=3.7V
ms
VCC=3.7V
us
VCC=3.7V
ms
VCC=3.7V
ms
VCC=3.7V
s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC05132C01MT
Recommended board layout
Board schematic
PAC+
R1
VCC
VCC
RSTB
R3 RSTB
Controller IC
Battery
C1
C2
(option)
VSS
S1
S2
C5
(option)
CS
R2
C3
C4
(option) (option)
PAC-
Board size L=38.7mm W=4.4mm H=1.6mm glass-epoxy 4layers
All layers
38.7mm
4.4
mm
Top layer
2nd layer
3rd layer
Bottom layer
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LC05132C01MT
Note
<1> Please connect the VSS line to a pin of S1 directly.
<2> Please connect the resistance of R2 to a pin of S2 directly.
It can perform the detection of the overcurrent exactly by performing these.
It can get rid of influence of the wiring impedance caused by a severe electric current flowing through S1 and S2.
Red line of schematic is very important line.
<2>
Zoom
<1>
Pdmax-Ta graph
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LC05132C01MT
Package Dimensions
unit : mm
WDFN6 2.6x4.0, 0.65P, Dual Flag
CASE 511BZ
ISSUE A
6
5 4
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
DIM
A
A3
b
b2
D
D2
D3
D4
E
E1
E2
E3
e
L
L2
L3
E1 E
1
2 3
TOP VIEW
A
0.10 C
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. PROFILE TOLERANCE APPLIES TO THE
EXPOSED PADS AS WELL AS THE LEADS.
A B
D
0.05 C
A3
SIDE VIEW
NOTE 3
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
D2
4X
4X
L3
1
3
L2
b2
4X
E3
6X
XXXXX
XXXXX
AYWW
D4
D3
XXXXX
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
E2
6
L
4
6X
e
BOTTOM VIEW
MILLIMETERS
MIN
MAX
−−−
0.80
0.10
0.25
0.25
0.40
0.15
0.30
2.60 BSC
2.075
2.375
1.20
1.50
0.40
0.70
4.00 BSC
3.80 REF
2.95
3.05
2.55
2.25
0.65 BSC
0.32
0.12
−−−
0.10
−−−
0.55
b
0.10
M
C A B
0.05
M
C
RECOMMENDED
SOLDERING FOOTPRINT*
2.29
0.53
0.27
6X
0.40
2.50
4.20
PACKAGE
OUTLINE
1
0.65
PITCH
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7
6X
0.40
DIMENSION: MILLIMETERS
LC05132C01MT
Pin Functions
Pin No.
Symbol
Pin Function
Description
1
S2
Charger minus voltage input pin
2
CS
Charger minus voltage input pin
3
RSTB
4
VSS
Negative power input
5
VCC
VCC terminal
6
S1
7
Drain
Drain of FET
Exposed pad (wide)
8
Sub
IC Sub (VSS)
Exposed pad
Charge and discharge off control terminal
( “L” = Reset )
Connected to VCC with 100k
Negative power input
Block Diagram
RSTB
VCC
100kohm
Power
Control
OSC
Control Circuit
Over- discharge
D etector
Discharge
O ver - current
D etector
Level
Shifter
1.2V
Short - circuit
Dete ctor
1.2V
Over- charge
D etector
C harge
O ver- current
D etector
DCHG _ SW
S1
VSS
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8
CHG _ SW
S2 CS
（ Pack minus）
LC05132C01MT
Description of operation
(1)Normal mode
LC05132C01MT controls charging and discharging by detecting cell voltage (VCC) and controls S2-S1 current. In
case that cell voltage is between over-discharge detection voltage (Vuv) and over-charge detection voltage (Vov), and
S2-S1 current is between charge over-current detection current (Ioch) and discharge over-current detection current
(Ioc), internal power MOS FETs as CHG_SW, DCHG_SW are both turned ON.
This is the normal mode, and it is possible to be charged and discharged.
(2)Over-charging mode
Internal poer MOS FETCHG_SW turns off if cell voltage becomes greater than or equal to over-charge detection
voltage (Vov) over the delay time of over-charging (Tov).
This is the over-charging detection mode.
The recovery from over-charging will be made after the following two conditions are satisfied.
1. Charger is removed from IC.
2. Cell voltage decreases under over-charge release voltage (Vovr) over the delay time of over-charging releasing
(Tovr) due to discharging through a load.
Consequently, internal power MOS FET as CHG_SW will be turned on and normal mode will be resumed.
In over-charging mode, discharging over-current detection is made only when CS pin increases more than discharging
over-current detection current 2(Ioc2), because discharge current flows through parasitic diode of CHG_SW FET.
If CS pin voltage increases more than discharging over-current detection current 2 (Ioc2) over the delay time of
discharging over-current 2 (Toc2), discharging will be shut off, because internal power FETs as DCHG_SW is turned
off. (short-circuit detection mode)
After detecting short-circuit, CS pin will be pulled down to Vss by internal resistor Rcsd.
The recovery from short circuit detection in over-charging mode will be made after the following two conditions are
satisfied.
1. Load is removed from IC.
2. CS pin voltage becomes less than or equal to discharging over-current detection current 2 (Ioc2) due to CS pin
pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and over-charging detection mode will be
resumed.
(3)Over-discharging mode
If cell voltage drops lower than over-discharge detection voltage (Vuv) over the delay time of over-discharging (Tuv),
discharging will be shut off, internal power FETs as DCHG_SW is turned off.
This is the over-discharging mode.
After detecting over-discharging, CS pin will be pulled up to Vcc by an internal resistor Rcsu and the bias of internal
circuits will be shut off. (Shut-down mode)
In shut-down mode, operating current is suppressed under 0.1uA (max).
The recovery from stand-by mode will be made by internal circuits biased after the connecting charger.
By continuing to be charged, if cell voltage increases more than over-discharge detection voltage (Vuvr) over the delay
time of over-discharging (Tuvr), internal power MOS FETs as DCHG_SW is turned on and normal mode will be
resumed.
In over-discharge detection mode, charging over-current detection does not operate.
By continuing to be charged, charging over-current detection starts to operate after cell voltage goes up more than
over-discharge release voltage (Vuvr).
(4)Discharging over-current detection mode 1
Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage
becomes greater than or equal to discharging over-current detection current (Ioc) over the delay time of discharging
over-current (Toc1).
This is the discharging over-current detection mode 1.
In discharging over-current detection mode 1, CS pin will be pulled down to Vss with internal resistor Rcsd.
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LC05132C01MT
The recovery from discharging over-current detection mode will be made after the following two conditions are
satisfied.
1. Load is removed from IC.
2. CS pin voltage becomes less than or equal to discharging over-current release current (Iocr) over the delay time of
discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed.
(5)Discharging over-current detection mode 2 (short circuit detection)
 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage
becomes greater than or equal to discharging over-current detection current2 (Ioc2) over the delay time of discharging
over-current 2 (Toc2).
This is the short circuit detection mode.
 In short circuit detection mode, CS pin will be pulled down to Vss by internal resistor Rcsd.
The recovery from short circuit detection mode will be made after the following two conditions are satisfied.
a. Load is removed from IC.
b. CS pin voltage becomes less than or equal to discharging over-current release current (Iocr) over the delay time of
discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed.
(6)Charging over-current detection mode
 Internal power MOS FET as CHG_SW will be turned off and charging current will be shut off if CS pin voltage
becomes less than or equal to charging over-current detection current (Ioch) over the delay time of charging
over-current (Toch).
This is the charging over-current detection mode.
 The recoveries from charging over-current detection mode will be made after the following two conditions are
satisfied.
1. Charger is removed from IC and CS pin will increase by load connection.
2. CS pin voltage becomes greater than or equal to charging over-current release current (Iochr) over the delay time of
charging over-current release (Tocrh).
Consequently, internal power MOS FET as CHG_SW will be turned on, and normal mode will be resumed.
*Internal current flows out through CS and S2 terminals.
After charger is removed, it flows through parasitic diode of CHG_SW FET.
Therefore, CS pin voltage will go up more than charging over-current release current (Iochr).
So CS pin voltage is not an indispensable condition for recovery from charging over-current detection.
(7) 0V Battery Protection Function
This function protects the battery when a short circuit in the battery (0V battery) is detected, at which point charging
will be prohibited.
When the voltage of a battery is below 1.4V (max), the gate of the charging control FET is fixed to the
PAC-Terminal voltage, at which point charging will be prohibited.
If the voltage of the battery is greater than the 0V battery prohibit voltage (Vinh), charging will be enabled.
(8)Reset mode
In case of normal mode, internal power MOS FET as CHG_SW and DCHG_SW will be turned off and charging and
discharging current will be shut off if RSTB pin voltage becomes less than or equal to low-level input voltage (VIL)
over the delay time of reset pulse width(Tw_res).
This is the reset mode.
The recovery from reset mode will be made itself after the reset release time (Tres).
Consequently, internal power MOS FET as CHG_SW and DCHG_SW will be turned on, and normal mode will be
resumed.
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LC05132C01MT
Timing Chart
Over-charge detection/release, Over-discharge detection/release (Connect charger)
Charger
connection
Load
connection
Charger
connection
VCC
Vov
Vovr
Vuv/Vuvr
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Tov
Tovr
Tuv
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11
Tuvr
LC05132C01MT
Over-charge detection/release, Over-discharge detection/release (Non-connect charger)
Charger connection
Load connection
VCC
Vov
Vovr
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Tov
Tovr
Tuv
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12
LC05132C01MT
Discharge over-current detection1, Discharge over-current detection2
(Short circuit)
Load connection
Load connection
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Discharge
Current
Ioc
Toc1
Toc2
Tocr1
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13
Tocr1
LC05132C01MT
Charge over-current detection
Charger
connection
Load connection
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Charge/Discharge
Current
0
Ioch
Toch
Tochr
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14
LC05132C01MT
Reset function
Load connection
Load connection
RSTB
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
Discharge
Current
Tw_res
Tres
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15
LC05132C01MT
ORDERING INFORMATION
Device
LC05132C01MTTTG
Package
WDFN6 (2.6×4.0)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
4000 / Tape & Reel
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and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
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further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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