NCP4305 Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies The NCP4305 is high performance driver tailored to control a synchronous rectification MOSFET in switch mode power supplies. Thanks to its high performance drivers and versatility, it can be used in various topologies such as DCM or CCM flyback, quasi resonant flyback, forward and half bridge resonant LLC. The combination of externally adjustable minimum off-time and on-time blanking periods helps to fight the ringing induced by the PCB layout and other parasitic elements. A reliable and noise less operation of the SR system is insured due to the Self Synchronization feature. The NCP4305 also utilizes Kelvin connection of the driver to the MOSFET to achieve high efficiency operation at full load and utilizes a light load detection architecture to achieve high efficiency at light load. The precise turn−off threshold, extremely low turn−off delay time and high sink current capability of the driver allow the maximum synchronous rectification MOSFET conduction time and enables maximum SMPS efficiency. The high accuracy driver and 5 V gate clamp enables the use of GaN FETs. www.onsemi.com MARKING DIAGRAMS 8 1 SOIC−8 D SUFFIX CASE 751 8 NCP4305x ALYW G G 1 1 DFN8 MN SUFFIX CASE 488AF 4305x ALYWG G 1 Features • Self−Contained Control of Synchronous Rectifier in CCM, DCM and • • • • • • • • • • • • • • • • • WDFN8 MT SUFFIX CASE 511AT 5xMG G QR for Flyback, Forward or LLC Applications Precise True Secondary Zero Current Detection 4305x = Specific Device Code Typically 12 ns Turn off Delay from Current Sense Input to Driver x = A, B, C, D or Q Rugged Current Sense Pin (up to 200 V) A = Assembly Location L = Wafer Lot Ultrafast Turn−off Trigger Interface/Disable Input (7.5 ns) Y = Year Adjustable Minimum ON−Time W = Work Week M = Date Code Adjustable Minimum OFF-Time with Ringing Detection G = Pb−Free Package Adjustable Maximum ON−Time for CCM Controlling of Primary (Note: Microdot may be in either location) QR Controller Improved Robust Self Synchronization Capability ORDERING INFORMATION 8 A / 4 A Peak Current Sink / Source Drive Capability See detailed ordering and shipping information on page 49 of Operating Voltage Range up to VCC = 35 V this data sheet. Automatic Light−load & Disable Mode Typical Applications Adaptive Gate Drive Clamp • Notebook Adapters GaN Transistor Driving Capability (options A and C) • High Power Density AC/DC Power Supplies (Cell Low Startup and Disable Current Consumption Phone Chargers) Maximum Operation Frequency up to 1 MHz • LCD TVs SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages • All SMPS with High Efficiency Requirements These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 1 1 Publication Order Number: NCP4305/D NCP4305 Figure 1. Typical Application Example − LLC Converter with Optional LLD and Trigger Utilization Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter with optional LLD and Disabled TRIG www.onsemi.com 2 NCP4305 Figure 3. Typical Application Example − Primary Side Flyback Converter with optional LLD and Disabled TRIG Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy Loads utilizing MAX−TON www.onsemi.com 3 NCP4305 PIN FUNCTION DESCRIPTION ver. A, B, C, D ver. Q Pin Name 1 1 VCC 2 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground. 3 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground. 4 4 LLD This input modulates the driver clamp level and/or turns the driver off during light load conditions. 5 − TRIG/DIS Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applications in order to improve efficiency. Activates disable mode if pulled−up for more than 100 ms. 6 6 CS Current sense pin detects if the current flows through the SR MOSFET and/or its body diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can decrease the turn off threshold if needed. 7 7 GND Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground connection for minimum on and off time adjust resistors, LLD and trigger inputs. GND pin should be wired directly to the SR MOSFET source terminal/soldering point using Kelvin connection. DFN8 exposed flag should be connected to GND 8 8 DRV Driver output for the SR MOSFET − 5 MAX_TON MIN_TON Description Supply voltage pin Adjust the maximum on time period by connecting resistor to ground. ELAPSED ADJ DISABLE Minimum ON time generator EN Disable detection & V DRV clamp modulation LLD V_DRV control VDD 100mA CS CS_ON CS detection DRIVER CS_OFF DRV Out DRV Control logic CS_RESET V DD RESET MIN_TOFF ADJ Minimum OFF time generator ELAPSED DISABLE EN TRIG TRIG/ DISABLE Vtrig Figure 5. Internal Circuit Architecture − NCP4305A, B, C, D www.onsemi.com 4 VCC DISABLE Disable detection 10 A VCC managment UVLO GND NCP4305 ELAPSED MIN_TON ADJ DISABLE Minimum ON time generator EN Disable detection & V DRV clamp modulation LLD V_DRV control VDD 100mA CS CS_ON CS detection DRIVER DRV Out DRV CS_OFF Control logic CS_RESET VDD RESET MIN_TOFF ADJ Minimum OFF time generator ELAPSED EN DISABLE VCC managment UVLO VCC ELAPSED MAX_TON ADJ Maximum ON time generator GND EN Figure 6. Internal Circuit Architecture − NCP4305Q (CCM QR) with MAX_TON www.onsemi.com 5 NCP4305 ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC −0.3 to 37.0 V VTRIG/DIS, VMIN_TON, VMIN_TOFF, VMAX_TON, VLLD −0.3 to VCC V Driver Output Voltage VDRV −0.3 to 17.0 V Current Sense Input Voltage VCS −4 to 200 V Supply Voltage TRIG/DIS, MIN_TON, MIN_TOFF, MAX_TON, LLD Input Voltage Current Sense Dynamic Input Voltage (tPW = 200 ns) MIN_TON, MIN_TOFF, MAX_TON, LLD, TRIG Input Current VCS_DYN −10 to 200 V IMIN_TON, IMIN_TOFF, IMAX_TON, ILLD, ITRIG −10 to 10 mA RqJ−A_SOIC8 160 °C/W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 RqJ−A_DFN8 80 °C/W RqJ−A_WDFN8 160 °C/W Maximum Junction Temperature TJMAX 150 °C Storage Temperature TSTG −60 to 150 °C ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E ESDHBM 2000 V ESD Capability, Human Body Model, Pin 6, per JESD22−A114E ESDHBM 1000 V ESD Capability, Machine Model, per JESD22−A115−A ESDMM 200 V ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F ESDCDM 750 V ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F ESDCDM 250 V Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, DFN8 Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Maximum Operating Input Voltage Min VCC Operating Junction Temperature TJ −40 Max Unit 35 V 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C Parameter Test Conditions Symbol Min Typ Max Unit VCC rising VCCON 8.3 8.8 9.3 V VCC falling VCCOFF 7.3 7.8 8.3 SUPPLY SECTION VCC UVLO (ver. B & C) VCC UVLO Hysteresis (ver. B & C) VCC UVLO (ver. A, D & Q) VCCHYS V VCC rising VCCON 4.20 4.45 4.70 VCC falling VCCOFF 3.70 3.95 4.20 VCC UVLO Hysteresis (ver. A, D & Q) Start−up Delay 1.0 VCC rising from 0 to VCCON + 1 V @ tr = 10 ms www.onsemi.com 6 VCCHYS 0.5 tSTART_DEL 75 V V 125 ms NCP4305 ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C Parameter Test Conditions Symbol Min Typ Max Unit ICC 3.3 4.0 5.6 mA B, D, Q 3.8 4.5 6.0 A, C 4.5 6.0 7.5 B, D, Q 7.7 9.0 10.7 A, C 20 25 30 SUPPLY SECTION Current Consumption, RMIN_TON = RMIN_TOFF = 0 kW CLOAD = 0 nF, fSW = 500 kHz A, C CLOAD = 1 nF, fSW = 500 kHz CLOAD = 10 nF, fSW = 500 kHz B, D, Q Current Consumption No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF =0k ICC Current Consumption below UVLO No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V ICC_UVLO Current Consumption in Disable Mode VLLD = VCC − 0.1 V, VCS = 0 V ICC_DIS VTRIG = 5 V, VLLD = VCC – 3 V, VCS = 0 V 40 50 60 1.5 2.0 2.5 mA 75 125 mA 40 55 70 mA 45 65 80 40 55 ns 35 ns DRIVER OUTPUT Output Voltage Rise−Time CLOAD = 10 nF, 10% to 90% VDRVMAX Output Voltage Fall−Time CLOAD = 10 nF, 90% to 10% VDRVMAX Driver Source Resistance Driver Sink Resistance Output Peak Source Current Output Peak Sink Current Maximum Driver Output Voltage VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V, (ver. B, D and Q) tr tf 20 RDRV_SOURCE 1.2 W RDRV_SINK 0.5 W IDRV_SOURCE 4 A IDRV_SINK 8 A VDRVMAX VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V, (ver. A, C) Minimum Driver Output Voltage VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. B) VDRVMIN 9.5 10.5 4.3 4.7 5.5 V V 7.2 7.8 8.5 VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. C) 4.2 4.7 5.3 VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. A) 3.6 4.0 4.4 3.8 4.0 4.4 0.0 0.4 1.2 V VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. D, Q) Minimum Driver Output Voltage 9.0 VLLD = VCC − VLLDREC V VDRVLLDMIN CS INPUT Total Propagation Delay From CS to DRV Output On VCS goes down from 4 to −1 V, tf_CS = 5 ns tPD_ON 35 60 ns Total Propagation Delay From CS to DRV Output Off VCS goes up from −1 to 4 V, tr_CS = 5 ns tPD_OFF 12 23 ns CS Bias Current VCS = −20 mV Turn On CS Threshold Voltage Turn Off CS Threshold Voltage Guaranteed by Design Turn Off Timer Reset Threshold Voltage CS Leakage Current ICS −105 −100 −95 mA −75 −40 mV 0 mV 0.54 V VTH_CS_ON −120 VTH_CS_OFF −1 VTH_CS_RESET 0.42 0.48 VCS = 200 V ICS_LEAKAGE 0.4 mA VTRIG = 5 V; Shorter pulses may not be proceeded tTRIG_PW_MIN 10 ns TRIGGER DISABLE INPUT Minimum Trigger Pulse Duration Trigger Threshold Voltage VTRIG_TH Trigger to DRV Propagation Delay VTRIG goes from 0 to 5 V, tr_TRIG = 5 ns Trigger Blank Time After DRV Turn−on Event VCS drops below VTH_CS_ON tTRIG_BLANK www.onsemi.com 7 1.95 tPD_TRIG 35 2.02 2.15 V 7.5 12.5 ns 50 65 ns NCP4305 ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C Parameter Test Conditions Symbol Min Typ Max Unit TRIGGER DISABLE INPUT Delay to Disable Mode VTRIG = 5 V tDIS_TIM 85 100 115 ms Disable Recovery Timer VTRIG goes down from 5 to 0 V tDIS_REC 6 8 10 ms 200 ns Minimum Pulse Duration to Disable VTRIG = 0 V; Shorter pulses may not be Mode End proceeded Pull Down Current tDIS_END_MIN VTRIG = 5 V ITRIG 9 13 16 mA MINIMUM tON and tOFF ADJUST Minimum tON time RMIN_TON = 0 W tON_MIN 35 55 75 ns Minimum tOFF time RMIN_TOFF = 0 W tOFF_MIN 190 245 290 ns Minimum tON time RMIN_TON = 10 kW tON_MIN 0.92 1.00 1.08 ms Minimum tOFF time RMIN_TOFF = 10 kW tOFF_MIN 0.92 1.00 1.08 ms Minimum tON time RMIN_TON = 50 kW tON_MIN 4.62 5.00 5.38 ms Minimum tOFF time RMIN_TOFF = 50 kW tOFF_MIN 4.62 5.00 5.38 ms Maximum tON Time VMAX_TON = 3 V tON_MAX 4.3 4.8 5.3 ms Maximum tON Time VMAX_TON = 0.3 V tON_MAX 41 48 55 ms Maximum tON Output Current VMAX_TON = 0.3 V IMAX_TON −105 −100 −95 mA Disable Threshold VLLD_DIS = VCC − VLLD VLLD_DIS 0.8 0.9 1.0 V Recovery Threshold VLLD_REC = VCC − VLLD VLLD_REC 0.9 1.0 1.1 V MAXIMUM tON ADJUST LLD INPUT Disable Hysteresis Disable Time Hysteresis Disable to Normal, Normal to Disable Disable Recovery Time 0.1 V tLLD_DISH 45 ms tLLD_DIS_REC 9.0 fLPLLD 6 Low Pass Filter Frequency Driver Voltage Clamp Threshold VLLD_DISH VDRV = VDRVMAX, VLLDMAX = VCC − VLLD VLLDMAX 12.5 15.0 ms 10 13 kHz 2.0 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. TYPICAL CHARACTERISTICS 9.3 4.7 4.6 9.1 VCCON 4.4 8.7 4.3 8.5 4.2 4.1 VCCOFF 4.0 VCCON 8.9 VCC (V) VCC (V) 4.5 8.3 8.1 VCCOFF 7.9 3.9 7.7 3.8 7.5 7.3 −40 −20 3.7 −40 −20 0 20 40 60 TJ (°C) 80 100 120 Figure 7. VCCON and VCCOFF Levels, ver. A, D, Q 0 20 40 60 TJ (°C) 80 100 Figure 8. VCCON and VCCOFF Levels, ver. B, C www.onsemi.com 8 120 NCP4305 TYPICAL CHARACTERISTICS 6 TJ = 55°C TJ = 25°C 120 TJ = 85°C TJ = 125°C 5 100 ICC_UVLO (mA) ICC (mA) 4 TJ = 0°C 3 TJ = −20°C TJ = −40°C 2 1 80 60 40 20 0 0 5 10 15 20 25 30 0 −40 35 −20 0 20 80 100 TJ (°C) Figure 9. Current Consumption, CDRV = 0 nF, fCS = 500 kHz, ver. D Figure 10. Current Consumption, VCC = VCCOFF − 0.1 V, VCS = 0 V, ver. D 120 60 CDRV = 10 nF CDRV = 10 nF 25 50 20 40 ICC (mA) ICC (mA) 60 VCC (V) 30 15 10 30 20 CDRV = 1 nF 5 CDRV = 1 nF 10 CDRV = 0 nF CDRV = 0 nF 0 −40 −20 0 20 40 60 80 100 0 −40 −20 120 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 11. Current Consumption, VCC = 12 V, VCS = −1 to 4 V, fCS = 500 kHz, ver. A Figure 12. Current Consumption, VCC = 12 V, VCS = −1 to 4 V, fCS = 500 kHz, ver. D 70 80 65 75 70 60 ICC_DIS (mA) ICC_DIS (mA) 40 55 50 60 55 45 40 −40 65 50 −20 0 20 40 60 80 100 45 −40 120 −20 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 13. Current Consumption in Disable, VCC = 12 V, VCS = 0 V, VLLD = VCC − 0.1 V Figure 14. Current Consumption in Disable, VCC = 12 V, VCS = 0 V, VLLD = VCC − 3 V, VTRIG = 5V www.onsemi.com 9 NCP4305 TYPICAL CHARACTERISTICS 0 −90 −92 −0.2 −94 −0.4 −98 ICS (mA) ICS (mA) −96 −100 −102 −104 TJ = 125°C TJ = 85°C TJ = 55°C TJ = 25°C TJ = 0°C TJ = −20°C TJ = −40°C −0.6 −0.8 −1.0 −106 −108 −110 −40 −1.2 −20 0 20 40 60 80 100 −1.4 −1.0 −0.8 −0.6 −0.4 −0.2 120 0.4 0.6 VCS (V) Figure 15. CS Current, VCS = −20 mV Figure 16. CS Current, VCC = 12 V 2.5 −50 VTH_CS_ON (mV) −30 2.0 ICC (mA) 0.2 TJ (°C) 3.0 TJ = 125°C TJ = 85°C TJ = 55°C TJ = 25°C TJ = 0°C TJ = −20°C TJ = −40°C 1.5 1.0 0.5 0 −4 0 −3 −2 0.8 1.0 −70 −90 −110 −130 −1 0 1 2 3 −150 −40 −20 4 0 20 40 60 80 100 VCS (V) TJ (°C) Figure 17. Supply Current vs. CS Voltage, VCC = 12 V Figure 18. CS Turn−on Threshold 1.0 120 0.60 VTH_CS_RESET (V) VTH_CS_OFF (mV) 0.5 0 −0.5 −1.0 0.55 0.50 0.45 −1.5 −2.0 −40 −20 0 20 40 60 80 100 0.40 −40 120 −20 0 20 40 60 80 TJ (°C) TJ (°C) Figure 19. CS Turn−off Threshold Figure 20. CS Reset Threshold www.onsemi.com 10 100 120 NCP4305 0.80 200 0.75 180 0.70 160 0.65 140 ICS_LEAKAGE (nA) VTH_CS_RESET (V) TYPICAL CHARACTERISTICS 0.60 0.55 0.50 0.45 100 80 60 0.40 40 0.35 0.30 20 0 −40 0 5 10 15 20 25 30 35 −20 0 20 40 60 80 100 VCC (V) TJ (°C) Figure 21. CS Reset Threshold Figure 22. CS Leakage, VCS = 200 V 60 24 55 22 120 20 50 18 tPD_OFF (ns) tPD_ON (ns) 120 45 40 35 16 14 12 10 30 8 25 6 20 −40 −20 0 20 40 60 80 100 4 −40 120 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 23. Propagation Delay from CS to DRV Output On Figure 24. Propagation Delay from CS to DRV Output Off 2.5 2.15 2.13 2.4 2.11 2.3 2.09 2.2 VTRIG_TH (V) VTRIG_TH (V) −20 2.07 2.05 2.03 2.1 2.0 1.9 2.01 1.8 1.99 1.7 1.97 1.6 1.5 1.95 −40 −20 0 20 40 60 80 100 120 TJ = 125°C TJ = 85°C TJ = 55°C TJ = 25°C 0 5 10 15 20 TJ = 0°C TJ = −20°C TJ = −40°C 25 TJ (°C) VCC (V) Figure 25. Trigger Threshold, VCC = 12 V Figure 26. Trigger Threshold www.onsemi.com 11 30 35 NCP4305 16 14 15 12 14 10 ITRIG (mA) ITRIG (mA) TYPICAL CHARACTERISTICS 13 12 4 10 2 TJ = 125°C TJ = 85°C TJ = 55°C TJ = 25°C TJ = 0°C TJ = −20°C TJ = −40°C 0 −20 0 20 40 60 80 100 0 120 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TJ (°C) VTRIG (V) Figure 27. Trigger Pull Down Current Figure 28. Trigger Pull Down Current, VCC = 12 V 14 115 12 110 10 105 tDIS_TIM (ms) tPD_TRIG (ns) 6 11 9 −40 8 6 100 95 90 4 2 −40 −20 0 20 40 60 80 100 85 −40 −20 120 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 29. Propagation Delay from Trigger to Driver Output Off Figure 30. Delay to Disable Mode, VTRIG = 5 V 75 1.08 70 1.06 65 1.04 tMIN_TON (ms) tMIN_TON (ns) 8 60 55 50 1.02 1.00 0.98 45 0.96 40 0.94 35 −40 −20 0 20 40 60 80 100 0.92 −40 120 −20 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 31. Minimum On−time RMIN_TON = 0 W Figure 32. Minimum On−time RMIN_TON = 10 kW www.onsemi.com 12 NCP4305 TYPICAL CHARACTERISTICS 5.4 290 5.3 280 270 tMIN_TOFF (ns) tMIN_TON (ms) 5.2 5.1 5.0 4.9 240 230 210 4.7 4.6 −40 −20 0 20 40 60 80 100 200 190 −40 120 −20 0 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 33. Minimum On−time RMIN_TON = 50 kW Figure 34. Minimum Off−time RMIN_TOFF = 0 W 1.08 5.4 1.06 5.3 1.04 5.2 tMIN_TOFF (ms) tMIN_TOFF (ms) 250 220 4.8 1.02 1.00 0.98 5.1 5.0 4.9 0.96 4.8 0.94 4.7 0.92 −40 −20 0 20 40 60 80 100 4.6 −40 120 −20 0 20 40 60 80 100 TJ (°C) TJ (°C) Figure 35. Minimum Off−time RMIN_TOFF = 10 kW Figure 36. Minimum Off−time RMIN_TOFF = 50 kW 1.04 1.08 1.03 1.06 1.02 1.04 tMIN_TOFF (ms) tMIN_TON (ms) 260 1.01 1.00 0.98 120 1.02 1.00 0.98 0.96 0.96 0.94 0.94 092 0.92 0 5 10 15 20 25 30 0 35 5 10 15 20 25 30 VCC (V) VCC (V) Figure 37. Minimum On−time RMIN_TON = 10 kW Figure 38. Minimum Off−time RMIN_TOFF = 10 kW www.onsemi.com 13 35 NCP4305 TYPICAL CHARACTERISTICS 5.5 10.4 VCC = 12 V, CDRV = 0 nF VCC = 12 V, CDRV = 1 nF VCC = 12 V, CDRV = 10 nF VCC = 35 V, CDRV = 0 nF VCC = 35 V, CDRV = 1 nF VCC = 35 V, CDRV = 10 nF VDRV (V) 10.0 9.8 5.1 VDRV (V) 10.2 VCC = 12 V, CDRV = 0 nF VCC = 12 V, CDRV = 1 nF VCC = 12 V, CDRV = 10 nF VCC = 35 V, CDRV = 0 nF VCC = 35 V, CDRV = 1 nF VCC = 35 V, CDRV = 10 nF 5.3 9.6 4.9 4.7 9.4 4.5 9.2 9.0 −40 −20 0 20 40 60 80 4.3 −40 −20 120 100 20 40 60 80 100 120 TJ (°C) TJ (°C) Figure 39. Driver and Output Voltage, ver. B, D and Q Figure 40. Driver Output Voltage, ver. A and C 50 5.3 TJ = 125°C TJ = 85°C TJ = 55°C TJ = 25°C 45 40 TJ = 0°C TJ = −20°C TJ = −40°C 5.2 5.1 tMAX_TON (ms) 35 30 25 20 5.0 4.9 4.8 4.7 15 4.6 10 4.5 5 0 4.4 0 0.5 1.0 1.5 2.0 2.5 4.3 −40 3.0 −20 0 20 40 60 80 100 120 VMAX_TON (V) TJ (°C) Figure 41. Maximum On−time, ver. Q Figure 42. Maximum On−time, VMAX_TON = 3 V, ver. Q 55 53 51 tMAX_TON (ms) tMAX_TON (ms) 0 49 47 45 43 41 −40 −20 0 20 40 60 80 100 TJ (°C) Figure 43. Maximum On−time, VMAX_TON = 0.3 V, ver. Q www.onsemi.com 14 120 NCP4305 APPLICATION INFORMATION General description forward). The time delay from trigger input to driver turn off event is tPD_TRIG. Additionally, the trigger input can be used to disable the IC and activate a low consumption standby mode. This feature can be used to decrease standby consumption of an SMPS. If the trigger input is not wanted than the trigger pin can be tied to GND or an option can be chosen to replace this pin with a MAX_TON input. An output driver features capability to keep SR transistor closed even when there is no supply voltage for NCP4305. SR transistor drain voltage goes up and down during SMPS operation and this is transferred through drain gate capacitance to gate and may turn on transistor. NCP4305 uses this pulsing voltage at SR transistor gate (DRV pin) and uses it internally to provide enough supply to activate internal driver sink transistor. DRV voltage is pulled low (not to zero) thanks to this feature and eliminate the risk of turned on SR transistor before enough VCC is applied to NCP4305. Some IC versions include a MAX_TON circuit that helps a quasi resonant (QR) controller to work in CCM mode when a heavy load is present like in the example of a printer’s motor starting up. Finally, the NCP4305 features a special pin (LLD) that can be used to reduce gate driver voltage clamp according to application load conditions. This feature helps to reduce issues with transition from disabled driver to full driver output voltage and back. Disable state can be also activated through this pin to decrease power consumption in no load conditions. If the LLD feature is not wanted then the LLD pin can be tied to GND. The NCP4305 is designed to operate either as a standalone IC or as a companion IC to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. This controller features a high current gate driver along with high−speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification MOSFET. With its novel architecture, the NCP4305 has enough versatility to keep the synchronous rectification system efficient under any operating mode. The NCP4305 works from an available voltage with range from 4 V (A, D & Q options) or 8 V (B & C options) to 35 V (typical). The wide VCC range allows direct connection to the SMPS output voltage of most adapters such as notebooks, cell phone chargers and LCD TV adapters. Precise turn-off threshold of the current sense comparator together with an accurate offset current source allows the user to adjust for any required turn-off current threshold of the SR MOSFET switch using a single resistor. Compared to other SR controllers that provide turn-off thresholds in the range of −10 mV to −5 mV, the NCP4305 offers a turn-off threshold of 0 mV. When using a low RDS(on) SR (1 mW) MOSFET our competition, with a −10 mV turn off, will turn off with 10 A still flowing through the SR FET, while our 0 mV turn off turns off the FET at 0 A; significantly reducing the turn-off current threshold and improving efficiency. Many of the competitor parts maintain a drain source voltage across the MOSFET causing the SR MOSFET to operate in the linear region to reduce turn−off time. Thanks to the 8 A sink current of the NCP4305 significantly reduces turn off time allowing for a minimal drain source voltage to be utilized and efficiency maximized. To overcome false triggering issues after turn-on and turn−off events, the NCP4305 provides adjustable minimum on-time and off-time blanking periods. Blanking times can be adjusted independently of IC VCC using external resistors connected to GND. If needed, blanking periods can be modulated using additional components. An extremely fast turn−off comparator, implemented on the current sense pin, allows for NCP4305 implementation in CCM applications without any additional components or external triggering. An ultrafast trigger input offers the possibility to further increase efficiency of synchronous rectification systems operated in CCM mode (for example, CCM flyback or Current Sense Input Figure 44 shows the internal connection of the CS circuitry on the current sense input. When the voltage on the secondary winding of the SMPS reverses, the body diode of M1 starts to conduct current and the voltage of M1’s drain drops approximately to −1 V. The CS pin sources current of 100 mA that creates a voltage drop on the RSHIFT_CS resistor (resistor is optional, we recommend shorting this resistor). Once the voltage on the CS pin is lower than VTH_CS_ON threshold, M1 is turned−on. Because of parasitic impedances, significant ringing can occur in the application. To overcome false sudden turn−off due to mentioned ringing, the minimum conduction time of the SR MOSFET is activated. Minimum conduction time can be adjusted using the RMIN_TON resistor. www.onsemi.com 15 NCP4305 Figure 44. Current Sensing Circuitry Functionality Figure 45). Therefore the turn−off current depends on MOSFET RDSON. The −0.5 mV threshold provides an optimum switching period usage while keeping enough time margin for the gate turn-off. The RSHIFT_CS resistor provides the designer with the possibility to modify (increase) the actual turn−on and turn−off secondary current thresholds. To ensure proper switching, the min_tOFF timer is reset, when the VDS of the MOSFET rings and falls down past the VTH_CS_RESET. The minimum off−time needs to expire before another drive pulse can be initiated. Minimum off−time timer is started again when VDS rises above VTH_CS_RESET. The SR MOSFET is turned-off as soon as the voltage on the CS pin is higher than VTH_CS_OFF (typically −0.5 mV minus any voltage dropped on the optional RSHIFT_CS). For the same ringing reason, a minimum off-time timer is asserted once the VCS goes above VTH_CS_RESET. The minimum off-time can be externally adjusted using RMIN_TOFF resistor. The minimum off−time generator can be re−triggered by MIN_TOFF reset comparator if some spurious ringing occurs on the CS input after SR MOSFET turn−off event. This feature significantly simplifies SR system implementation in flyback converters. In an LLC converter the SR MOSFET M1 channel conducts while secondary side current is decreasing (refer to www.onsemi.com 16 NCP4305 VDS = VCS ISEC V TH_CS _RESET – (RSHIFT _CS*ICS ) VTH_CS_OFF – (RSHIFT _CS*ICS ) VTH_CS _ON – (RSHIFT _CS*ICS ) VDRV Turn−on delay Turn −off delay Min ON−time tMIN_TON Min t OFF timer was stopped here because of VCS<VTH_CS_RESET Min OFF−time tMIN_TOFF t The tMIN_TON and t MIN_TOFF are adjustable by R MIN_TON and RMIN_TOFF resistors Figure 45. CS Input Comparators Thresholds and Blanking Periods Timing in LLC VDS = VCS ISEC VTH_CS_RESET – (RSHIFT_CS*ICS ) VTH_CS_OFF – (RSHIFT_CS*ICS ) VTH_CS _ON – (RSHIFT_CS*ICS ) VDRV Turn−on delay Turn −off delay Min ON−time Min t OFF timer was stopped here because of VCS<VTH_CS_RESET tMIN_TON Min OFF−time tMIN_TOFF t The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors Figure 46. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback www.onsemi.com 17 NCP4305 If no RSHIFT_CS resistor is used, the turn-on, turn-off and VTH_CS_RESET thresholds are fully given by the CS input specification (please refer to electrical characteristics table). The CS pin offset current causes a voltage drop that is equal to: V RSHIFT_CS + R SHIFT_CS * I CS Note that RSHIFT_CS impact on turn-on and VTH_CS_RESET thresholds is less critical than its effect on the turn−off threshold. It should be noted that when using a SR MOSFET in a through hole package the parasitic inductance of the MOSFET package leads (refer to Figure 47) causes a turn−off current threshold increase. The current that flows through the SR MOSFET experiences a high Di(t)/Dt that induces an error voltage on the SR MOSFET leads due to their parasitic inductance. This error voltage is proportional to the derivative of the SR MOSFET current; and shifts the CS input voltage to zero when significant current still flows through the MOSFET channel. As a result, the SR MOSFET is turned−off prematurely and the efficiency of the SMPS is not optimized − refer to Figure 48 for a better understanding. (eq. 1) Final turn−on and turn off thresholds can be then calculated as: V CS_TURN_ON + V TH_CS_ON * ǒR SHIFT_CS * I CSǓ (eq. 2) V CS_TURN_OFF + V TH_CS_OFF * ǒR SHIFT_CS * I CSǓ (eq. 3) V CS_RESET + V TH_CS_RESET * ǒR SHIFT_CS * I CSǓ (eq. 4) Figure 47. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application www.onsemi.com 18 NCP4305 Figure 48. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 Package With Long Leads − SR MOSFET channel Conduction Time is Reduced current Di/Dt and high operating frequency is to use lead−less SR MOSFET i.e. SR MOSFET in SMT package. The parasitic inductance of a SMT package is negligible causing insignificant CS turn−off threshold shift and thus minimum impact to efficiency (refer to Figure 49). Note that the efficiency impact caused by the error voltage due to the parasitic inductance increases with lower MOSFETs RDS(on) and/or higher operating frequency. It is thus beneficial to minimize SR MOSFET package leads length in order to maximize application efficiency. The optimum solution for applications with high secondary www.onsemi.com 19 NCP4305 Figure 49. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package with Minimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized It can be deduced from the above paragraphs on the induced error voltage and parameter tables that turn−off threshold precision is quite critical. If we consider a SR MOSFET with RDS(on) of 1 mW, the 1 mV error voltage on the CS pin results in a 1 A turn-off current threshold difference; thus the PCB layout is very critical when implementing the SR system. Note that the CS turn-off comparator is referred to the GND pin. Any parasitic impedance (resistive or inductive − even on the magnitude of mW and nH values) can cause a high error voltage that is then evaluated by the CS comparator. Ideally the CS turn−off comparator should detect voltage that is caused by secondary current directly on the SR MOSFET channel resistance. In reality there will be small parasitic impedance on the CS path due to the bonding wires, leads and soldering. To assure the best efficiency results, a Kelvin connection of the SR controller to the power circuitry should be implemented. The GND pin should be connected to the SR MOSFET source soldering point and current sense pin should be connected to the SR MOSFET drain soldering point − refer to Figure 47. Using a Kelvin connection will avoid any impact of PCB layout parasitic elements on the SR controller functionality; SR MOSFET parasitic elements will still play a role in attaining an error voltage. Figure 50 and Figure 51 show examples of SR system layouts using MOSFETs in TO220 and SMT packages. It is evident that the MOSFET leads should be as short as possible to minimize parasitic inductances when using packages with leads (like TO220). Figure 51 shows how to layout design with two SR MOSFETs in parallel. It has to be noted that it is not easy task and designer has to paid lot of attention to do symmetric Kelvin connection. www.onsemi.com 20 NCP4305 the start of SR MOSFET turn−off of process. This input can be used in applications operated in deep Continues Conduction Mode (CCM) to further increase efficiency and/or to activate disable mode of the SR driver in which the consumption of the NCP4305 is reduced to maximum of ICC_DIS. NCP4305 is capable to turn−off the SR MOSFET reliably in CCM applications just based on CS pin information only, without using the trigger input. However, natural delay of the ZCD comparator and DRV turn−off delay increase overlap between primary and secondary MOSFETs switching (also known as cross conduction). If one wants to achieve absolutely maximum efficiency with deep CCM applications, then the trigger signal coming from the primary side should be applied to the trigger pin. The trigger input then turns the SR MOSFET off slightly before the secondary winding voltage reverses. There are several possibilities for transferring the trigger signal from the primary to the secondary side − refer to Figures 66 and 67. The trigger signal is blanked for tTRIGBLANK after the DRV turn−on process has begun. The blanking technique is used to increase trigger input noise immunity against the parasitic ringing that is present during the turn on process due to the SMPS layout. The trigger input is supersedes the CS input except trigger blanking period. TRIG/DIS signal turns the SR MOSFET off or prohibits its turn−on when the Trigger/Disable pin is pulled above VTRIG_TH. The SR controller enters disable mode when the trigger pin is pulled−up for more than tDIS_TIM. In disable mode the IC consumption is significantly reduced. To recover from disable mode and enter normal operation, the TRIG/DIS pin is pulled low at least for tDIS_END. Figure 50. Recommended Layout When Using SR MOSFET in TO220 Package Figure 51. Recommended Layout When Using SR MOSFET in SMT Package (2x SO8 FL) Trigger/Disable input The NCP4305 features an ultrafast trigger input that exhibits a maximum of tPD_TRIG delay from its activation to www.onsemi.com 21 NCP4305 V DS = VCS V TH _CS _RESET V TH _CS _OFF V TH _CS _ON VTRIG /DIS VDRV t1 t2 t3 t4 t5 t6 t7 t8 t9 t Figure 52. Trigger Input Functionality Waveforms Using the Trigger to Turn−off and Block the DRV Signal Trigger/Disable pin almost immediately turns off the drive to the SR MOSFET, turning off the MOSFET. The DRV is not turned−on in other case (t6) because the trigger pin is high in the time when CS pin signal crosses turn−on threshold. This figure clearly shows that the DRV can be asserted only on falling edge of the CS pin signal in case the trigger input is at low level (t2). Figure 52 shows basic Trigger/Disable input functionality. At t1 the Trigger/Disable pin is pulled low to enter into normal operation. At t2 the CS pin is dropped below the VTH_CS_ON, signaling to the NCP4305 to start to turn the SR MOSFET on. At t3 the NCP4305 begins to drive the MOSFET. At t4, the SR MOSFET is conducting and the Trigger/Disable pin is pulled high. This high signal on the www.onsemi.com 22 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS TRIG/DIS blank tTRIGBLANK Min ON−time VDRV t1 t2 t t3 Figure 53. Trigger Input Functionality Waveforms − Trigger Blanking In Figure 53 above, at time t1 the CS pin falls below the VTH_CS_ON while the Trigger is low setting in motion the DRV signal that appears at t2. At time t2 the DRV signal and Trigger blanking clock begin. Trigger/Disable signal goes high shortly after time t2. Due to the Trigger blanking clock (tTRIG_BLANK) the Trigger’s high signal does not affect the DRV signal until the tTRIGBLANK timer has expired. At time t3 the Trigger/Disable signal is re evaluated and the DRV signal is turned off. The TRIG/DIS input is blanked for tTRIGBLANK after DRV set signal to avoid undesirable behavior during SR MOSFET turn−on event. The blanking time in combination with high threshold voltage (VTRIG_TH) prevent triggering on ringing and spikes that are present on the TRIG/DIS input pin during the SR MOSFET turn−on process. Controller’s response to the narrow pulse on the Trigger/Disable pin is depicted in Figure 53 − this short trigger pulse enables to turn the DRV on for tTRIG_BLANK. Note that this case is valid only if device not entered disable mode before. www.onsemi.com 23 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS TRIG/DIS blank tTRIGBLANK MIN ON−TIME VDRV t0 t1 t2 t3 t4 t5 t6 t Figure 54. Trigger Input Functionality Waveforms − Trigger Blanking Acts Like a Filter Figure 54 above shows almost the same situation as in Figure 53 with one main exception; the TRIG/DIS signal was not high after trigger blanking timer expired so the DRV signal remains high. The advantage of the trigger blanking time during DRV turn−on is evident from Figure 54 since it acts like a filter on the Trigger/Disable pin. Rising edge of the DRV signal may cause spikes on the trigger input. If it wasn’t for the TRIG/DIS blanking these spikes, in combination with ultra−fast performance of the trigger logic, could turn the SR MOSFET off in an inappropriate time. www.onsemi.com 24 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS Min ON−time VDRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t Figure 55. Trigger Input Functionality Waveforms − Trigger Over Ride, CS Turn Off and Min On−time In Figure 56 the trigger input is low the whole time and the DRV pulses are purely a function of the CS signal and the minimum on−time. The first DRV pulse terminated based on the CS signal and another two DRV pulses are prolonged till the minimum on−time period end despite the CS signal crosses the VTH_CS_OFF threshold earlier. If a minimum on−time is too long the situation that occurs after time marker t6 Figure 56 can occur, is not correct and should be avoided. The minimum tON period should be selected shorter to overcome situation that the SR MOSFET is turned−on for too long time. The secondary current then changes direction and energy flows back to the transformer that result in reduced application efficiency and also in excessive ringing on the primary and secondary MOSFETs. Figure 55 depicts all possible driver turn−off events in details when correct VCC is applied. Controller driver is disabled based on trigger input signal in time t2; the trigger input overrides the minimum on−time period. Driver is turned−off according to the CS (VDS) signal (t5 marker) and when minimum on−time period elapsed already. TRIG/DIS signal needs to be LOW during this event. If the CS (VDS) voltage reaches VTH_CS_OFF threshold before minimum on−time period ends (t7) and the Trigger/Disable pin is low the DRV is turned−off on the falling edge of the minimum on−time period (t8 time marker in Figure 55). This demonstrates the fact that the Trigger over rides the minimum on−time. Minimum on−time has higher priority than the CS signal. www.onsemi.com 25 NCP4305 VDS = VCS VTH_CS _RESET VTH_CS _OFF VTH_CS _ON VTRIG/DIS Min ON−time VDRV t0 t1 t2 t3 t4 t5 Figure 56. Minimum On−Time Priority www.onsemi.com 26 t6 t7 t8 t9 t NCP4305 VDS = V CS V TH _CS_RESET V TH _CS_OFF V TH _CS_ON VTRIG /DIS Min ON−time Min OFF−time VDRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t Figure 57. Trigger Input Functionality Waveforms − Two Pulses at One Cycle voltage goes above VTH_CS_RESET threshold. Next cycle starts in time t6. The TRIG/DIS is low so driver is enabled and ready to be turned on when VDS falls below VTH_CS_ON threshold voltage thus the driver is turned on at time t6. The trigger signal rises up to HIGH level at time t7, consequently DRV turns−off and IC waits for high CS voltage to start minimum off−time execution. Figure 57 shows IC behavior in case the trigger signal features two pulses during one cycle of the VDS (CS) signal. The trigger goes low enables the DRV just before time t1 and DRV turns−on because the VDS voltage drops under VTH_CS_ON threshold voltage. The trigger signal disables driver at time t2. The trigger drops down to LOW level in time t3, but IC waits for complete minimum off−time. Minimum off−time execution is blocked until CS pin www.onsemi.com 27 NCP4305 V DS = VCS V TH _CS _RESET V TH _CS _OFF V TH _CS _ON VTRIG/DIS t DIS_TIM Min ON−time VDRV Power consumption t0 t1 t2 t3 t4 t Figure 58. Trigger Input Functionality Waveforms − Disable Mode Activation transition to disable mode. Figure 59 shows disable mode transition 2nd case − i.e. when trigger rising edge comes during the trigger blank period. Figure 60 shows entering into disable mode and back to normal sequences. In Figure 58 above, at t2 the CS pin rises to VTH_CS_OFF and the SR MOSFET is turned−off. At t3 the TRIG/DIS signal is held high for more than tDIS_TIM. NCP4305 enters disable mode after tDIS_TIM. Driver output is disabled in disable mode. The DRV stays low (disabled) during www.onsemi.com 28 NCP4305 VDS = VCS V TH_CS _RESET VTH_CS _OFF VTH_CS _ON VTRIG/DIS t DIS_TIM Min ON−time VDRV tTRIGBLANK Power consumption t0 t1 t2 t3 Figure 59. Trigger Input Functionality Waveforms − Disable Mode Clock Initiation www.onsemi.com 29 t NCP4305 VDS = VCS VTH_CS _RESET VTH_CS_OFF VTH_CS _ON VTRIG/DIS tDIS _TIM VDRV t DIS_REC Min OFF−time Power consumption Disable mode t0 t1 t2 t3 t4 t Figure 60. Trigger Input Functionality Waveforms − Disable and Normal Modes Figures 61 and 62 shows exit from disable mode in detail. NCP4305 requires up to tDIS_REC to recover all internal circuitry to normal operation mode when recovering from disable mode. The driver is then enabled after complete tMIN_TOFF period when CS(VDS) voltage is over VTH_CS_RESET threshold. Driver turns−on in the next cycle on CS (VDS) falling edge signal only (t5 − Figure 61). The DRV stays low during recovery time period. Trigger input has to be low at least for tDIS_END time to end disable mode and start with recovery. Trigger can go back high after tDIS_END without recovery interruption. www.onsemi.com 30 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS Min OFF−time VDRV Disable mode Power consumption tDIS _REC t0 Waits for complete tMIN_TOFF t1 t2 t3 Normal mode t4 t5 t6 t7 t8 t Figure 61. Trigger Input Functionality Waveforms − Exit from Disable Mode before the Falling Edge of the CS Signal www.onsemi.com 31 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS Min OFF−time t DIS _END VDRV Disable mode Power consumption Waits for complete t MIN_TOFF Recovery time t0 t1 t2 t3 Normal mode t4 Figure 62. Trigger Input Functionality Waveforms www.onsemi.com 32 t5 t NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF V TH_CS_ON VTRIG/DIS Min OFF−time tMIN_TOFF VDRV tDIS_REC Power consumption Disable mode t0 Waits for complete t MIN_TOFF Recovery t1 t2 t3 Normal mode t4 t5 t6 t Figure 63. Trigger Input Functionality Waveforms Figure 63 shows detail IC behavior after disable mode is ended. The trigger pin voltage goes low at t1 and after tDIS_REC IC leaves disable mode (t2). VDS voltage goes high again at time t3 and this event starts minimum off−time timer execution. Next VDS falling edge below VTH_CS_ON level activates driver. www.onsemi.com 33 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF V TH_CS_ON VTRIG/DIS Min OFF−time tMIN_TOFF VDRV Disable mode Power consumption t DIS_REC Waits for complete tMIN_TOFF Recovery t0 t1 t2 t3 t4 Normal mode t5 t6 t7 t8 t Figure 64. Trigger Input Functionality Waveforms Different situation of leaving from disable mode is shown at Figure 64. Minimum off−time execution starts at time t2, but before time elapses VDS voltage falls to negative voltage. This interrupts minimum off−time execution and the IC waits to another time when VDS voltage is positive and then is again started the minimum off−time timer. The IC returns into normal mode after whole minimum off−time elapses. www.onsemi.com 34 NCP4305 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON t MIN_TOFF Not complete t MIN_TOFF −> IC is not activated Min OFF− time t MIN_TOFF Complete t MIN_TOFF activates IC t MIN_TOFF is stopped due to VDS drops below VTH_CS_RESET t MIN_TON Min ON−time VDRV VCC VCCON t1 t3 t2 t4 t5 t7 t6 t9 t8 t10 t11 t13 t15 t12 t14 Figure 65. NCP4305 Operation after Start−Up Event minimum off−time period expires, at time t2 thanks to CS voltage lower than VTH_CS_RESET threshold. The aforementioned reset situation can be seen again at time t3, t4, t5 and t6. A complete minimum off−time period elapses between times t7 and t8 allowing the IC to activate a driver output after time t8. The NCP4305 works very well in CCM application without any triggering method, but using some may improve overall operation. Typical application schematics of CCM flyback converters using two different primary triggering techniques can be seen in Figures 66 and 67. Both provided methods reduce the commutation losses and the SR MOSFET drain voltage spike, which results in improved efficiency. Start−up event waveforms are shown at Figure 65. A start−up event is very similar to an exit from disable mode event. The IC waits for a complete minimum off−time event (CS pin voltage is higher than VTH_CS_RESET) until drive pulses can continue. Figure 65 shows how the minimum off−time timer is reset when CS voltage is oscillating through VTH_CS_RESET level. The NCP4305 starts operation at time t1 (time t1 can be seen as a wake−up event from the disable mode through TRIG/DIS or LLD pin). Internal logic waits for one complete minimum off−time period to expire before the NCP4305 can activate the driver after a start−up or wake−up event. The minimum off−time timer starts to run at time t1, because VCS is higher than VTH_CS_RESET. The timer is then reset, before its set www.onsemi.com 35 NCP4305 + Vbulk TR1 R5 C2 C8 R14 +Vout R13 + C3 D3 R12 C7 + VCC FLYBACK CONTROL CIRCUITRY FB M2 D4 D7 C4 DRV D1 GND C6 M1 CS R1 R9 R10 R6 D5 R7 OK1 TR2 NCP4305 C5 D6 R11 Figure 66. Primary Triggering in Deep CCM Application Using Auxiliary Winding − NCP4305A, B, C or D The application shown in Figure 66 is simplest and the most cost effective solution for primary SR triggering. This method uses auxiliary winding made of triple insulated wire placed close to the primary winding section. This auxiliary winding provides information about primary turn−on event to the SR controller before the secondary winding reverses. This is possible thanks to the leakage between primary and secondary windings that creates natural delay in energy transfer. This technique provides approximately 0.5% efficiency improvement when the application is operated in deep CCM and a transformer that has a leakage of 1% of primary inductance is used. Figure 67. Primary Triggering in Deep CCM Application Using Trigger Transformer − NCP4305A, B, C or D sensitive, it is not necessary to transmit the entire primary driver pulse to the secondary. The coupling capacitor C5 is used to allow the trigger transformer’s core to reset and also to prepare a needle pulse (a pulse with width shorter than Application from Figure 67 uses an ultra−small trigger transformer to transfer primary turn−on information directly from the primary controller driver pin to the SR controller trigger input. Because the trigger input is rising edge www.onsemi.com 36 NCP4305 primary and secondary to transmit the trigger signal. We do not recommend this technique as the parasitic capacitive currents between primary and secondary may affect the trigger signal and thus overall system functionality. 100 ns) to be transmitted to the NCP4305 trigger input. The advantage of needle trigger pulse usage is that the required volt−second product of the pulse transformer is very low and that allows the designer to use very small and cheap magnetic. The trigger transformer can even be prepared on a small toroidal ferrite core with outer diameter of 4 mm and four turns for primary and secondary windings to assure Lprimary = Lsecondary > 10 mH. Proper safety insulation between primary and secondary sides can be easily assured by using triple insulated wire for one or, better, both windings. This primary triggering technique provides approximately 0.5% efficiency improvement when the application is operated in deep CCM and transformer with leakage of 1% of primary inductance is used. It is also possible to use capacitive coupling (use additional capacitor with safety insulation) between the Minimum tON and tOFF Adjustment The NCP4305 offers an adjustable minimum on−time and off−time blanking periods that ease the implementation of a synchronous rectification system in any SMPS topology. These timers avoid false triggering on the CS input after the MOSFET is turned on or off. The adjustment of minimum tON and tOFF periods are done based on an internal timing capacitance and external resistors connected to the GND pin − refer to Figure 68 for a better understanding. Figure 68. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way) Current through the MIN_TON adjust resistor can be calculated as: I R_MIN_TON + V ref R Ton_min The internal capacitor size would be too large if IR_MIN_TON was used. The internal current mirror uses a proportional current, given by the internal current mirror ratio. One can then calculate the MIN_TON and MIN_TOFF blanking periods using below equations: (eq. 5) If the internal current mirror creates the same current through RMIN_TON as used the internal timing capacitor (Ct) charging, then the minimum on−time duration can be calculated using this equation. t MIN_TON + C t V ref I R_MIN_TON + Ct V ref Vref t MIN_TON + 1.00 * 10 −4 * R MIN_TON [ms] (eq. 7) t MIN_TOFF + 1.00 * 10 −4 * R MIN_TOFF [ms] (eq. 8) Note that the internal timing comparator delay affects the accuracy of Equations 7 and 8 when MIN_TON/ MIN_TOFF times are selected near to their minimum possible values. Please refer to Figures 69 and 70 for measured minimum on and off time charts. (eq. 6) + C t @ R MIN_TON RMIN_TON www.onsemi.com 37 NCP4305 10 The absolute minimum tON duration is internally clamped to 55 ns and minimum tOFF duration to 245 ns in order to prevent any potential issues with the MIN_TON and/or MIN_TOFF pins being shorted to GND. The NCP4305 features dedicated anti−ringing protection system that is implemented with a MIN_TOFF blank generator. The minimum off−time one−shot generator is restarted in the case when the CS pin voltage crosses VTH_CS_RESET threshold and MIN_TOFF period is active. The total off-time blanking period is prolonged due to the ringing in the application (refer to Figure 45). Some applications may require adaptive minimum on and off time blanking periods. With NCP4305 it is possible to modulate blanking periods by using an external NPN transistor − refer to Figure 71. The modulation signal can be derived based on the load current, feedback regulator voltage or other application parameter. 9 8 tMIN_TON (ms) 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 RMIN_TON (kW) Figure 69. MIN_TON Adjust Characteristics 10 9 tMIN_TOFF (ms) 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 RMIN_TOFF (kW) Figure 70. MIN_TOFF Adjust Characteristics Figure 71. Possible Connection for MIN_TON and MIN_TOFF Modulation www.onsemi.com 38 NCP4305 Maximum tON adjustment The Internal connection of the MAX_TON feature is shown in Figure 72. Figure 72 shows a method that allows for a modification of the maximum on−time according to output voltage. At a lower VOUT, caused by hard overload or at startup, the maximum on−time should be longer than at nominal voltage. Resistor RA can be used to modulate maximum on−time according to VOUT or any other parameter. The operational waveforms at heavy load in QR type SMPS are shown in Figure 73. After tMAX_TON time is exceeded, the synchronous switch is turned off and the secondary current is conducted by the diode. Information about turned off SR MOSFET is transferred by the DRV pin through a small pulse transformer to the primary side where it acts on the ZCD detection circuit to allow the primary switch to be turned on. Secondary side current disappears before the primary switch is turned on without a possibility of cross current condition. The NCP4305Q offers an adjustable maximum on−time (like the min_tON and min_tOFF settings shown above) that can be very useful for QR controllers at high loads. Under high load conditions the QR controller can operate in CCM thanks to this feature. The NCP4305Q version has the ability to turn−off the DRV signal to the SR MOSFET before the secondary side current reaches zero. The DRV signal from the NCP4305Q can be fed to the primary side through a pulse transformer (see Figure 4 for detail) to a transistor on the primary side to emulate a ZCD event before an actual ZCD event occurs. This feature helps to keep the minimum switching frequency up so that there is better energy transfer through the transformer (a smaller transformer core can be used). Also another advantage is that the IC controls the SR MOSFET and turns off from secondary side before the primary side is turned on in CCM to ensure no cross conduction. By controlling the SR MOSFET’s turn off before the primary side turn off, producing a zero cross conduction operation, this will improve efficiency. Figure 72. Internal Connection of the MAX_TON Generator, NCP4305Q www.onsemi.com 39 NCP4305 VDS = VCS ISEC V TH_CS _RESET – (RSHIFT _CS*ICS ) VTH_CS_OFF – (RSHIFT _CS*ICS ) VTH_CS _ON – (RSHIFT _CS*ICS ) Primary virtual ZCD detection delay V DRV Turn−on delay Turn −off delay Min ON−time t MIN _TON Min OFF−time tMIN _TOFF Max ON−time tMAX _TON t The tMIN _TON and tMIN _TOFF are adjustable by R MIN _TON and R MIN _TOFF resistors, t MAX_TON is adjustable by R MAX_TON Figure 73. Function of MAX_TON Generator in Heavy Load Condition Adaptive Gate Driver Clamp and automatic Light Load Turn−off and drop at MOSFET’s RDS(on) only improves stability during load transients. 2nd − In extremely low load conditions or no load conditions the NCP4305 fully disables driver output and reduces the internal power consumption when output load drops below the level where skip−mode takes place. Both features are controlled by voltage at LLD pin. The LLD pin voltage characteristic is shown in Figure 74. Driver voltage clamp is a linear function of the voltage difference between the VCC and LLD pins from VLLD_REC point up to VLLD_MAX. A disable mode is available, where the IC current consumption is dramatically reduced, when the difference of VCC − VLLD voltage drops below VLLD_DIS. When the voltage difference between the VCC − VLLD pins increase above VLLC_REC the disable mode ends and the IC regains normal operation. It should be noted that there are also some time delays to enter and exit from the disable mode. Time waveforms are shown at Figure 75. There is a time, tLLD_DISH, that the logic ignores changes from disable mode to normal or reversely. There is also some time tLLD_DIS_R that is needed after an exit from the disable mode to assure proper internal block biasing before SR controller starts work normally. As synchronous rectification system significantly improves efficiency in most of SMPS applications during medium or full load conditions. However, as the load reduces into light or no−load conditions the SR MOSFET driving losses and SR controller consumption become more critical. The NCP4305 offers two key features that help to optimize application efficiency under light load and no load conditions: 1st − The driver clamp voltage is modulated and follows the output load condition. When the output load decreases the driver clamp voltage decreases as well. Under heavy load conditions the SR MOSFET’s gate needs to be driven very hard to optimize the performance and reduce conduction losses. During light load conditions it is not as critical to drive the SR MOSFET’s channel into such a low RDSON state. This adaptive gate clamp technique helps to optimize efficiency during light load conditions especially in LLC applications where the SR MOSFETs with high input capacitance are used. Driver voltage modulation improves the system behavior when SR controller state is changed in and out of normal or disable modes. Soft transient between drop at body diode www.onsemi.com 40 NCP4305 VDRVCLAMP ICC VDRVMAX VLLD_DIS VLLD_REC VCC −VLLD VLLD_MAX Figure 74. LLD Voltage to Driver Clamp and Current Consumption Characteristic (DRV Unloaded) VCC−VLLD tLLD_DISH tLLD_DISH tLLD_DISH tLLD_DISH VLLD_REC DISABLE MODE NORMAL DISABLE MODE tLLD_DIS_R tLLD_DIS_R NORMAL ICC NORMAL VLLD_DIS t Figure 75. LLD Pin Disable Behavior in Time Domain through R3 and capacitors C2 and C3, the load level can be sensed. Output voltage of this detector on the LLD pin is referenced to controller VCC with an internal differential amplifier in NCP4305. The output of the differential amplifier is then used in two places. First the output is used in the driver block for gate drive clamp voltage adjustment. Next, the output signal is evaluated by a no−load detection comparator that activates IC disable mode in case the load is disconnected from the application output. The two main SMPS applications that are using synchronous rectification systems today are flyback and LLC topologies. Different light load detection techniques are used in NCP4305 controller to reflect differences in operation of both mentioned applications. Detail of the light load detection implementation technique used in NCP4305 in flyback topologies is displayed at Figure 76. Using a simple and cost effective peak detector implemented with a diode D1, resistors R1 www.onsemi.com 41 NCP4305 Figure 76. NCP4305 Light Load and No Load Detection Principle in Flyback Topologies directly reduces DRV clamp voltage down from its maximum level. The DRV is then fully disabled when IC enters disable mode. The IC exits from disable mode when difference between LLD voltage and VCC increases over VLLD_REC. Resistors R2 and R3 are also used for voltage level adjustment and with capacitor C3 form low pass filter that filters relatively high speed ripple at C2. This low pass filter also reduces speed of state change of the SR controller from normal to disable mode or reversely. Time constant should be higher than feedback loop time constant to keep whole system stable. Operational waveforms related to the flyback LLD circuitry are provided in Figure 77. The SR MOSFET drain voltage drops to ~ 0 V when ISEC current is flowing. When the SR MOSFET is conducting the capacitor C2 charges−up, causing the difference between the LLD pin and VCC pin to increase, and drop the LLD pin voltage. As the load decreases the secondary side currents flows for a shorter a shorter time. C2 has less time to accumulate charge and the voltage on the C2 decreases, because it is discharged by R2 and R3. This smaller voltage on C2 will cause the LLD pin voltage to increase towards VCC and the difference between LLD and VCC will go to zero. The output voltage then ISEC VC2 VC3 VLLD_REC VLLDMAX VLLD_DIS VDRV VDRVMAX IC enters disable mode t Figure 77. NCP4305 Driver Clamp Modulation Waveforms in Flyback Application Entering into Light/No Load Condition www.onsemi.com 42 NCP4305 IOUT VCC−VLLD VLLD_REC VLLDMAX VLLD_DIS VDRVMAX IC enters disable mode VDRV t Figure 78. NCP4305 Driver Clamp Modulation Circuitry Transfer Characteristic in Flyback Application The technique used for LLD detection in LLC is similar to the LLD detection method used in a flyback with the exception the D1 and D2 OR−ing diodes are used to measure the total duty cycle to see if it is operating in skip mode. Figure 79. NCP4305 Light Load Detection in LLC Topology The driver clamp modulation waveforms of NCP4305 in LLC are provided in Figure 80. The driver clamp voltage clips to its maximum level when LLC operates in normal mode. When the LLC starts to operate in skip mode the driver clamp voltage begins to decrease. The specific output current level is determined by skip duty cycle and detection circuit consists of R1, R2, R3, C2, C3 and diodes D1, D2. The NCP4305 enters disable mode in low load condition, when VCC−VLLD drops below VLLD_DIS (0.9 V). Disable mode ends when this voltage increase above VLLD_REC (1.0 V) Figure 81 shows how LLD voltage modulates the driver output voltage clamp. www.onsemi.com 43 NCP4305 Normal operation Skip operation VCS 1 VCS 2 VC2 V LLDMAX V CC −V LLD (V C3) V LLD_REC V LLD_DIS V DRVMAX DRV clamp IC enters disable mode t Figure 80. NCP4305 Driver Clamp Modulation Waveforms in LLC Application www.onsemi.com 44 NCP4305 VCC−VLLD IC enters disable mode VLLDMAX VLLD_REC VLLD_DIS VDRVMAX DRV clamp IOUT t Figure 81. NCP4305 Driver Clamp Modulation Circuitry Characteristic in LLC Application behavior is shown in Figure 46. Operation waveforms for this option are provided in Figure 83. Capacitor C2 is charged to maximum voltage when LLC is switching. When there is no switching in skip, capacitor C2 is discharged by R2 and when LLD voltage referenced to VCC falls below VLLD_DIS IC enters disable mode. Disable mode is ended when LLC starts switching. There exist some LLC applications where behavior described above is not the best choice. These applications transfer significant portion of energy in a few first pulses in skip burst. It is good to keep SR fully working during skip mode to improve efficiency. There can be still saved some energy using LLD function by activation disable mode between skip bursts. Simplified schematic for this LLD Figure 82. NCP4305 Light Load Detection in LLC Application − Other Option www.onsemi.com 45 NCP4305 Normal operation Skip operation VCS1 VCS2 VC2 VLLDMAX VCC−VLLD VLLD_DIS DRV clamp VLLD_REC IC enters disable mode VDRVMAX t Figure 83. NCP4305 Light Load Detection Behavior in LLC Application – Other Option Power Dissipation Calculation significantly. Therefore, the MOSFET switch always operates under Zero Voltage Switching (ZVS) conditions when in a synchronous rectification system. The following steps show how to approximately calculate the power dissipation and DIE temperature of the NCP4305 controller. Note that real results can vary due to the effects of the PCB layout on the thermal resistance. It is important to consider the power dissipation in the MOSFET driver of a SR system. If no external gate resistor is used and the internal gate resistance of the MOSFET is very low, nearly all energy losses related to gate charge are dissipated in the driver. Thus it is necessary to check the SR driver power losses in the target application to avoid over temperature and to optimize efficiency. In SR systems the body diode of the SR MOSFET starts conducting before SR MOSFET is turned−on, because there is some delay from VTH_CS_ON detect to turn−on the driver. On the other hand, the SR MOSFET turn off process always starts before the drain to source voltage rises up Step 1 − MOSFET Gate−to Source Capacitance: During ZVS operation the gate to drain capacitance does not have a Miller effect like in hard switching systems because the drain to source voltage does not change (or its change is negligible). www.onsemi.com 46 NCP4305 it will need to be measured. Please note that the input capacitance is not linear (as shown Figure 84) and it needs to be characterized for a given gate voltage clamp level. Step 2 − Gate Drive Losses Calculation: Gate drive losses are affected by the gate driver clamp voltage. Gate driver clamp voltage selection depends on the type of MOSFET used (threshold voltage versus channel resistance). The total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. Most of today’s MOSFETs for SR systems feature low RDS(on) for 5 V VGS voltage. The NCP4305 offers both a 5 V gate clamp and a 10 V gate clamp for those MOSFET that require higher gate to source voltage. The total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the MOSFET: P DRV_total + V CC @ V CLAMP @ C g_ZVS @ f SW (eq. 9) Where: VCC VCLAMP Cg_ZVS C iss + C gs ) C gd is the NCP4305 supply voltage is the driver clamp voltage is the gate to source capacitance of the MOSFET in ZVS mode fsw is the switching frequency of the target application The total driving power loss won’t only be dissipated in the IC, but also in external resistances like the external gate resistor (if used) and the MOSFET internal gate resistance (Figure 50). Because NCP4305 features a clamped driver, it’s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. The low side driver switch resistance does not drop immediately at turn−off, thus it is necessary to use an equivalent value (RDRV_SIN_EQ) for calculations. This method simplifies power losses calculations and still provides acceptable accuracy. Internal driver power dissipation can then be calculated using Equation 10: C rss + C gd C oss + C ds ) C gd Figure 84. Typical MOSFET Capacitances Dependency on VDS and VGS Voltages Therefore, the input capacitance of a MOSFET operating in ZVS mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. Ciss capacitance for given gate to source voltage). The total gate charge, Qg_total, of most MOSFETs on the market is defined for hard switching conditions. In order to accurately calculate the driving losses in a SR system, it is necessary to determine the gate charge of the MOSFET for operation specifically in a ZVS system. Some manufacturers define this parameter as Qg_ZVS. Unfortunately, most datasheets do not provide this data. If the Ciss (or Qg_ZVS) parameter is not available then www.onsemi.com 47 NCP4305 Figure 85. Equivalent Schematic of Gate Drive Circuitry P DRV_IC + 1 @ C g_ZVS @ V CLAMP 2 @ f SW @ 2 ǒ R DRV_SINK_EQ Ǔ R DRV_SINK_EQ ) R G_EXT ) R g_int 1 ) @ C g_ZVS @ V CLAMP 2 @ f SW @ 2 ǒ R DRV_SOURCE_EQ ) C g_ZVS @ V CLAMP @ f SW @ ǒV CC * V CLAMPǓ Ǔ (eq. 10) R DRV_SOURCE_EQ ) R G_EXT ) R g_int Step 4 − IC Die Temperature Arise Calculation: Where: RDRV_SINK_EQ The die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal IC consumption losses). The package thermal resistance is specified in the maximum ratings table for a 35 mm thin copper layer with no extra copper plates on any pin (i.e. just 0.5 mm trace to each pin with standard soldering points are used). The DIE temperature is calculated as: is the NCP4305x driver low side switch equivalent resistance (0.5 W) RDRV_SOURCE_EQ is the NCP4305x driver high side switch equivalent resistance (1.2 W) is the external gate resistor (if used) RG_EXT Rg_int is the internal gate resistance of the MOSFET Step 3 − IC Consumption Calculation: T DIE + ǒP DRV_IC ) P CCǓ @ R qJ−A ) T A In this step, power dissipation related to the internal IC consumption is calculated. This power loss is given by the ICC current and the IC supply voltage. The ICC current depends on switching frequency and also on the selected min tON and tOFF periods because there is current flowing out from the min tON and tOFF pins. The most accurate method for calculating these losses is to measure the ICC current when CDRV = 0 nF and the IC is switching at the target frequency with given MIN_TON and MIN_TOFF adjust resistors. IC consumption losses can be calculated as: P CC + V CC @ I CC Where: PDRV_IC PCC RqJA TA (eq. 11) www.onsemi.com 48 (eq. 12) is the IC driver internal power dissipation is the IC control internal power dissipation is the thermal resistance from junction to ambient is the ambient temperature NCP4305 PRODUCT OPTIONS OPN Package UVLO [V] DRV clamp [V] Pin 5 function NCP4305ADR2G SOIC8 4.5 4.7 TRIG NCP4305AMTTWG WDFN8 4.5 4.7 TRIG NCP4305DDR2G SOIC8 4.5 9.5 TRIG NCP4305DMNTWG DFN8 4.5 9.5 TRIG NCP4305DMTTWG WDFN8 4.5 9.5 TRIG NCP4305QDR2G SOIC8 4.5 9.5 MAX_TON Usage LLC, CCM flyback, DCM flyback, forward, QR, QR with primary side CCM control QR with forced CCM from secondary side ORDERING INFORMATION Device NCP4305ADR2G Package Package marking Packing Shipping† SOIC8 NCP4305A SOIC−8 (Pb−Free) 2500 /Tape & Reel WDFN−8 (Pb−Free) 3000 /Tape & Reel DFN−8 (Pb−Free) 4000 /Tape & Reel NCP4305DDR2G NCP4305D NCP4305QDR2G NCP4305AMTTWG NCP4305Q WDFN8 NCP4305DMTTWG NCP4305DMNTWG 5A 5D DFN8 4305D †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 49 NCP4305 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 50 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCP4305 PACKAGE DIMENSIONS DFN8 4x4 CASE 488AF ISSUE C A B D PIN ONE REFERENCE 0.15 C 2X 0.15 C 2X 0.10 C 8X ÉÉ ÉÉ ÉÉ 0.08 C L1 DETAIL A E OPTIONAL CONSTRUCTIONS ÇÇ ÇÇ ÉÉ TOP VIEW EXPOSED Cu ÇÇÇÇ DETAIL B A A1 C SIDE VIEW ÇÇ MOLD CMPD ÉÉÉ ÉÉÉ ÇÇÇ A3 A1 DETAIL B (A3) NOTE 4 ALTERNATE CONSTRUCTIONS SEATING PLANE D2 DETAIL A 1 ÇÇ 8 K e NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS. L L 8X DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 −−− 0.30 0.50 −−− 0.15 SOLDERING FOOTPRINT* L 8X 2.21 4 0.63 E2 5 8X 4.30 2.39 b 0.10 C A B 0.05 C PACKAGE OUTLINE NOTE 3 BOTTOM VIEW 8X 0.80 PITCH 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 51 NCP4305 PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AT ISSUE O D L A B L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. L1 PIN ONE REFERENCE 0.10 C 2X 2X ÍÍÍ ÍÍÍ ÍÍÍ 0.10 C DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÉÉ TOP VIEW EXPOSED Cu DETAIL B 0.05 C 0.05 C A1 A3 SIDE VIEW e/2 MOLD CMPD DETAIL B A 8X MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.40 0.60 --0.15 0.50 0.70 ALTERNATE CONSTRUCTIONS C SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* DETAIL A e 7X 1 DIM A A1 A3 b D E e L L1 L2 7X PACKAGE OUTLINE 0.78 L 4 L2 2.30 8 5 8X BOTTOM VIEW b 0.10 C A 0.05 C 0.88 1 B 8X NOTE 3 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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