P4C1026 with packages - Pyramid Semiconductor

P4C1026/P4C1026L
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Three-State Outputs
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 20/25/35 ns (Military)
TTL/CMOS Compatible Outputs
Low Power
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C1026L only)
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil SOJ
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
DESCRIPTION
The P4C1026/P4C1026L is a 1 Meg ultra high speed
static RAM organized as 256K x 4. The CMOS memory
requires no clock or refreshing and has equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAM operates from a single 5V±10% tolerance power
supply. With battery backup (P4C1026L only), data integrity
is maintained for supply voltages down to 2.0V.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1026/P4C1026L is available in a 28-pin 300 mil
and 400 mil SOJ packages, as well as Ceramic DIP and
LCC packages, providing excellent board level densities.
Functional Block Diagram
Pin ConfigurationS
SOJ (J5, J7), DIP (C7)
Document # SRAM127 REV F
LCC (L13)
Revised July 2015
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
Maximum Ratings(1)
Sym
Parameter
RECOMMENDED OPERATING CONDITIONS
Value
Unit
V
Grade(2)
Ambient Temp
GND
VCC
0°C to 70°C
0V
5.0V ± 10%
Industrial
-40°C to +85°C
0V
5.0V ± 10%
Military
-55°C to +125°C
0V
5.0V ± 10%
VCC
Power Supply Pin with
Respect to GND
-0.5 to +7
VTERM
Terminal Voltage with
Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5
V
TA
Operating Temperature
-55 to +125
°C
TBIAS
Temperature Under Bias
-55 to +125
°C
TSTG
Storage Temperature
-65 to +150
°C
Sym
Parameter
Commercial
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
PT
Power Dissipation
1.0
W
CIN
Input Capacitance
IOUT
DC Output Current
50
mA
COUT
Output Capacitance
Conditions
Typ
Unit
VIN=0V
7
pF
VOUT=0V
10
pF
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym
Parameter
Test Conditions
P4C1026
P4C1026L
Unit
Min
Max
Min
Max
VCC + 0.5
2.2
VCC + 0.5
V
0.8
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5
VHC
CMOS Input High Voltage
VCC - 0.2
VCC + 0.5
VCC - 0.2
VCC + 0.5
V
VLC
CMOS Input Low Voltage
-0.5(3)
0.2
-0.5(3)
0.2
V
VCD
Input Clamp Diode
Voltage
VCC = Min, IIN = -18 mA
-1.2
-1.2
V
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min
0.4
0.4
V
VOH
Output High Voltage
(TTL Load)
IOH = -4 mA, VCC = Min
2.4
ILI
Input Leakage Current
VCC = Max,
VIN = GND to VCC
-5
+5
-5
+5
µA
ILO
Output Leakage Current
VCC = Max, CE = VIH,
VOUT = GND to VCC
-5
+5
-5
+5
µA
ISB
CE ≥ VIH, VCC = Max, f = Max,
Standby Power Supply
Current (TTL Input Levels) Outputs Open
—
35
—
20
mA
ISB1
Standby Power Supply
Current (CMOS Input
Levels)
—
10
—
2
mA
(3)
0.8
-0.5
(3)
2.4
V
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
VIN ≤ VLC or VIN ≥ VHC
N/A = Not applicable
Document # SRAM127 REV F
Page 2
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym
ICC
Parameter
Dynamic Operating Current*
Temperature Range
-15
-20
-25
-35
Unit
Commercial
80
75
75
75
mA
Industrial
90
80
80
80
mA
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS (P4C1026L only)
Sym
Parameter
Test Conditions
Min
Typ* VCC=
2.0V
3.0V
Max VCC=
2.0V
3.0V
2.0
Unit
VDR
VCC for Data Retention
V
ICCDR
Data Retention Current
CE ≥ VCC -0.2V,
tCDR
Chip Deselect to Data Retention Time
VIN ≥ VCC -0.2V
0
ns
tR†
Operation Recovery Time
or VIN ≤ 0.2V
tRC§
ns
10
15
250
500
µA
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETENTION WAVEFORM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-15
Min
-20
Max
Max
20
Min
-35
Max
Max
tAA
Address Access Time
15
20
25
35
ns
tAC
Chip Enable Access Time
15
20
25
35
ns
tOH
Output Hold from Address Change
2
2
2
2
ns
tLZ
Chip Enable to Output in Low Z
2
3
3
3
ns
tHZ
Chip Disable to Output in High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down
0
9
0
15
35
Unit
Read Cycle Time
8
25
Min
tRC
Document # SRAM127 REV F
15
Min
-25
10
0
20
ns
11
0
25
ns
ns
35
ns
Page 3
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
Notes:
1.Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
2.Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM127 REV F
4.This parameter is sampled and not 100% tested.
5.WE is HIGH for READ cycle.
6.CE is LOW and OE is LOW for READ cycle.
7.ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8.Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9.Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-15
Min
-20
Max
Min
-25
Max
Min
-35
Max
Min
Max
Unit
tWC
Write Cycle Time
13
20
25
35
ns
tCW
Chip Enable Time to End of Write
12
15
18
25
ns
tAW
Address Valid to End of Write
12
15
18
25
ns
tAS
Address Setup Time
0
0
0
0
ns
tWP
Write Pulse Width
12
15
18
25
ns
tAH
Address Hold Time
0
0
0
0
ns
tDW
Data Valid to End of Write
7
8
10
15
ns
tDH
Data Hold Time
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
6
2
8
2
10
2
15
3
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV F
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
Timing Waveform of Write Cycle No. 2 (CE Controlled)(10)
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
CE
OE
WE
I/O
Power
Standby
H
X
X
High Z
Standby
DOUT Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C1026/L, care must be taken
when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
* including scope and test fixture.
Document # SRAM127 REV F
Page 6
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
ORDERING INFORMATION
Document # SRAM127 REV F
Page 7
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
SIDEBRAZED DUAL IN-LINE PACKAGE
C7
Pkg #
# Pins
28 (400 mil)
Symbol
Min
Max
A
0.115
0.255
b
0.016
0.020
b2
0.045
0.065
C
0.008
0.018
D
1.384
1.416
e
E
eA
0.100 BSC
0.387
0.403
0.400 BSC
L
0.125
0.200
Q
0.015
0.070
S1
0.005
—
S2
0.005
—
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
A
0.120
0.148
A1
0.078
-
b
0.014
0.020
C
0.007
0.011
D
0.700
0.730
e
0.050 BSC
E
0.292
0.300
E1
0.335
0.347
E2
0.262
0.272
Q
0.025
-
Document # SRAM127 REV F
Page 8
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
SOJ SMALL OUTLINE IC PACKAGE
J7
Pkg #
# Pins
28 (400 mil)
Symbol
Min
Max
A
0.128
0.148
A1
0.082
-
b
0.013
0.019
C
0.007
0.013
D
0.720
0.730
e
0.050 BSC
E
0.395
0.405
E1
0.435
0.445
E2
0.362
0.372
Q
0.025
-
Pkg #
L13
# Pins
32
RECTANGULAR LEADLESS CHIP CARRIER
Symbol
Min
Max
A
0.070
0.093
A1
0.054
0.066
B1
0.025
0.031
D
0.442
0.458
D1
0.300 BSC
D2
0.150 BSC
D3
—
0.458
E
0.742
0.758
E1
0.400 BSC
E2
0.200 BSC
E3
e
0.558
0.050 TYP
h
j
L
0.045
0.055
L1
0.045
0.055
L2
0.075
0.095
ND
7
NE
9
Document # SRAM127 REV F
Page 9
P4C1026/P4C1026L - ULTRA HIGH SPEED 256K X 4 STATIC CMOS RAMS
REVISIONS
DOCUMENT NUMBER
SRAM 127
DOCUMENT TITLE
P4C1026/P4C1026L ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAMS
REV
ISSUE DATE
ORIGINATOR
OR
Oct-05
JDB
New Data Sheet
A
Aug-06
JDB
Updated SOJ package information
B
Oct-06
JDB
Added Ceramic DIP, LCC packages and military processing
C
Dec-06
JDB
Added L13 package, removed L12 package
D
Mar-07
JDB
Minor typographic corrections
E
Apr-07
JDB
Corrected LCC pin configuration
F
Jul-15
JDB
Added P4C1026L
Document # SRAM127 REV F
DESCRIPTION OF CHANGE
Page 10